static void i2c_generic_fill_ssdt(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); struct acpi_i2c i2c = { .address = dev->path.i2c.device, .mode_10bit = dev->path.i2c.mode_10bit, .speed = config->speed ? : I2C_SPEED_FAST, .resource = scope, }; if (!dev->enabled || !scope) return; if (!config->hid) { printk(BIOS_ERR, "%s: ERROR: HID required\n", dev_path(dev)); return; } /* Device */ acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); acpigen_write_name_string("_HID", config->hid); acpigen_write_name_integer("_UID", config->uid); acpigen_write_name_string("_DDN", config->desc); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); /* Resources */ acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpi_device_write_i2c(&i2c); acpi_device_write_interrupt(&config->irq); acpigen_write_resourcetemplate_footer(); /* Wake capabilities */ if (config->wake) { acpigen_write_name_integer("_S0W", 4); acpigen_write_PRW(config->wake, 3); } acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), config->desc ? : dev->chip_ops->name, dev_path(dev)); } /* Use name specified in config or build one from I2C address */ static const char *i2c_generic_acpi_name(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; static char name[5]; if (config->name) return name; snprintf(name, sizeof(name), "D%03.3X", dev->path.i2c.device); name[4] = '\0'; return name; } #endif static struct device_operations i2c_generic_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_name = &i2c_generic_acpi_name, .acpi_fill_ssdt_generator = &i2c_generic_fill_ssdt, #endif }; static void i2c_generic_enable(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; /* Check if device is present by reading GPIO */ if (config->device_present_gpio) { int present = gpio_get(config->device_present_gpio); present ^= config->device_present_gpio_invert; printk(BIOS_INFO, "%s is %spresent\n", dev->chip_ops->name, present ? "" : "not "); if (!present) { dev->enabled = 0; return; } } dev->ops = &i2c_generic_ops; } struct chip_operations drivers_i2c_generic_ops = { CHIP_NAME("I2C Device") .enable_dev = &i2c_generic_enable };
*/ if( (vendor != PCI_VENDOR_ID_VIA) || (model != PCI_DEVICE_ID_VIA_8235)) return; printk(BIOS_DEBUG, "Initialising Devices\n"); /* make sure interupt controller is configured before keyboard init */ setup_i8259(); /* enable RTC and ethernet */ regval = pci_read_config8(dev, 0x51); regval |= 0x18; pci_write_config8(dev, 0x51, regval); /* turn on keyboard */ keyboard_on(dev); /* enable USB 1.1 & USB 2.0 - redundant really since we've * already been there - see note above */ regval = pci_read_config8(dev, 0x50); regval &= ~(0x36); pci_write_config8(dev, 0x50, regval); } struct chip_operations southbridge_via_vt8235_ops = { CHIP_NAME("VIA VT8235 Southbridge") .enable_dev = vt8235_enable, };
sb_config->PORTCONFIG[3].PortCfg.PortPresent = dev->enabled; /* * GPP_CFGMODE_X4000: PortA Lanes[3:0] * GPP_CFGMODE_X2200: PortA Lanes[1:0], PortB Lanes[3:2] * GPP_CFGMODE_X2110: PortA Lanes[1:0], PortB Lane2, PortC Lane3 * GPP_CFGMODE_X1111: PortA Lanes0, PortB Lane1, PortC Lane2, PortD Lane3 */ if (sb_config->GppLinkConfig != sb_chip->gpp_configuration) { sb_config->GppLinkConfig = sb_chip->gpp_configuration; } sbPcieGppEarlyInit(sb_config); break; default: break; } /* Special setting ABCFG registers before PCI emulation. */ abSpecialSetBeforePciEnum(sb_config); usbDesertPll(sb_config); //sb_config->StdHeader.Func = SB_BEFORE_PCI_INIT; //AmdSbDispatcher(sb_config); } struct chip_operations southbridge_amd_cimx_wrapper_sb800_ops = { CHIP_NAME("ATI SB800") .enable_dev = sb800_enable, };
static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, }; static struct pnp_info pnp_dev_info[] = { { &ops, PC97307_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffb, 0 }, { 0xffb, 0x4}, }, { &ops, PC97307_KBCM, PNP_IRQ0 }, { &ops, PC97307_RTC, PNP_IO0 | PNP_IRQ0, { 0xfffe, 0}, }, { &ops, PC97307_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xfffa, 0}, }, { &ops, PC97307_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x03fc, 0}, }, { &ops, PC97307_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0xfff8, 0 }, }, { &ops, PC97307_SP1, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 }, }, { &ops, PC97307_GPIO, PNP_IO0, { 0xfff8, 0 } }, { &ops, PC97307_PM, PNP_IO0, { 0xfffe, 0 } }, }; static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc97307_ops = { CHIP_NAME("NSC PC97307 Super I/O") .enable_dev = enable_dev, };
} static void ene_kb3940q_enable_resources(device_t dev) { /* This function avoids an error on serial console. */ } static struct device_operations ops = { .init = ene_kb3940q_init, .read_resources = ene_kb3940q_read_resources, .enable_resources = ene_kb3940q_enable_resources }; static struct pnp_info pnp_dev_info[] = { { &ops, 0, 0, { 0, 0 }, } }; static void enable_dev(device_t dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations ec_quanta_ene_kb3940q_ops = { CHIP_NAME("QUANTA EnE KB3940Q EC") .enable_dev = enable_dev }; #endif /* ! __SMM__ */ #endif /* ! __PRE_RAM__ */
#include <device/device.h> struct chip_operations cpu_intel_socket_rPGA988B_ops = { CHIP_NAME("Socket rPGA988B CPU") };
/* Remote temperature 2 offset (LSB == 0.25C). */ result = smbus_write_byte(adt7463, 0x72, 0x01); /* Set TACH measurements to normal (1/second). */ result = smbus_write_byte(adt7463, 0x78, 0xf0); printk(BIOS_DEBUG, "ADT7463 properly initialized\n"); } static void adt7463_noop(device_t dummy) { } static struct device_operations adt7463_operations = { .read_resources = adt7463_noop, .set_resources = adt7463_noop, .enable_resources = adt7463_noop, .init = adt7463_init, }; static void enable_dev(struct device *dev) { dev->ops = &adt7463_operations; } struct chip_operations drivers_i2c_adt7463_ops = { CHIP_NAME("adt7463") .enable_dev = enable_dev, };
static void nau8825_fill_ssdt(struct device *dev) { struct drivers_i2c_nau8825_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); struct acpi_i2c i2c = { .address = dev->path.i2c.device, .mode_10bit = dev->path.i2c.mode_10bit, .speed = config->bus_speed ? : I2C_SPEED_FAST, .resource = scope, }; struct acpi_dp *dp = NULL; if (!dev->enabled || !scope) return; if (config->sar_threshold_num > NAU8825_MAX_BUTTONS) return; /* Device */ acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); acpigen_write_name_string("_HID", NAU8825_ACPI_HID); acpigen_write_name_integer("_UID", 0); acpigen_write_name_string("_DDN", dev->chip_ops->name); acpigen_write_STA(acpi_device_status(dev)); /* Resources */ acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpi_device_write_i2c(&i2c); acpi_device_write_interrupt(&config->irq); acpigen_write_resourcetemplate_footer(); /* Device Properties */ dp = acpi_dp_new_table("_DSD"); NAU8825_DP_INT("jkdet-enable", config->jkdet_enable); NAU8825_DP_INT("jkdet-pull-enable", config->jkdet_pull_enable); NAU8825_DP_INT("jkdet-pull-up", config->jkdet_pull_up); NAU8825_DP_INT("jkdet-polarity", config->jkdet_polarity); NAU8825_DP_INT("vref-impedance", config->vref_impedance); NAU8825_DP_INT("micbias-voltage", config->micbias_voltage); NAU8825_DP_INT("sar-hysteresis", config->sar_hysteresis); NAU8825_DP_INT("sar-voltage", config->sar_voltage); NAU8825_DP_INT("sar-compare-time", config->sar_compare_time); NAU8825_DP_INT("sar-sampling-time", config->sar_sampling_time); NAU8825_DP_INT("short-key-debounce", config->short_key_debounce); NAU8825_DP_INT("jack-insert-debounce", config->jack_insert_debounce); NAU8825_DP_INT("jack-eject-deboune", config->jack_eject_debounce); NAU8825_DP_INT("sar-threshold-num", config->sar_threshold_num); acpi_dp_add_integer_array(dp, "nuvoton,sar-threshold", config->sar_threshold, config->sar_threshold_num); acpi_dp_write(dp); acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ printk(BIOS_INFO, "%s: %s address 0%xh irq %d\n", acpi_device_path(dev), dev->chip_ops->name, dev->path.i2c.device, config->irq.pin); } static const char *nau8825_acpi_name(const struct device *dev) { return NAU8825_ACPI_NAME; } #endif static struct device_operations nau8825_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_name = &nau8825_acpi_name, .acpi_fill_ssdt_generator = &nau8825_fill_ssdt, #endif }; static void nau8825_enable(struct device *dev) { dev->ops = &nau8825_ops; } struct chip_operations drivers_i2c_nau8825_ops = { CHIP_NAME("Nuvoton NAU8825 Codec") .enable_dev = &nau8825_enable };
#include <console/console.h> #include <device/smbus.h> #include <string.h> #include <uart8250.h> #include <pc80/keyboard.h> #include <stdlib.h> #include "chip.h" #include "lpc47b272.h" /* Forward declarations */ static void enable_dev(device_t dev); static void lpc47b272_init(device_t dev); // static void dump_pnp_device(device_t dev); struct chip_operations superio_smsc_lpc47b272_ops = { CHIP_NAME("SMSC LPC47B272 Super I/O") .enable_dev = enable_dev }; static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = lpc47b272_init, .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { { &ops, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
static struct pnp_info pnp_dev_info[] = { { &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, { &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627EHG_WDTO_PLED, }, { &ops, W83627EHG_ACPI, PNP_IRQ0, }, { &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, {0x07fe, 0}, }, { &ops, W83627EHG_GAME, PNP_IO0, {0x07ff, 0}, }, { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0, 0}, {0x07fe, 4}, }, { &ops, W83627EHG_GPIO1, }, { &ops, W83627EHG_GPIO2, }, { &ops, W83627EHG_GPIO3, }, { &ops, W83627EHG_GPIO4, }, { &ops, W83627EHG_GPIO5, }, { &ops, W83627EHG_GPIO6, }, }; static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_winbond_w83627ehg_ops = { CHIP_NAME("Winbond W83627EHG Super I/O") .enable_dev = enable_dev, };
.read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = it8516e_pm2_init }; static struct pnp_info it8516e_dev_infos[] = { { NULL, IT8516E_LDN_UART1, PNP_IO0 | PNP_IRQ0, { 0x07f8, }, }, { NULL, IT8516E_LDN_UART2, PNP_IO0 | PNP_IRQ0, { 0x07f8, }, }, { NULL, IT8516E_LDN_SWUC, PNP_IO0 | PNP_IRQ0, { 0xff7e0, }, }, { NULL, IT8516E_LDN_MOUSE, PNP_IRQ0, }, { NULL, IT8516E_LDN_KBD, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, { NULL, IT8516E_LDN_SMFI, PNP_IO0 | PNP_IRQ0, { 0xfff0, }, }, { NULL, IT8516E_LDN_BRAM, PNP_IO0 | PNP_IO1, { 0xfffe, }, { 0xfffe, }, }, { NULL, IT8516E_LDN_PM1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, { &it8516e_pm2_ops, IT8516E_LDN_PM2, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, { NULL, IT8516E_LDN_PM3, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x07ff, }, { 0x07ff, }, }, }; static void it8516e_enable(const device_t dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(it8516e_dev_infos), it8516e_dev_infos); } const struct chip_operations ec_kontron_it8516e_ops = { CHIP_NAME("Kontron (Fintec/ITE) IT8516E EC") .enable_dev = it8516e_enable };
break; case IT8705F_MIDI: /* TODO. */ break; } } static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, }; /* TODO: FDC, PP, EC, GPIO, GAME, IR, MIDI. */ static struct pnp_info pnp_dev_info[] = { { &ops, IT8705F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, IT8705F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, }; static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8705f_ops = { CHIP_NAME("ITE IT8705F Super I/O") .enable_dev = enable_dev, };
/* TODO: TOP_MEM2 */ #else uma_memory_size = 0x8000000; /* 128M recommended UMA */ uma_memory_base = 0x38000000; /* 1GB system memory supposed */ #endif set_pcie_dereset(); /* get_ide_dma66(); */ set_thermal_config(); set_gpio40_gfx(); } int add_mainboard_resources(struct lb_memory *mem) { /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ #if (CONFIG_GFXUMA == 1) printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif return 0; } struct chip_operations mainboard_ops = { CHIP_NAME("GIGABYTE MA785GMT-UD2H Mainboard") .enable_dev = ma785gmt_enable, };
} static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, }; static struct pnp_info pnp_dev_info[] = { { &ops, PC8374_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, }, { &ops, PC8374_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, }, { &ops, PC8374_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, { &ops, PC8374_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, PC8374_SWC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, }, { &ops, PC8374_KBCM, PNP_IRQ0, }, { &ops, PC8374_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, { &ops, PC8374_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, }, }; static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc8374_ops = { CHIP_NAME("NSC PC8374 Super I/O") .enable_dev = enable_dev, };
/* * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <device/device.h> struct chip_operations cpu_amd_agesa_family10_ops = { CHIP_NAME("AMD CPU Family 10h") };
} static void cpu_bus_noop(device_t dev) { } static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, .init = cpu_bus_init, .scan_bus = 0, }; static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { dev->ops = &pci_domain_ops; pci_set_method(dev); } else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) { dev->ops = &cpu_bus_ops; } } struct chip_operations northbridge_intel_i440bx_ops = { CHIP_NAME("Intel 82443BX (440BX) Northbridge") .enable_dev = enable_dev, };
#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include "i82801gx.h" #include "sata.h" #if !CONFIG_MMCONF_SUPPORT_DEFAULT #error ICH7 requires CONFIG_MMCONF_SUPPORT_DEFAULT #endif void i82801gx_enable(device_t dev) { u32 reg32; /* Enable SERR */ reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_SERR; pci_write_config32(dev, PCI_COMMAND, reg32); if (dev->path.pci.devfn == PCI_DEVFN(31, 2)) { printk(BIOS_DEBUG, "Set SATA mode early\n"); sata_enable(dev); } } struct chip_operations southbridge_intel_i82801gx_ops = { CHIP_NAME("Intel ICH7/ICH7-M (82801Gx) Series Southbridge") .enable_dev = i82801gx_enable, };
/* ACPI command and data regions */ wilco_ec_resource(dev, 0, CONFIG_EC_BASE_ACPI_DATA, 8); /* Host command and data regions */ wilco_ec_resource(dev, 1, CONFIG_EC_BASE_HOST_DATA, 8); /* Packet region */ wilco_ec_resource(dev, 2, CONFIG_EC_BASE_PACKET, 16); } static struct device_operations ops = { .init = wilco_ec_init, .read_resources = wilco_ec_read_resources, .enable_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, }; static struct pnp_info info[] = { { NULL, 0, 0, 0, } }; static void wilco_ec_enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(info), info); } struct chip_operations ec_google_wilco_ops = { CHIP_NAME("Google Wilco EC") .enable_dev = wilco_ec_enable_dev, };
__func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ #else uma_memory_size = 0x8000000; /* 128M recommended UMA */ uma_memory_base = 0x38000000; /* 1GB system memory supposed */ #endif set_thermal_config(); } int add_mainboard_resources(struct lb_memory *mem) { /* UMA is removed from system memory in the northbridge code, but * in some circumstances we want the memory mentioned as reserved. */ #if (CONFIG_GFXUMA == 1) printk(BIOS_INFO, "uma_memory_base=0x%llx, uma_memory_size=0x%llx \n", uma_memory_base, uma_memory_size); lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif technexion_post_code(LED_MESSAGE_FINISH); return 0; } struct chip_operations mainboard_ops = { CHIP_NAME("TechNexion TIM-5690 Mainboard") .enable_dev = tim5690_enable, };
/* If no Super I/O was found, return. */ if (i == ARRAY_SIZE(logical_device_table)) return; /* Temporarily save the LD_FOO values. */ for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) tmp[j] = pnp_dev_info[j].function; /* * Replace the LD_FOO markers in pnp_dev_info[] with * the real logical device IDs of this Super I/O chip. */ for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) { fn = pnp_dev_info[j].function; pnp_dev_info[j].function = logical_device_table[i].devs[fn]; } /* Enable the specified devices (if present on the chip). */ pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), &pnp_dev_info[0]); /* Restore LD_FOO values. */ for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) pnp_dev_info[j].function = tmp[j]; } struct chip_operations superio_smsc_smscsuperio_ops = { CHIP_NAME("Various SMSC Super I/Os") .enable_dev = enable_dev };
.ops_pci = &ti_pci1x2y_pci_ops, }; static const struct pci_driver ti_pci1225_driver __pci_driver = { .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1225, }; static const struct pci_driver ti_pci1420_driver __pci_driver = { .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1420, }; static const struct pci_driver ti_pci1510_driver __pci_driver = { .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1510, }; static const struct pci_driver ti_pci1520_driver __pci_driver = { .ops = &southbridge_ti_pci1x2x_pciops, .vendor = PCI_VENDOR_ID_TI, .device = PCI_DEVICE_ID_TI_1520, }; struct chip_operations southbridge_ti_pci1x2x_ops = { CHIP_NAME("TI PCI1x2x Cardbus controller") };
break; case 0x20000000: /* 512M system memory */ uma_memory_size = 0x8000000; /* 128M recommended UMA */ break; default: /* 1GB and above system memory */ uma_memory_size = 0x10000000; /* 256M recommended UMA */ break; } uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); /* TODO: TOP_MEM2 */ #else uma_memory_size = 0x8000000; /* 128M recommended UMA */ uma_memory_base = 0x38000000; /* 1GB system memory supposed */ #endif set_pcie_dereset(); /* get_ide_dma66(); */ set_thermal_config(); } struct chip_operations mainboard_ops = { CHIP_NAME("ASUS M4A785-M Mainboard") .enable_dev = m4a785m_enable, };
} static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, .scan_bus = cpu_bus_scan, }; static void northbridge_enable(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; } } struct chip_operations mainboard_emulation_qemu_i440fx_ops = { CHIP_NAME("QEMU Northbridge i440fx") .enable_dev = northbridge_enable, }; struct chip_operations mainboard_emulation_qemu_q35_ops = { CHIP_NAME("QEMU Northbridge q35") .enable_dev = northbridge_enable, };
/* * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <device/device.h> struct chip_operations cpu_amd_agesa_family15_ops = { CHIP_NAME("AMD CPU Family 15h") };
break; case IT8661F_IR: /* TODO. */ break; } } static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_enable, .init = init, }; /* TODO: FDC, PP, IR, GPIO. */ static struct pnp_info pnp_dev_info[] = { { &ops, IT8661F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, IT8661F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, }; static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8661f_ops = { CHIP_NAME("ITE IT8661F Super I/O") .enable_dev = enable_dev, };
.set_resources = f71889_pnp_set_resources, .enable_resources = f71889_pnp_enable_resources, .enable = f71889_pnp_enable, .init = f71889_init, }; static struct pnp_info pnp_dev_info[] = { /* TODO: Some of the 0x07f8 etc. values may not be correct. */ { &ops, F71889_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, F71889_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71889_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71889_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, F71889_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, { &ops, F71889_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, { &ops, F71889_GPIO, }, { &ops, F71889_VID, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71889_SPI, }, { &ops, F71889_PME, }, { &ops, F71889_VREF, }, }; static void enable_dev(device_t dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_fintek_f71889_ops = { CHIP_NAME("Fintek F71889 Super I/O") .enable_dev = enable_dev };
} static void tegra132_init(void *chip_info) { struct tegra_revision rev; tegra_revision_info(&rev); printk(BIOS_INFO, "chip %x rev %02x.%x\n", rev.chip_id, rev.major, rev.minor); printk(BIOS_INFO, "MTS build %u\n", raw_read_aidr_el1()); } struct chip_operations soc_nvidia_tegra132_ops = { CHIP_NAME("SOC Nvidia Tegra132") .init = tegra132_init, .enable_dev = enable_tegra132_dev, }; static void tegra132_cpu_init(device_t cpu) { } static const struct cpu_device_id ids[] = { { 0x4e0f0000 }, { CPU_ID_END }, }; static struct device_operations cpu_dev_ops = { .init = tegra132_cpu_init, };
static struct device_operations ops = { .read_resources = pnp_read_resources, .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, .enable = pnp_alt_enable, .init = f81865f_init, .ops_pnp_mode = &pnp_conf_mode_8787_aa, }; static struct pnp_info pnp_dev_info[] = { /* TODO: Some of the 0x7f8 etc. values may not be correct. */ { &ops, F81865F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, { &ops, F81865F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, F81865F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, { &ops, F81865F_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x07ff, 0}, }, { &ops, F81865F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, { &ops, F81865F_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, }, { &ops, F81865F_GPIO, PNP_IRQ0, }, { &ops, F81865F_PME, }, }; static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_fintek_f81865f_ops = { CHIP_NAME("Fintek F81865F Super I/O") .enable_dev = enable_dev };
res->limit = 0xffffUL; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } static struct device_operations southbridge_ops = { .read_resources = cs5535_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = southbridge_init, .enable = southbridge_enable, }; static const struct pci_driver cs5535_pci_driver __pci_driver = { .ops = &southbridge_ops, .vendor = PCI_VENDOR_ID_NS, .device = PCI_DEVICE_ID_NS_CS5535 }; struct chip_operations southbridge_amd_cs5535_ops = { CHIP_NAME("AMD Geode CS5535 Southbridge") /* This is only called when this device is listed in the * static device tree. */ .enable_dev = southbridge_enable, };
.enable = pnp_alt_enable, .init = lpc47m10x_init, .ops_pnp_mode = &pnp_conf_mode_55_aa, }; static struct pnp_info pnp_dev_info[] = { { &ops, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, { &ops, LPC47M10X2_PME, PNP_IO0, { 0x0f80, 0 }, }, }; /** * Create device structures and allocate resources to devices specified in the * pnp_dev_info array (above). * * @param dev Pointer to structure describing a Super I/O device. */ static void enable_dev(struct device *dev) { pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_smsc_lpc47m10x_ops = { CHIP_NAME("SMSC LPC47M10x Super I/O") .enable_dev = enable_dev };