void HAL_USBDeInit(uint8_t corenum, uint8_t mode)
{
HAL_DisableUSBInterrupt(corenum);
if (mode == USB_MODE_Device) {
#if defined(USB_CAN_BE_HOST)
USB_REG(corenum)->USBSTS_H = 0xFFFFFFFF; /* clear all current interrupts */
USB_REG(corenum)->PORTSC1_H &= ~(1 << 12); /* clear port power */
USB_REG(corenum)->USBMODE_H = (1 << 0); /* set USB mode reserve */
#endif
}
else if (mode == USB_MODE_Host) {
#if defined(USB_CAN_BE_DEVICE)
/* Clear all pending interrupts */
USB_REG(corenum)->USBSTS_D = 0xFFFFFFFF;
USB_REG(corenum)->ENDPTNAK = 0xFFFFFFFF;
USB_REG(corenum)->ENDPTNAKEN = 0;
USB_REG(corenum)->ENDPTSETUPSTAT = USB_REG(corenum)->ENDPTSETUPSTAT;
USB_REG(corenum)->ENDPTCOMPLETE = USB_REG(corenum)->ENDPTCOMPLETE;
while (USB_REG(corenum)->ENDPTPRIME) ; /* Wait until all bits are 0 */
USB_REG(corenum)->ENDPTFLUSH = 0xFFFFFFFF;
while (USB_REG(corenum)->ENDPTFLUSH) ; /* Wait until all bits are 0 */
#endif
}
/* Disable USB PHY if both USB cores are disabled */
if (coreEnabled[1 - corenum]) {
/* Turn off the phy (prior to PLL disabled) */
Chip_CREG_EnableUSB0Phy(false);
}
/* Power down USB clocking */
if (corenum == 0) {
Chip_Clock_Disable(CLK_MX_USB0);
Chip_Clock_DisableBaseClock(CLK_BASE_USB0);
}
else {
Chip_Clock_Disable(CLK_MX_USB1);
Chip_Clock_DisableBaseClock(CLK_BASE_USB1);
}
/* Disable USB PLL if both USB cores are disabled */
if (coreEnabled[1 - corenum]) {
/* Disable USB PLL */
Chip_Clock_DisablePLL(CGU_USB_PLL);
}
coreEnabled[corenum] = false;
}
/* De-initializes the UARTx peripheral */
void Chip_UART_DeInit(LPC_USART_Type *UARTx)
{
UART_ID_Type UARTPort = Chip_UART_Get_UARTNum(UARTx);
IP_UART_DeInit(UARTx, UARTPort);
/* Disable UART clocking */
Chip_Clock_Disable(Chip_UART_DetermineClk(UARTx));
}
/* Shutdown I2S */
void Chip_I2S_DeInit(LPC_I2S_Type *pI2S)
{
IP_I2S_DeInit(pI2S);
clksEnabled--;
if (clksEnabled == 0) {
Chip_Clock_Disable(CLK_APB1_I2S);
}
}
/* Shutdown I2S */
void Chip_I2S_DeInit(LPC_I2S_T *pI2S)
{
pI2S->DAI = 0x07E1;
pI2S->DAO = 0x87E1;
pI2S->IRQ = 0;
pI2S->TXMODE = 0;
pI2S->RXMODE = 0;
pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_1] = 0;
pI2S->DMA[I2S_DMA_REQUEST_CHANNEL_2] = 0;
Chip_Clock_Disable(CLK_APB1_I2S);
}
/* Shutdown ADC */
void Chip_HSADC_DeInit(LPC_HSADC_T *pHSADC)
{
/* Power down */
Chip_HSADC_DisablePower(pHSADC);
/* Reset HSADC and wait for clear, will auto-clear */
Chip_RGU_TriggerReset(RGU_ADCHS_RST);
while (Chip_RGU_InReset(RGU_ADCHS_RST)) {}
/* SHutdown HSADC clock after reset is complete */
Chip_Clock_Disable(CLK_MX_ADCHS);
}
/* Ethernet interface shutdown */
void Chip_ENET_DeInit(LPC_ENET_T *pENET)
{
/* Disable packet reception */
pENET->MAC_CONFIG = 0;
/* Flush transmit FIFO */
pENET->DMA_OP_MODE = DMA_OM_FTF;
/* Disable receive and transmit DMA processes */
pENET->DMA_OP_MODE = 0;
Chip_Clock_Disable(CLK_MX_ETHERNET);
}
/* Ethernet interface shutdown */
void Chip_ENET_DeInit(void)
{
IP_ENET_DeInit(LPC_ETHERNET);
Chip_Clock_Disable(CLK_MX_ETHERNET);
}
/* Shutdown DAC */
void Chip_DAC_DeInit(LPC_DAC_T *pDAC)
{
Chip_Clock_Disable(CLK_APB3_DAC);
}
/* Shutdown SCT */
void Chip_SCT_DeInit(LPC_SCT_T *pSCT)
{
Chip_Clock_Disable(CLK_MX_SCT);
}
/* De-initializes the SSP peripheral */
void Chip_SSP_DeInit(LPC_SSP_T *pSSP)
{
Chip_SSP_Disable(pSSP);
Chip_Clock_Disable(Chip_SSP_GetClockIndex(pSSP));
}
/* Shutdown the LCD controller */
void Chip_LCD_DeInit(LPC_LCD_T *pLCD)
{
Chip_Clock_Disable(CLK_MX_LCD);
}
/* Shutdown SCT */
void Chip_SCT_DeInit(void)
{
Chip_Clock_Disable(CLK_MX_SCT);
}
/* Shutdown ADC */
void Chip_ADC_DeInit(LPC_ADC_T *pADC)
{
pADC->INTEN = 0x00000100;
pADC->CR = 0;
Chip_Clock_Disable(Chip_ADC_GetClockIndex(pADC));
}
/* Shutdown a timer */
void Chip_TIMER_DeInit(LPC_TIMER_T *pTMR)
{
Chip_Clock_Disable(Chip_Timer_GetClock(pTMR));
}
/* Shutdown the SD/MMC controller */
void Chip_SDIF_DeInit(LPC_SDMMC_T *pSDMMC)
{
IP_SDMMC_DeInit(pSDMMC);
Chip_Clock_Disable(CLK_MX_SDIO);
}
/* DeInitialize the RIT */
void Chip_RIT_DeInit(LPC_RITIMER_T *pRITimer)
{
Chip_RIT_Init(pRITimer);
Chip_Clock_Disable(CLK_MX_RITIMER);
}
/* Shutdown the GPDMA */
void Chip_GPDMA_DeInit(LPC_GPDMA_T *pGPDMA)
{
Chip_Clock_Disable(CLK_MX_DMA);
}