/** * @brief Polling for transfer complete. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @param CompleteLevel: Specifies the DMA level complete. * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) { uint32_t temp, tmp, tmp1, tmp2; uint32_t tickstart = 0; /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Transfer Complete flag */ temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); } else { /* Half Transfer Complete flag */ temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); } /* Get tick */ tickstart = HAL_GetTick(); while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) { tmp = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); tmp1 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); tmp2 = __HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); if((tmp != RESET) || (tmp1 != RESET) || (tmp2 != RESET)) { if(tmp != RESET) { /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; /* Clear the transfer error flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); } if(tmp1 != RESET) { /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; /* Clear the FIFO error flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma)); } if(tmp2 != RESET) { /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; /* Clear the Direct Mode error flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma)); } /* Change the DMA state */ hdma->State= HAL_DMA_STATE_ERROR; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_TIMEOUT; } } } if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) { /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == 0) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_READY_MEM0; } /* Current memory buffer used is Memory 1 */ else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_READY_MEM1; } } else { /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); /* The selected Streamx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY_MEM0; } /* Process Unlocked */ __HAL_UNLOCK(hdma); } else { /* Multi_Buffering mode enabled */ if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != 0) { /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); /* Current memory buffer used is Memory 0 */ if((hdma->Instance->CR & DMA_SxCR_CT) == 0) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; } /* Current memory buffer used is Memory 1 */ else if((hdma->Instance->CR & DMA_SxCR_CT) != 0) { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_READY_HALF_MEM1; } } else { /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_READY_HALF_MEM0; } } return HAL_OK; }
/** * @brief EXTI line detection callbacks. * @param GPIO_Pin: Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { static JOYState_TypeDef JoyState = JOY_NONE; static uint32_t debounce_time = 0; if(GPIO_Pin == GPIO_PIN_2) { /* Get the Joystick State */ JoyState = BSP_JOY_GetState(); /* Clear joystick interrupt pending bits */ BSP_IO_ITClear(JOY_ALL_PINS); if(audio_select_mode == AUDIO_SELECT_MENU) { AUDIO_MenuProbeKey(JoyState); switch(JoyState) { case JOY_LEFT: LCD_LOG_ScrollBack(); break; case JOY_RIGHT: LCD_LOG_ScrollForward(); break; default: break; } } else if(audio_select_mode == AUDIO_PLAYBACK_CONTROL) { AUDIO_PlaybackProbeKey(JoyState); } } if(audio_demo.state == AUDIO_DEMO_PLAYBACK) { if(GPIO_Pin == KEY_BUTTON_PIN) { /* Prevent debounce effect for user key */ if((HAL_GetTick() - debounce_time) > 50) { debounce_time = HAL_GetTick(); } else { return; } /* Change the selection type */ if(audio_select_mode == AUDIO_SELECT_MENU) { Audio_ChangeSelectMode(AUDIO_PLAYBACK_CONTROL); } else if(audio_select_mode == AUDIO_PLAYBACK_CONTROL) { Audio_ChangeSelectMode(AUDIO_SELECT_MENU); } } } }
/** * @brief Initiates and transmits a CAN frame message. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @param Timeout: Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout) { uint32_t transmitmailbox = 5U; uint32_t tickstart = 0U; /* Check the parameters */ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE)); assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR)); assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC)); if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)) { /* Process locked */ __HAL_LOCK(hcan); if(hcan->State == HAL_CAN_STATE_BUSY_RX) { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_TX_RX; } else { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_TX; } /* Select one empty transmit mailbox */ if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) { transmitmailbox = 0U; } else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) { transmitmailbox = 1U; } else { transmitmailbox = 2U; } /* Set up the Id */ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ; if (hcan->pTxMsg->IDE == CAN_ID_STD) { assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId)); hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \ hcan->pTxMsg->RTR); } else { assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId)); hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \ hcan->pTxMsg->IDE | \ hcan->pTxMsg->RTR); } /* Set up the DLC */ hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU; hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U; hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC; /* Set up the data field */ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) | ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) | ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) | ((uint32_t)hcan->pTxMsg->Data[0U])); hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) | ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) | ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) | ((uint32_t)hcan->pTxMsg->Data[4U])); /* Request transmission */ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ; /* Get tick */ tickstart = HAL_GetTick(); /* Check End of transmission flag */ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox))) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { hcan->State = HAL_CAN_STATE_TIMEOUT; /* Process unlocked */ __HAL_UNLOCK(hcan); return HAL_TIMEOUT; } } } if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX) { /* Change CAN state */ hcan->State = HAL_CAN_STATE_BUSY_RX; } else { /* Change CAN state */ hcan->State = HAL_CAN_STATE_READY; } /* Process unlocked */ __HAL_UNLOCK(hcan); /* Return function status */ return HAL_OK; } else { /* Change CAN state */ hcan->State = HAL_CAN_STATE_ERROR; /* Return function status */ return HAL_ERROR; } }
/** * @brief Write Spare area(s) to NAND memory * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress : pointer to NAND address structure * @param pBuffer : pointer to source buffer to write * @param NumSpareAreaTowrite : number of spare areas to write to block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { __IO uint32_t index = 0; uint32_t tickstart = 0; uint32_t deviceAddress = 0, numSpareAreaWritten = 0, nandAddress = 0, addressStatus = NAND_VALID_ADDRESS; /* Process Locked */ __HAL_LOCK(hnand); /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } /* Identify the device address */ if(hnand->Init.NandBank == FMC_NAND_BANK2) { deviceAddress = NAND_DEVICE1; } else { deviceAddress = NAND_DEVICE2; } /* Update the FMC_NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; /* Spare area(s) write loop */ while((NumSpareAreaTowrite != 0) && (addressStatus == NAND_VALID_ADDRESS)) { /* NAND raw address calculation */ nandAddress = __ARRAY_ADDRESS(pAddress, hnand); /* Send write Spare area command sequence */ *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C; *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0; *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00; *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_1st_CYCLE(nandAddress); *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_2nd_CYCLE(nandAddress); *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_3rd_CYCLE(nandAddress); /* for 512 and 1 GB devices, 4th cycle is required */ if(hnand->Info.BlockNbr >= 1024) { *(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = __ADDR_4th_CYCLE(nandAddress); } /* Write data to memory */ for(index = 0 ; index < hnand->Info.SpareAreaSize; index++) { *(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++; } *(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; /* Read status until NAND is ready */ while(HAL_NAND_Read_Status(hnand) != NAND_READY) { /* Get tick */ tickstart = HAL_GetTick(); if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) { return HAL_TIMEOUT; } } /* Increment written spare areas number */ numSpareAreaWritten++; /* Decrement spare areas to write */ NumSpareAreaTowrite--; /* Increment the NAND address */ HAL_NAND_Address_Inc(hnand, pAddress); } /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hnand); return HAL_OK; }
/** * @brief Receive an amount of data (Control Flow) with Interrupt * @param hspdif: SPDIFRX handle * @param pData: a 32-bit pointer to the Receive data buffer. * @param Size: number of data sample (Control Flow) to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) { uint32_t tickstart = 0U; if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX)) { if((pData == NULL ) || (Size == 0U)) { return HAL_ERROR; } /* Process Locked */ __HAL_LOCK(hspdif); hspdif->pCsBuffPtr = pData; hspdif->CsXferSize = Size; hspdif->CsXferCount = Size; hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; /* Check if a receive process is ongoing or not */ hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX; /* Enable the SPDIFRX PE Error Interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_PERRIE); /* Enable the SPDIFRX OVR Error Interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_OVRIE); /* Process Unlocked */ __HAL_UNLOCK(hspdif); /* Enable the SPDIFRX CSRNE interrupt */ __HAL_SPDIFRX_ENABLE_IT(hspdif, SPDIFRX_IT_CSRNE); if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); /* Get tick */ tickstart = HAL_GetTick(); /* Wait until SYNCD flag is set */ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK) { return HAL_TIMEOUT; } /* Start reception */ __HAL_SPDIFRX_RCV(hspdif); } return HAL_OK; } else { return HAL_BUSY; } }
/** * @brief Handle BatteryCharging Process. * @param hpcd: PCD handle * @retval HAL status */ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) { USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; uint32_t tickstart = HAL_GetTick(); /* Start BCD When device is connected */ if (USBx_DEVICE->DCTL & USB_OTG_DCTL_SDIS) { /* Enable DCD : Data Contact Detect */ USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; /* Wait Detect flag or a timeout is happen*/ while ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == 0) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > 1000) { HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); return; } } /* Right response got */ HAL_Delay(100); /* Check Detect flag*/ if (USBx->GCCFG & USB_OTG_GCCFG_DCDET) { HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); } /*Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ USBx->GCCFG &=~ USB_OTG_GCCFG_DCDEN; USBx->GCCFG |= USB_OTG_GCCFG_PDEN; HAL_Delay(100); if (!(USBx->GCCFG & USB_OTG_GCCFG_PDET)) { /* Case of Standard Downstream Port */ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); } else { /* start secondary detection to check connection to Charging Downstream Port or Dedicated Charging Port */ USBx->GCCFG &=~ USB_OTG_GCCFG_PDEN; USBx->GCCFG |= USB_OTG_GCCFG_SDEN; HAL_Delay(100); if ((USBx->GCCFG) & USB_OTG_GCCFG_SDET) { /* case Dedicated Charging Port */ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); } else { /* case Charging Downstream Port */ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); } } /* Battery Charging capability discovery finished */ HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); } }
/** * @brief Polling for transfer complete. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @param CompleteLevel: Specifies the DMA level complete. * @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead. * This model could be used for debug purpose. * @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode). * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) { HAL_StatusTypeDef status = HAL_OK; uint32_t temp; uint32_t tickstart = HAL_GetTick(); uint32_t tmpisr; /* calculate DMA base and stream number */ DMA_Base_Registers *regs; /* Polling mode not supported in circular mode and double buffering mode */ if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) { hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; return HAL_ERROR; } /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Transfer Complete flag */ temp = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; } else { /* Half Transfer Complete flag */ temp = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; } regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; tmpisr = regs->ISR; while((tmpisr & temp) == RESET ) { /* Check for the Timeout (Not applicable in circular mode)*/ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; return HAL_TIMEOUT; } } if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) { /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_TE; /* Clear the transfer error flag */ regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; } if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) { /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_FE; /* Clear the FIFO error flag */ regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; } if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) { /* Update error code */ hdma->ErrorCode |= HAL_DMA_ERROR_DME; /* Clear the Direct Mode error flag */ regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; } } if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) { if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) { HAL_DMA_Abort(hdma); /* Clear the half transfer and transfer complete flags */ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; /* Process Unlocked */ __HAL_UNLOCK(hdma); /* Change the DMA state */ hdma->State= HAL_DMA_STATE_READY; return HAL_ERROR; } status = HAL_ERROR; } /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Clear the half transfer and transfer complete flags */ regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; /* Process Unlocked */ __HAL_UNLOCK(hdma); hdma->State = HAL_DMA_STATE_READY; } else { /* Clear the half transfer and transfer complete flags */ regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; } return status; }
/** * @brief NAND memory Block erase * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress: pointer to NAND address structure * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress) { uint32_t deviceaddress = 0; uint32_t tickstart = 0; /* Process Locked */ __HAL_LOCK(hnand); /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } /* Identify the device address */ if(hnand->Init.NandBank == FMC_NAND_BANK2) { deviceaddress = NAND_DEVICE1; } else { deviceaddress = NAND_DEVICE2; } /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; /* Send Erase block command sequence */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE0; *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); /* for 512 and 1 GB devices, 4th cycle is required */ if(hnand->Info.BlockNbr >= 1024) { *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(ARRAY_ADDRESS(pAddress, hnand)); } *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_ERASE1; /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; /* Get tick */ tickstart = HAL_GetTick(); /* Read status until NAND is ready */ while(HAL_NAND_Read_Status(hnand) != NAND_READY) { if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) { /* Process unlocked */ __HAL_UNLOCK(hnand); return HAL_TIMEOUT; } } /* Process unlocked */ __HAL_UNLOCK(hnand); return HAL_OK; }
/** * @brief Polling for transfer complete. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CompleteLevel: Specifies the DMA level complete. * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) { uint32_t temp; uint32_t tickstart = 0x00; /* Get the level transfer complete flag */ if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Transfer Complete flag */ temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma); } else { /* Half Transfer Complete flag */ temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma); } /* Get tick */ tickstart = HAL_GetTick(); while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET) { if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)) { /* Clear the transfer error flags */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)); /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE); /* Change the DMA state */ hdma->State= HAL_DMA_STATE_ERROR; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update error code */ SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT); /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_TIMEOUT; } } } if(CompleteLevel == HAL_DMA_FULL_TRANSFER) { /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)); /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY; } else { /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)); /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers of half buffer are complete) */ hdma->State = HAL_DMA_STATE_READY_HALF; } /* Process unlocked */ __HAL_UNLOCK(hdma); return HAL_OK; }
/** * @brief Polling for transfer complete. * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @param CompleteLevel: Specifies the DMA level complete. * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout) { uint32_t temp; uint32_t tickstart = 0; if(HAL_DMA_STATE_BUSY != hdma->State) { /* no transfer ongoing */ hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; return HAL_ERROR; } /* Polling mode not supported in circular mode */ if (RESET != (hdma->Instance->CCR & DMA_CCR_CIRC)) { hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; return HAL_ERROR; } /* Get the level transfer complete flag */ if (HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Transfer Complete flag */ temp = DMA_FLAG_TC1 << hdma->ChannelIndex; } else { /* Half Transfer Complete flag */ temp = DMA_FLAG_HT1 << hdma->ChannelIndex; } /* Get tick */ tickstart = HAL_GetTick(); while(RESET == (hdma->DmaBaseAddress->ISR & temp)) { if((RESET != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << hdma->ChannelIndex)))) { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Clear all flags */ hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; /* Change the DMA state */ hdma->State= HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hdma); return HAL_ERROR; } } } if(HAL_DMA_FULL_TRANSFER == CompleteLevel) { /* Clear the transfer complete flag */ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << hdma->ChannelIndex); /* The selected Channelx EN bit is cleared (DMA is disabled and all transfers are complete) */ hdma->State = HAL_DMA_STATE_READY; } else { /* Clear the half transfer complete flag */ hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << hdma->ChannelIndex); } /* Process unlocked */ __HAL_UNLOCK(hdma); return HAL_OK; }
/** * @brief Write Spare area(s) to NAND memory * @param hnand: pointer to a NAND_HandleTypeDef structure that contains * the configuration information for NAND module. * @param pAddress: pointer to NAND address structure * @param pBuffer: pointer to source buffer to write * @param NumSpareAreaTowrite: number of spare areas to write to block * @retval HAL status */ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite) { __IO uint32_t index = 0; uint32_t tickstart = 0; uint32_t deviceaddress = 0, size = 0, num_spare_area_written = 0, addressstatus = NAND_VALID_ADDRESS; NAND_AddressTypeDef nandaddress; uint32_t addressoffset = 0; /* Process Locked */ __HAL_LOCK(hnand); /* Check the NAND controller state */ if(hnand->State == HAL_NAND_STATE_BUSY) { return HAL_BUSY; } /* Identify the device address */ if(hnand->Init.NandBank == FMC_NAND_BANK2) { deviceaddress = NAND_DEVICE1; } else { deviceaddress = NAND_DEVICE2; } /* Update the FMC_NAND controller state */ hnand->State = HAL_NAND_STATE_BUSY; /* Save the content of pAddress as it will be modified */ nandaddress.Block = pAddress->Block; nandaddress.Page = pAddress->Page; nandaddress.Zone = pAddress->Zone; /* Spare area(s) write loop */ while((NumSpareAreaTowrite != 0) && (addressstatus == NAND_VALID_ADDRESS)) { /* update the buffer size */ size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * num_spare_area_written); /* Get the address offset */ addressoffset = ARRAY_ADDRESS(&nandaddress, hnand); /* Send write Spare area command sequence */ *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_AREA_C; *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE0; *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = 0x00; *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_1ST_CYCLE(addressoffset); *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_2ND_CYCLE(addressoffset); *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_3RD_CYCLE(addressoffset); /* for 512 and 1 GB devices, 4th cycle is required */ if(hnand->Info.BlockNbr >= 1024) { *(__IO uint8_t *)((uint32_t)(deviceaddress | ADDR_AREA)) = ADDR_4TH_CYCLE(addressoffset); } /* Write data to memory */ for(; index < size; index++) { *(__IO uint8_t *)deviceaddress = *(uint8_t *)pBuffer++; } *(__IO uint8_t *)((uint32_t)(deviceaddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1; /* Get tick */ tickstart = HAL_GetTick(); /* Read status until NAND is ready */ while(HAL_NAND_Read_Status(hnand) != NAND_READY) { if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT) { return HAL_TIMEOUT; } } /* Increment written spare areas number */ num_spare_area_written++; /* Decrement spare areas to write */ NumSpareAreaTowrite--; /* Increment the NAND address */ addressstatus = NAND_AddressIncrement(hnand, &nandaddress); } /* Update the NAND controller state */ hnand->State = HAL_NAND_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hnand); return HAL_OK; }
/** * @brief Configures the selected DAC channel. * @param hdac: pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @param sConfig: DAC configuration structure. * @param Channel: The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) { uint32_t tmpreg1 = 0, tmpreg2 = 0; uint32_t tickstart = 0; /* Check the DAC parameters */ assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral)); assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming)); if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER) { assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue)); } assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold)); if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE) { assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime)); assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); } assert_param(IS_DAC_CHANNEL(Channel)); /* Process locked */ __HAL_LOCK(hdac); /* Change DAC state */ hdac->State = HAL_DAC_STATE_BUSY; if(sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) /* Sample on old configuration */ { /* SampleTime */ if (Channel == DAC_CHANNEL_1) { /* Get timeout */ tickstart = HAL_GetTick(); /* SHSR1 can be written when BWST1 equals RESET */ while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; return HAL_TIMEOUT; } } HAL_Delay(1); hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } else /* Channel 2 */ { /* SHSR2 can be written when BWST2 equals RESET */ while (((hdac->Instance->SR) & DAC_SR_BWST2)!= RESET) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) { /* Update error code */ SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); /* Change the DMA state */ hdac->State = HAL_DAC_STATE_TIMEOUT; return HAL_TIMEOUT; } } HAL_Delay(1); hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; } /* HoldTime */ hdac->Instance->SHHR = (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)<<Channel; /* RefreshTime */ hdac->Instance->SHRR = (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)<<Channel; } if(sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) /* USER TRIMMING */ { /* Get the DAC CCR value */ tmpreg1 = hdac->Instance->CCR; /* Clear trimming value */ tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << Channel); /* Configure for the selected trimming offset */ tmpreg2 = sConfig->DAC_TrimmingValue; /* Calculate CCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << Channel; /* Write to DAC CCR */ hdac->Instance->CCR = tmpreg1; } /* else factory trimming is used (factory setting are available at reset)*/ /* SW Nothing has nothing to do */ /* Get the DAC MCR value */ tmpreg1 = hdac->Instance->MCR; /* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */ tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel); /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral); /* Calculate MCR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << Channel; /* Write to DAC MCR */ hdac->Instance->MCR = tmpreg1; /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel); /* Get the DAC CR value */ tmpreg1 = hdac->Instance->CR; /* Clear TENx, TSELx, WAVEx and MAMPx bits */ tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel); /* Configure for the selected DAC channel: trigger */ /* Set TSELx and TENx bits according to DAC_Trigger value */ tmpreg2 = (sConfig->DAC_Trigger); /* Calculate CR register value depending on DAC_Channel */ tmpreg1 |= tmpreg2 << Channel; /* Write to DAC CR */ hdac->Instance->CR = tmpreg1; /* Disable wave generation */ hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel); /* Change DAC state */ hdac->State = HAL_DAC_STATE_READY; /* Process unlocked */ __HAL_UNLOCK(hdac); /* Return function status */ return HAL_OK; }
/** * @brief Wait for injected group conversion to be completed. * @param hadc: ADC handle * @param Timeout: Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) { uint32_t tickstart; /* Variables for polling in case of scan mode enabled and polling for each */ /* conversion. */ __IO uint32_t Conversion_Timeout_CPU_cycles = 0; uint32_t Conversion_Timeout_CPU_cycles_max = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Get timeout */ tickstart = HAL_GetTick(); /* Polling for end of conversion: differentiation if single/sequence */ /* conversion. */ /* For injected group, flag JEOC is set only at the end of the sequence, */ /* not for each conversion within the sequence. */ /* - If single conversion for injected group (scan mode disabled or */ /* InjectedNbrOfConversion ==1), flag jEOC is used to determine the */ /* conversion completion. */ /* - If sequence conversion for injected group (scan mode enabled and */ /* InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */ /* sequence. */ /* To poll for each conversion, the maximum conversion time is computed */ /* from ADC conversion time (selected sampling time + conversion time of */ /* 12.5 ADC clock cycles) and APB2/ADC clock prescalers (depending on */ /* settings, conversion time range can be from 28 to 32256 CPU cycles). */ if ((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) { /* Wait until End of Conversion flag is raised */ while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC)) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout)) { /* Update ADC state machine to timeout */ hadc->State = HAL_ADC_STATE_TIMEOUT; /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } } } else { /* Poll with maximum conversion time */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles */ /* and ADC maximum conversion cycles on all channels. */ /* - Wait for the expected ADC clock cycles delay */ Conversion_Timeout_CPU_cycles_max = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_CONVCYCLES_MAX_RANGE(hadc) ); while(Conversion_Timeout_CPU_cycles < Conversion_Timeout_CPU_cycles_max) { /* Check if timeout is disabled (set to infinite wait) */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Update ADC state machine to timeout */ hadc->State = HAL_ADC_STATE_TIMEOUT; /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } Conversion_Timeout_CPU_cycles ++; } } /* Clear injected group conversion flag (and regular conversion flag raised */ /* simultaneously) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC | ADC_FLAG_EOC); /* Update state machine on conversion status if not in error state */ if(hadc->State != HAL_ADC_STATE_ERROR) { /* Update ADC state machine */ if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG) { if(hadc->State == HAL_ADC_STATE_EOC_REG) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_EOC_INJ_REG; } else { /* Change ADC state */ hadc->State = HAL_ADC_STATE_EOC_INJ; } } } /* Return ADC state */ return HAL_OK; }
/** * @brief Perform an ADC automatic self-calibration * Calibration prerequisite: ADC must be disabled (execute this * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). * During calibration process, ADC is enabled. ADC is let enabled at * the completion of this function. * @param hadc: ADC handle * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; uint32_t tickstart; __IO uint32_t wait_loop_index = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); /* Process locked */ __HAL_LOCK(hadc); /* 1. Calibration prerequisite: */ /* - ADC must be disabled for at least two ADC clock cycles in disable */ /* mode before ADC enable */ /* Stop potential conversion on going, on regular and injected groups */ /* Disable ADC peripheral */ tmp_hal_status = ADC_ConversionStop_Disable(hadc); /* Check if ADC is effectively disabled */ if (tmp_hal_status != HAL_ERROR) { /* Hardware prerequisite: delay before starting the calibration. */ /* - Computation of CPU clock cycles corresponding to ADC clock cycles. */ /* - Wait for the expected ADC clock cycles delay */ wait_loop_index = ((SystemCoreClock / HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC)) * ADC_PRECALIBRATION_DELAY_ADCCLOCKCYCLES ); while(wait_loop_index != 0) { wait_loop_index--; } /* 2. Enable the ADC peripheral */ ADC_Enable(hadc); /* 3. Resets ADC calibration registers */ SET_BIT(hadc->Instance->CR2, ADC_CR2_RSTCAL); tickstart = HAL_GetTick(); /* Wait for calibration reset completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_RSTCAL)) { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ hadc->State = HAL_ADC_STATE_ERROR; /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } /* 4. Start ADC calibration */ SET_BIT(hadc->Instance->CR2, ADC_CR2_CAL); tickstart = HAL_GetTick(); /* Wait for calibration completion */ while(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_CAL)) { if((HAL_GetTick() - tickstart) > ADC_CALIBRATION_TIMEOUT) { /* Update ADC state machine to error */ hadc->State = HAL_ADC_STATE_ERROR; /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; }
/** * @brief Receive data in blocking mode. * @param hcec: CEC handle * @param pData: pointer to received data buffer. * @param Timeout: Timeout duration. * @note The received data size is not known beforehand, the latter is known * when the reception is complete and is stored in hcec->RxXferSize. * hcec->RxXferSize is the sum of opcodes + operands (0 to 14 operands max). * If only a header is received, hcec->RxXferSize = 0 * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout) { uint32_t temp = 0; uint32_t tickstart = 0; if(hcec->State == HAL_CEC_STATE_READY) { if(pData == NULL) { return HAL_ERROR; } /* When a ping is received, RxXferSize is 0*/ /* When a message is received, RxXferSize contains the number of received bytes */ hcec->RxXferSize = CEC_RXXFERSIZE_INITIALIZE; /* Process Locked */ __HAL_LOCK(hcec); hcec->ErrorCode = HAL_CEC_ERROR_NONE; /* Continue the reception until the End Of Message is received (CEC_FLAG_REOM) */ do { /* Timeout handling */ tickstart = HAL_GetTick(); /* Wait for next byte to be received */ while (HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_RBTF)) { /* Timeout handling */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { hcec->State = HAL_CEC_STATE_READY; __HAL_UNLOCK(hcec); return HAL_TIMEOUT; } } /* Check if an error occured during the reception */ if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR)) { /* Copy ESR for error handling purposes */ hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR); /* Acknowledgement of the error */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR); hcec->State = HAL_CEC_STATE_READY; __HAL_UNLOCK(hcec); return HAL_ERROR; } } /* Keep the value of CSR register as the register is cleared during reception process */ temp = hcec->Instance->CSR; /* Read received data */ *pData++ = hcec->Instance->RXD; /* Acknowledge received byte by writing 0x00 */ CLEAR_BIT(hcec->Instance->CSR, CEC_FLAG_RECEIVE_MASK); /* Increment the number of received data */ if(hcec->RxXferSize == CEC_RXXFERSIZE_INITIALIZE) { hcec->RxXferSize = 0; } else { hcec->RxXferSize++; } }while (HAL_IS_BIT_CLR(temp, CEC_FLAG_REOM)); hcec->State = HAL_CEC_STATE_READY; __HAL_UNLOCK(hcec); if(IS_CEC_MSGSIZE(hcec->RxXferSize)) { return HAL_OK; } else { return HAL_ERROR; } } else { return HAL_BUSY; } }
void pin_test(void) { uint32_t pin_counts[32] = { 0 }; uint32_t data; uint32_t count = 0; USB_printf("************* sampling...\r\n"); while (1) { // ZX_D0..ZX_D7 data = GPIOB->IDR; if (data & 1) pin_counts[0]++; if (data & 2) pin_counts[1]++; if (data & 4) pin_counts[2]++; if (data & 8) pin_counts[3]++; if (data & 16) pin_counts[4]++; if (data & 32) pin_counts[5]++; if (data & 64) pin_counts[6]++; if (data & 128) pin_counts[7]++; // ZX_A0..ZX_A15 data = GPIOE->IDR; if (data & 1) pin_counts[8]++; if (data & 2) pin_counts[9]++; if (data & 4) pin_counts[10]++; if (data & 8) pin_counts[11]++; if (data & 16) pin_counts[12]++; if (data & 32) pin_counts[13]++; if (data & 64) pin_counts[14]++; if (data & 128) pin_counts[15]++; if (data & 256) pin_counts[16]++; if (data & 512) pin_counts[17]++; if (data & 1024) pin_counts[18]++; if (data & 2048) pin_counts[19]++; if (data & 4096) pin_counts[20]++; if (data & 8192) pin_counts[21]++; if (data & 16384) pin_counts[22]++; if (data & 32768) pin_counts[23]++; // control lines on port D data = GPIOD->IDR; if (data & ZX_RESET_Pin) pin_counts[24]++; if (data & ZX_MEMREQ_Pin) pin_counts[25]++; if (data & ZX_IOREQ_Pin) pin_counts[26]++; if (data & ZX_RD_Pin) pin_counts[27]++; if (data & ZX_WR_Pin) pin_counts[28]++; // control lines on port A data = GPIOA->IDR; if (data & ZX_ROMCS_Pin) pin_counts[29]++; if (data & ZX_WAIT_Pin) pin_counts[30]++; if (++count == 1000000) { // blink LED HAL_GPIO_TogglePin(LED1_GPIO_Port, LED1_Pin); // dump pin counts USB_printf("************* systick=%ld\r\n", HAL_GetTick()); report_pin("D0", pin_counts[0], count); report_pin("D1", pin_counts[1], count); report_pin("D2", pin_counts[2], count); report_pin("D3", pin_counts[3], count); report_pin("D4", pin_counts[4], count); report_pin("D5", pin_counts[5], count); report_pin("D6", pin_counts[6], count); report_pin("D7", pin_counts[7], count); report_pin("A0", pin_counts[8], count); report_pin("A1", pin_counts[9], count); report_pin("A2", pin_counts[10], count); report_pin("A3", pin_counts[11], count); report_pin("A4", pin_counts[12], count); report_pin("A5", pin_counts[13], count); report_pin("A6", pin_counts[14], count); report_pin("A7", pin_counts[15], count); report_pin("A8", pin_counts[16], count); report_pin("A9", pin_counts[17], count); report_pin("A10", pin_counts[18], count); report_pin("A11", pin_counts[19], count); report_pin("A12", pin_counts[20], count); report_pin("A13", pin_counts[21], count); report_pin("A14", pin_counts[22], count); report_pin("A15", pin_counts[23], count); report_pin("RESET", pin_counts[24], count); report_pin("MEMREQ", pin_counts[25], count); report_pin("IOREQ", pin_counts[26], count); report_pin("RD", pin_counts[27], count); report_pin("WR", pin_counts[28], count); report_pin("ROMCS", pin_counts[29], count); report_pin("WAIT", pin_counts[30], count); USB_printf("************* sampling...\r\n"); count = 0; // zero pin counters for (int i = 0; i < 32; i++) { pin_counts[i] = 0; } } } }
static void main_init(void){ GPIO_InitTypeDef ledGPIOInit; int i; SystemInit(); HAL_Init(); /* Configure the system clock to 168 MHz */ //SystemClock_Config(); std_init(); __GPIOD_CLK_ENABLE(); __GPIOA_CLK_ENABLE(); ledGPIOInit.Pin = GPIO_PIN_12 | GPIO_PIN_13 | GPIO_PIN_14 | GPIO_PIN_15; ledGPIOInit.Mode = GPIO_MODE_OUTPUT_PP; ledGPIOInit.Pull = GPIO_NOPULL; ledGPIOInit.Speed = GPIO_SPEED_FREQ_MEDIUM; HAL_GPIO_Init(GPIOD,&ledGPIOInit); ledGPIOInit.Pin = GPIO_PIN_0; ledGPIOInit.Mode = GPIO_MODE_INPUT; ledGPIOInit.Pull = GPIO_PULLDOWN; ledGPIOInit.Speed = GPIO_SPEED_FREQ_MEDIUM; HAL_GPIO_Init(GPIOA,&ledGPIOInit); HAL_Delay(10); pwm_init(); for( i = 0; i < 4; i++){ power[i] = 0; } HAL_Delay(20); for( i = 0; i < 4; i++){ power[i] = 1000; } HAL_Delay(20); for( i = 0; i < 4; i++){ power[i] = 0; } if(initMPU()){ puts("Failed MPU"); } Get_Gyro_Offset_Start(); HAL_Delay(1000); if(Get_Gyro_Offset_Stopp()<900){ puts("Failed Gyrooffset"); Error_Handler(); } delayTime = HAL_GetTick(); pidDataX = &pidDataXObj; pidDataY = &pidDataYObj; pid_init(pidDataX,1,0,0,0.003f,9000,900); pid_init(pidDataY,1,0,0,0.003f,9000,900); init2Kalman(&kalman2X,90); init2Kalman(&kalman2Y,90); puts("Init + Selfcheck okay!"); }
int main(void) { // TODO disable JTAG /* STM32F4xx HAL library initialization: - Configure the Flash prefetch, instruction and Data caches - Configure the Systick to generate an interrupt each 1 msec - Set NVIC Group Priority to 4 - Global MSP (MCU Support Package) initialization */ HAL_Init(); // set the system clock to be HSE SystemClock_Config(); // enable GPIO clocks __GPIOA_CLK_ENABLE(); __GPIOB_CLK_ENABLE(); __GPIOC_CLK_ENABLE(); __GPIOD_CLK_ENABLE(); // enable the CCM RAM __CCMDATARAMEN_CLK_ENABLE(); #if 0 #if defined(NETDUINO_PLUS_2) { GPIO_InitTypeDef GPIO_InitStructure; GPIO_InitStructure.GPIO_Speed = GPIO_Speed_25MHz; GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT; GPIO_InitStructure.GPIO_OType = GPIO_OType_PP; GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL; #if MICROPY_HW_HAS_SDCARD // Turn on the power enable for the sdcard (PB1) GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; GPIO_Init(GPIOB, &GPIO_InitStructure); GPIO_WriteBit(GPIOB, GPIO_Pin_1, Bit_SET); #endif // Turn on the power for the 5V on the expansion header (PB2) GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; GPIO_Init(GPIOB, &GPIO_InitStructure); GPIO_WriteBit(GPIOB, GPIO_Pin_2, Bit_SET); } #endif #endif // basic sub-system init pendsv_init(); timer_tim3_init(); led_init(); switch_init0(); int first_soft_reset = true; soft_reset: // check if user switch held to select the reset mode led_state(1, 0); led_state(2, 1); led_state(3, 0); led_state(4, 0); uint reset_mode = 1; #if MICROPY_HW_HAS_SWITCH if (switch_get()) { for (uint i = 0; i < 3000; i++) { if (!switch_get()) { break; } HAL_Delay(20); if (i % 30 == 29) { if (++reset_mode > 3) { reset_mode = 1; } led_state(2, reset_mode & 1); led_state(3, reset_mode & 2); led_state(4, reset_mode & 4); } } // flash the selected reset mode for (uint i = 0; i < 6; i++) { led_state(2, 0); led_state(3, 0); led_state(4, 0); HAL_Delay(50); led_state(2, reset_mode & 1); led_state(3, reset_mode & 2); led_state(4, reset_mode & 4); HAL_Delay(50); } HAL_Delay(400); } #endif #if MICROPY_HW_ENABLE_RTC if (first_soft_reset) { rtc_init(); } #endif // more sub-system init #if MICROPY_HW_HAS_SDCARD if (first_soft_reset) { sdcard_init(); } #endif if (first_soft_reset) { storage_init(); } // GC init gc_init(&_heap_start, &_heap_end); // Change #if 0 to #if 1 if you want REPL on USART_6 (or another usart) // as well as on USB VCP #if 0 pyb_usart_global_debug = pyb_Usart(MP_OBJ_NEW_SMALL_INT(PYB_USART_YA), MP_OBJ_NEW_SMALL_INT(115200)); #else pyb_usart_global_debug = NULL; #endif // Micro Python init qstr_init(); mp_init(); mp_obj_list_init(mp_sys_path, 0); mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_0_colon__slash_)); mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR_0_colon__slash_lib)); mp_obj_list_init(mp_sys_argv, 0); readline_init(); exti_init(); #if MICROPY_HW_HAS_SWITCH // must come after exti_init switch_init(); #endif #if MICROPY_HW_HAS_LCD // LCD init (just creates class, init hardware by calling LCD()) lcd_init(); #endif pin_map_init(); // local filesystem init { // try to mount the flash FRESULT res = f_mount(&fatfs0, "0:", 1); if (reset_mode == 3 || res == FR_NO_FILESYSTEM) { // no filesystem, or asked to reset it, so create a fresh one // LED on to indicate creation of LFS led_state(PYB_LED_R2, 1); uint32_t start_tick = HAL_GetTick(); res = f_mkfs("0:", 0, 0); if (res == FR_OK) { // success creating fresh LFS } else { __fatal_error("could not create LFS"); } // create empty main.py FIL fp; f_open(&fp, "0:/main.py", FA_WRITE | FA_CREATE_ALWAYS); UINT n; f_write(&fp, fresh_main_py, sizeof(fresh_main_py) - 1 /* don't count null terminator */, &n); // TODO check we could write n bytes f_close(&fp); // create .inf driver file f_open(&fp, "0:/pybcdc.inf", FA_WRITE | FA_CREATE_ALWAYS); f_write(&fp, fresh_pybcdc_inf, sizeof(fresh_pybcdc_inf) - 1 /* don't count null terminator */, &n); f_close(&fp); // keep LED on for at least 200ms sys_tick_wait_at_least(start_tick, 200); led_state(PYB_LED_R2, 0); } else if (res == FR_OK) { // mount sucessful } else { __fatal_error("could not access LFS"); } } // make sure we have a 0:/boot.py { FILINFO fno; #if _USE_LFN fno.lfname = NULL; fno.lfsize = 0; #endif FRESULT res = f_stat("0:/boot.py", &fno); if (res == FR_OK) { if (fno.fattrib & AM_DIR) { // exists as a directory // TODO handle this case // see http://elm-chan.org/fsw/ff/img/app2.c for a "rm -rf" implementation } else { // exists as a file, good! } } else { // doesn't exist, create fresh file // LED on to indicate creation of boot.py led_state(PYB_LED_R2, 1); uint32_t start_tick = HAL_GetTick(); FIL fp; f_open(&fp, "0:/boot.py", FA_WRITE | FA_CREATE_ALWAYS); UINT n; f_write(&fp, fresh_boot_py, sizeof(fresh_boot_py) - 1 /* don't count null terminator */, &n); // TODO check we could write n bytes f_close(&fp); // keep LED on for at least 200ms sys_tick_wait_at_least(start_tick, 200); led_state(PYB_LED_R2, 0); } } // root device defaults to internal flash filesystem uint root_device = 0; #if defined(USE_DEVICE_MODE) usb_storage_medium_t usb_medium = USB_STORAGE_MEDIUM_FLASH; #endif #if MICROPY_HW_HAS_SDCARD // if an SD card is present then mount it on 1:/ if (reset_mode == 1 && sdcard_is_present()) { FRESULT res = f_mount(&fatfs1, "1:", 1); if (res != FR_OK) { printf("[SD] could not mount SD card\n"); } else { // use SD card as root device root_device = 1; if (first_soft_reset) { // use SD card as medium for the USB MSD #if defined(USE_DEVICE_MODE) usb_medium = USB_STORAGE_MEDIUM_SDCARD; #endif } } } #else // Get rid of compiler warning if no SDCARD is configured. (void)first_soft_reset; #endif // run <root>:/boot.py, if it exists if (reset_mode == 1) { const char *boot_file; if (root_device == 0) { boot_file = "0:/boot.py"; } else { boot_file = "1:/boot.py"; } FRESULT res = f_stat(boot_file, NULL); if (res == FR_OK) { if (!pyexec_file(boot_file)) { flash_error(4); } } } // turn boot-up LEDs off led_state(2, 0); led_state(3, 0); led_state(4, 0); #if defined(USE_HOST_MODE) // USB host pyb_usb_host_init(); #elif defined(USE_DEVICE_MODE) // USB device if (reset_mode == 1) { usb_device_mode_t usb_mode = USB_DEVICE_MODE_CDC_MSC; if (pyb_config_usb_mode != MP_OBJ_NULL) { if (strcmp(mp_obj_str_get_str(pyb_config_usb_mode), "CDC+HID") == 0) { usb_mode = USB_DEVICE_MODE_CDC_HID; } } pyb_usb_dev_init(usb_mode, usb_medium); } else { pyb_usb_dev_init(USB_DEVICE_MODE_CDC_MSC, usb_medium); } #endif #if MICROPY_HW_ENABLE_RNG // RNG rng_init(); #endif #if MICROPY_HW_ENABLE_TIMER // timer //timer_init(); #endif // I2C i2c_init(); #if MICROPY_HW_HAS_MMA7660 // MMA accel: init and reset accel_init(); #endif #if MICROPY_HW_ENABLE_SERVO // servo servo_init(); #endif #if MICROPY_HW_ENABLE_DAC // DAC dac_init(); #endif // now that everything is initialised, run main script if (reset_mode == 1 && pyexec_mode_kind == PYEXEC_MODE_FRIENDLY_REPL) { vstr_t *vstr = vstr_new(); vstr_printf(vstr, "%d:/", root_device); if (pyb_config_main == MP_OBJ_NULL) { vstr_add_str(vstr, "main.py"); } else { vstr_add_str(vstr, mp_obj_str_get_str(pyb_config_main)); } FRESULT res = f_stat(vstr_str(vstr), NULL); if (res == FR_OK) { if (!pyexec_file(vstr_str(vstr))) { flash_error(3); } } vstr_free(vstr); } #if 0 #if MICROPY_HW_HAS_WLAN // wifi pyb_wlan_init(); pyb_wlan_start(); #endif #endif // enter REPL // REPL mode can change, or it can request a soft reset for (;;) { if (pyexec_mode_kind == PYEXEC_MODE_RAW_REPL) { if (pyexec_raw_repl() != 0) { break; } } else { if (pyexec_friendly_repl() != 0) { break; } } } printf("PYB: sync filesystems\n"); storage_flush(); printf("PYB: soft reboot\n"); first_soft_reset = false; goto soft_reset; }
/** * @brief Initialize the DMA according to the specified * parameters in the DMA_InitTypeDef and create the associated handle. * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { uint32_t tmp = 0U; uint32_t tickstart = HAL_GetTick(); DMA_Base_Registers *regs; /* Check the DMA peripheral state */ if(hdma == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); /* Check the memory burst, peripheral burst and FIFO threshold parameters only when FIFO mode is enabled */ if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) { assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); } /* Allocate lock resource */ __HAL_UNLOCK(hdma); /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); /* Check if the DMA Stream is effectively disabled */ while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) { /* Check for the Timeout */ if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_TIMEOUT; return HAL_TIMEOUT; } } /* Get the CR register value */ tmp = hdma->Instance->CR; /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR, CT and DBM bits */ tmp &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \ DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \ DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \ DMA_SxCR_DIR | DMA_SxCR_CT | DMA_SxCR_DBM)); /* Prepare the DMA Stream configuration */ tmp |= hdma->Init.Channel | hdma->Init.Direction | hdma->Init.PeriphInc | hdma->Init.MemInc | hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | hdma->Init.Mode | hdma->Init.Priority; /* the Memory burst and peripheral burst are not used when the FIFO is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) { /* Get memory burst and peripheral burst */ tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; } /* Write to DMA Stream CR register */ hdma->Instance->CR = tmp; /* Get the FCR register value */ tmp = hdma->Instance->FCR; /* Clear Direct mode and FIFO threshold bits */ tmp &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH); /* Prepare the DMA Stream FIFO configuration */ tmp |= hdma->Init.FIFOMode; /* the FIFO threshold is not used when the FIFO mode is disabled */ if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) { /* Get the FIFO threshold */ tmp |= hdma->Init.FIFOThreshold; if (DMA_CheckFifoParam(hdma) != HAL_OK) { /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_PARAM; /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; return HAL_ERROR; } } /* Write to DMA Stream FCR */ hdma->Instance->FCR = tmp; /* Initialize StreamBaseAddress and StreamIndex parameters to be used to calculate DMA steam Base Address needed by HAL_DMA_IRQHandler() and HAL_DMA_PollForTransfer() */ regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); /* Clear all interrupt flags */ regs->IFCR = 0x3FU << hdma->StreamIndex; /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; /* Initialize the DMA state */ hdma->State = HAL_DMA_STATE_READY; return HAL_OK; }
// parses, compiles and executes the code in the lexer // frees the lexer before returning bool parse_compile_execute(mp_lexer_t *lex, mp_parse_input_kind_t input_kind, bool is_repl) { mp_parse_error_kind_t parse_error_kind; mp_parse_node_t pn = mp_parse(lex, input_kind, &parse_error_kind); qstr source_name = mp_lexer_source_name(lex); if (pn == MP_PARSE_NODE_NULL) { // parse error mp_parse_show_exception(lex, parse_error_kind); mp_lexer_free(lex); return false; } mp_lexer_free(lex); mp_obj_t module_fun = mp_compile(pn, source_name, MP_EMIT_OPT_NONE, is_repl); if (mp_obj_is_exception_instance(module_fun)) { mp_obj_print_exception(module_fun); return false; } nlr_buf_t nlr; bool ret; uint32_t start = HAL_GetTick(); if (nlr_push(&nlr) == 0) { usb_vcp_set_interrupt_char(VCP_CHAR_CTRL_C); // allow ctrl-C to interrupt us mp_call_function_0(module_fun); usb_vcp_set_interrupt_char(VCP_CHAR_NONE); // disable interrupt nlr_pop(); ret = true; } else { // uncaught exception // FIXME it could be that an interrupt happens just before we disable it here usb_vcp_set_interrupt_char(VCP_CHAR_NONE); // disable interrupt mp_obj_print_exception((mp_obj_t)nlr.ret_val); ret = false; } // display debugging info if wanted if (is_repl && repl_display_debugging_info) { uint32_t ticks = HAL_GetTick() - start; // TODO implement a function that does this properly printf("took %lu ms\n", ticks); gc_collect(); // qstr info { mp_uint_t n_pool, n_qstr, n_str_data_bytes, n_total_bytes; qstr_pool_info(&n_pool, &n_qstr, &n_str_data_bytes, &n_total_bytes); printf("qstr:\n n_pool=" UINT_FMT "\n n_qstr=" UINT_FMT "\n n_str_data_bytes=" UINT_FMT "\n n_total_bytes=" UINT_FMT "\n", n_pool, n_qstr, n_str_data_bytes, n_total_bytes); } // GC info { gc_info_t info; gc_info(&info); printf("GC:\n"); printf(" " UINT_FMT " total\n", info.total); printf(" " UINT_FMT " : " UINT_FMT "\n", info.used, info.free); printf(" 1=" UINT_FMT " 2=" UINT_FMT " m=" UINT_FMT "\n", info.num_1block, info.num_2block, info.max_block); } } return ret; }
/** * @brief Initializes the LCD peripheral according to the specified parameters * in the LCD_InitStruct. * @note This function can be used only when the LCD is disabled. * The LCD HighDrive can be enabled/disabled using related macros up to user. * @param hlcd: LCD handle * @retval None */ HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd) { uint32_t tickstart = 0x00; uint8_t counter = 0; /* Check the LCD handle allocation */ if(hlcd == NULL) { return HAL_ERROR; } /* Check function parameters */ assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance)); assert_param(IS_LCD_PRESCALER(hlcd->Init.Prescaler)); assert_param(IS_LCD_DIVIDER(hlcd->Init.Divider)); assert_param(IS_LCD_DUTY(hlcd->Init.Duty)); assert_param(IS_LCD_BIAS(hlcd->Init.Bias)); assert_param(IS_LCD_VOLTAGE_SOURCE(hlcd->Init.VoltageSource)); assert_param(IS_LCD_PULSE_ON_DURATION(hlcd->Init.PulseOnDuration)); assert_param(IS_LCD_HIGHDRIVE(hlcd->Init.HighDrive)); assert_param(IS_LCD_DEAD_TIME(hlcd->Init.DeadTime)); assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast)); assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency)); assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode)); assert_param(IS_LCD_MUXSEGMENT(hlcd->Init.MuxSegment)); if(hlcd->State == HAL_LCD_STATE_RESET) { /* Allocate lock resource and initialize it */ hlcd->Lock = HAL_UNLOCKED; /* Initialize the low level hardware (MSP) */ HAL_LCD_MspInit(hlcd); } hlcd->State = HAL_LCD_STATE_BUSY; /* Disable the peripheral */ __HAL_LCD_DISABLE(hlcd); /* Clear the LCD_RAM registers and enable the display request by setting the UDR bit in the LCD_SR register */ for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++) { hlcd->Instance->RAM[counter] = 0; } /* Enable the display request */ SET_BIT(hlcd->Instance->SR, LCD_SR_UDR); /* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency: Set PS[3:0] bits according to hlcd->Init.Prescaler value Set DIV[3:0] bits according to hlcd->Init.Divider value Set BLINK[1:0] bits according to hlcd->Init.BlinkMode value Set BLINKF[2:0] bits according to hlcd->Init.BlinkFrequency value Set DEAD[2:0] bits according to hlcd->Init.DeadTime value Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value Set CC[2:0] bits according to hlcd->Init.Contrast value Set HD[0] bit according to hlcd->Init.HighDrive value */ MODIFY_REG(hlcd->Instance->FCR, \ (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK| LCD_FCR_BLINKF | \ LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC), \ (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \ hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast | hlcd->Init.HighDrive)); /* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK domain. It is cleared by hardware when writing to the LCD_FCR register.*/ LCD_WaitForSynchro(hlcd); /* Configure the LCD Duty, Bias, Voltage Source, Dead Time: Set DUTY[2:0] bits according to hlcd->Init.Duty value Set BIAS[1:0] bits according to hlcd->Init.Bias value Set VSEL bit according to hlcd->Init.VoltageSource value Set MUX_SEG bit according to hlcd->Init.MuxSegment value */ MODIFY_REG(hlcd->Instance->CR, \ (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \ (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment)); /* Enable the peripheral */ __HAL_LCD_ENABLE(hlcd); /* Get timeout */ tickstart = HAL_GetTick(); /* Wait Until the LCD is enabled */ while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET) { if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) { hlcd->ErrorCode = HAL_LCD_ERROR_ENS; return HAL_TIMEOUT; } } /* Get timeout */ tickstart = HAL_GetTick(); /*!< Wait Until the LCD Booster is ready */ while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET) { if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE) { hlcd->ErrorCode = HAL_LCD_ERROR_RDY; return HAL_TIMEOUT; } } /* Initialize the LCD state */ hlcd->ErrorCode = HAL_LCD_ERROR_NONE; hlcd->State= HAL_LCD_STATE_READY; return HAL_OK; }
bool sys_tick_has_passed(uint32_t start_tick, uint32_t delay_ms) { return HAL_GetTick() - start_tick >= delay_ms; }
/** * @brief This function handles SPDIFRX Communication Timeout. * @param hspdif: SPDIFRX handle * @param Flag: Flag checked * @param Status: Value of the flag expected * @param Timeout: Duration of the timeout * @param tickstart: Tick start value * @retval HAL status */ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart) { /* Wait until flag is set */ if(Status == RESET) { while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) == RESET) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); hspdif->State= HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); return HAL_TIMEOUT; } } } } else { while(__HAL_SPDIFRX_GET_FLAG(hspdif, Flag) != RESET) { /* Check for the Timeout */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) { /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_RXNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_CSRNE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_PERRIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_OVRIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SBLKIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_SYNCDIE); __HAL_SPDIFRX_DISABLE_IT(hspdif, SPDIFRX_IT_IFEIE); hspdif->State= HAL_SPDIFRX_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hspdif); return HAL_TIMEOUT; } } } } return HAL_OK; }
void Command_Task() { // //if (Get_Accelero_State()) { const char *gps_gga = (char *)Get_GPS_Message(GGA); const char *gps_rmc = (char *)Get_GPS_Message(RMC); uint8_t free_fall_state = Get_Free_Fall_State(); if (alarm) { if ((HAL_GetTick() - alarm_start_time) > GetParamValue(ALARM_TIME)*1000) { alarm = 0; HAL_GPIO_WritePin(GPIOC, GPIO_PIN_15, GPIO_PIN_SET); } } if (((HAL_GetTick() - last_tick) > ServerCommands[1]) || free_fall_state ) { last_tick = HAL_GetTick(); if ((gps_gga != nullptr) && (gps_rmc != nullptr)) { Reset_Message_Status(GGA); Reset_Message_Status(RMC); int size = 0; SensorAxesRaw_t * acc_data = Get_ACC_Data(); SensorAxesRaw_t * gyro_data = Get_GYRO_Data(); int32_t * adc_data = Get_ADC_Data(); // set uin--------------------------------------------------------------- //PushToBuffer(CLEAR, "%s,%d,%d,%d\r\n", uin, system_info.tracker_id, system_info.sw_version, system_info.hw_version); // set tmark------------------------------------------------------------- // get time // copy seconds // copy packet naumber // copy packet naumber uint32_t time = calendar_coder(); uint16_t sub_sec = 0; packet_number++; PushToBuffer(CLEAR, "%s,%d,%d,%d\r\n", tmark, time, sub_sec, packet_number ); // set gga--------------------------------------------------------------- PushToBuffer(NO_ACTION, "%s\r\n", gps_gga); // set rmc--------------------------------------------------------------- PushToBuffer(NO_ACTION, "%s\r\n", gps_rmc); // set motion state------------------------------------------------------ PushToBuffer(NO_ACTION, "%s,%d,%d,%d,%d,%d,%d\r\n", ag, acc_data->AXIS_X, acc_data->AXIS_Y, acc_data->AXIS_Z, gyro_data->AXIS_X, gyro_data->AXIS_Y, gyro_data->AXIS_Z); // set adc result-------------------------------------------------------- PushToBuffer(NO_ACTION, "%s,%d,%d\r\n", volt, abs(adc_data[0]), abs(adc_data[1])); // push event to output data in gsm routing // set event state------------------------------------------------------- /* for (int i = EVENT_FREE_FALL; i < MAX_EVENTS; i++) { if (GetEventState(i) == EVENT_ACTIVE) { PushToBuffer(NO_ACTION, "%s,%d,0\r\n", event, i); // we must make sure that the event is delivered // flags will be resets, when data will be delivered SetBufferFlags(i); } } */ // push end of file cmd ------------------------------------------------- //PushToBuffer(NO_ACTION, "%s\r\n", eof); EndBufferWrite(); } } } // else // { // } }
/** * @brief Receive an amount of data (Control Flow) with DMA * @param hspdif: SPDIFRX handle * @param pData: a 32-bit pointer to the Receive data buffer. * @param Size: number of data (Control Flow) sample to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) { uint32_t tickstart = 0U; if((pData == NULL) || (Size == 0U)) { return HAL_ERROR; } if((hspdif->State == HAL_SPDIFRX_STATE_READY) || (hspdif->State == HAL_SPDIFRX_STATE_BUSY_RX)) { hspdif->pCsBuffPtr = pData; hspdif->CsXferSize = Size; hspdif->CsXferCount = Size; /* Process Locked */ __HAL_LOCK(hspdif); hspdif->ErrorCode = HAL_SPDIFRX_ERROR_NONE; hspdif->State = HAL_SPDIFRX_STATE_BUSY_CX; /* Set the SPDIFRX Rx DMA Half transfer complete callback */ hspdif->hdmaCsRx->XferHalfCpltCallback = SPDIFRX_DMACxHalfCplt; /* Set the SPDIFRX Rx DMA transfer complete callback */ hspdif->hdmaCsRx->XferCpltCallback = SPDIFRX_DMACxCplt; /* Set the DMA error callback */ hspdif->hdmaCsRx->XferErrorCallback = SPDIFRX_DMAError; /* Enable the DMA request */ HAL_DMA_Start_IT(hspdif->hdmaCsRx, (uint32_t)&hspdif->Instance->CSR, (uint32_t)hspdif->pCsBuffPtr, Size); /* Enable CBDMAEN bit in SPDIFRX CR register for control flow reception*/ hspdif->Instance->CR |= SPDIFRX_CR_CBDMAEN; if (((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != SPDIFRX_STATE_SYNC) || ((SPDIFRX->CR & SPDIFRX_CR_SPDIFEN) != 0x00U)) { /* Start synchronization */ __HAL_SPDIFRX_SYNC(hspdif); /* Get tick */ tickstart = HAL_GetTick(); /* Wait until SYNCD flag is set */ if(SPDIFRX_WaitOnFlagUntilTimeout(hspdif, SPDIFRX_FLAG_SYNCD, RESET, SPDIFRX_TIMEOUT_VALUE, tickstart) != HAL_OK) { return HAL_TIMEOUT; } /* Start reception */ __HAL_SPDIFRX_RCV(hspdif); } /* Process Unlocked */ __HAL_UNLOCK(hspdif); return HAL_OK; } else { return HAL_BUSY; } }
int Parse_Command(char * data, int size) { /* $CMD,N,1,0\r\n*/ char * ptr = nullptr; int16_t reg = -1; int16_t value = -1; uint8_t error_code = 0; ptr = (char*)strstr(data, cmd); if (ptr != nullptr) { ptr += strlen(cmd) + 1; char command = *ptr; ptr += 2; // get register address char * end_str = (char *)strchr(ptr, ','); if (end_str != nullptr) { char number[8] = {0}; int size = (uint32_t)end_str - (uint32_t)(ptr); size = size < 8 ? size : 8; strncpy ( number, ptr, size ); reg = atoi(number); // get command value ptr = end_str + 1; end_str = (char *)strchr(ptr, '\r'); if (end_str != nullptr) { memset(number, 0, 8); size = (uint32_t)end_str - (uint32_t)(ptr); size = size < 8 ? size : 8; strncpy ( number, ptr, size ); value = atoi(number); } else { error_code = 2; } if ((reg >= 0) && (reg <= 7) && (value >= 0) && (value <= 7)) { switch (command) { case 'W': if (reg == 0) { switch (value) { case CMD_REBOOT: DEBUG_PRINTF("REBOOT\r\n"); break; case CMD_SLEEP: DEBUG_PRINTF("SLEEP\r\n"); force_sleep = 1; DisableWakeupDetection(); break; case CMD_ACTIVE: DEBUG_PRINTF("ACTIVE\r\n"); EnableWakeupDetection(); force_sleep = 0; break; case CMD_ALARM: DEBUG_PRINTF("ALARM\r\n"); alarm = 1; alarm_start_time = HAL_GetTick(); HAL_GPIO_WritePin(GPIOC, GPIO_PIN_15, GPIO_PIN_RESET); break; default: value = 0; error_code = 3; DEBUG_PRINTF("Unknown Command\r\n"); break; } } else { ServerCommands[reg] = value; } break; case 'R': if (reg == 0) { value = 0; } else { value = ServerCommands[reg]; } break; case 'N': break; } } } else { error_code = 1; } PushToAnswers((void *)ack, sizeof(ack)-1, CLEAR); EndBufferWriteAnsw(); } return -1; }
/** * @brief Initializes the CAN peripheral according to the specified * parameters in the CAN_InitStruct. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) { uint32_t InitStatus = 3U; uint32_t tickstart = 0U; /* Check CAN handle */ if(hcan == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); assert_param(IS_CAN_MODE(hcan->Init.Mode)); assert_param(IS_CAN_SJW(hcan->Init.SJW)); assert_param(IS_CAN_BS1(hcan->Init.BS1)); assert_param(IS_CAN_BS2(hcan->Init.BS2)); assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); if(hcan->State == HAL_CAN_STATE_RESET) { /* Allocate lock resource and initialize it */ hcan->Lock = HAL_UNLOCKED; /* Init the low level hardware */ HAL_CAN_MspInit(hcan); } /* Initialize the CAN state*/ hcan->State = HAL_CAN_STATE_BUSY; /* Exit from sleep mode */ hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); /* Request initialisation */ hcan->Instance->MCR |= CAN_MCR_INRQ ; /* Get tick */ tickstart = HAL_GetTick(); /* Wait the acknowledge */ while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) { if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) { hcan->State= HAL_CAN_STATE_TIMEOUT; /* Process unlocked */ __HAL_UNLOCK(hcan); return HAL_TIMEOUT; } } /* Check acknowledge */ if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) { InitStatus = CAN_INITSTATUS_FAILED; } else { /* Set the time triggered communication mode */ if (hcan->Init.TTCM == ENABLE) { hcan->Instance->MCR |= CAN_MCR_TTCM; } else { hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; } /* Set the automatic bus-off management */ if (hcan->Init.ABOM == ENABLE) { hcan->Instance->MCR |= CAN_MCR_ABOM; } else { hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; } /* Set the automatic wake-up mode */ if (hcan->Init.AWUM == ENABLE) { hcan->Instance->MCR |= CAN_MCR_AWUM; } else { hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; } /* Set the no automatic retransmission */ if (hcan->Init.NART == ENABLE) { hcan->Instance->MCR |= CAN_MCR_NART; } else { hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; } /* Set the receive FIFO locked mode */ if (hcan->Init.RFLM == ENABLE) { hcan->Instance->MCR |= CAN_MCR_RFLM; } else { hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; } /* Set the transmit FIFO priority */ if (hcan->Init.TXFP == ENABLE) { hcan->Instance->MCR |= CAN_MCR_TXFP; } else { hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; } /* Set the bit timing register */ hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ ((uint32_t)hcan->Init.SJW) | \ ((uint32_t)hcan->Init.BS1) | \ ((uint32_t)hcan->Init.BS2) | \ ((uint32_t)hcan->Init.Prescaler - 1U); /* Request leave initialisation */ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; /* Get tick */ tickstart = HAL_GetTick(); /* Wait the acknowledge */ while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE) { hcan->State= HAL_CAN_STATE_TIMEOUT; /* Process unlocked */ __HAL_UNLOCK(hcan); return HAL_TIMEOUT; } } /* Check acknowledged */ if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { InitStatus = CAN_INITSTATUS_FAILED; } else { InitStatus = CAN_INITSTATUS_SUCCESS; } } if(InitStatus == CAN_INITSTATUS_SUCCESS) { /* Set CAN error code to none */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; /* Return function status */ return HAL_OK; } else { /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_ERROR; /* Return function status */ return HAL_ERROR; } }
/** * @brief Send data in blocking mode * @param hcec: CEC handle * @param DestinationAddress: destination logical address * @param pData: pointer to input byte data buffer * @param Size: amount of data to be sent in bytes (without counting the header). * 0 means only the header is sent (ping operation). * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). * @param Timeout: Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout) { uint8_t temp = 0; uint32_t tickstart = 0; /* If the IP is ready */ if((hcec->State == HAL_CEC_STATE_READY) && (__HAL_CEC_GET_TRANSMISSION_START_FLAG(hcec) == RESET)) { /* Basic check on pData pointer */ if(((pData == NULL) && (Size > 0)) || (! IS_CEC_MSGSIZE(Size))) { return HAL_ERROR; } assert_param(IS_CEC_ADDRESS(DestinationAddress)); /* Process Locked */ __HAL_LOCK(hcec); /* Enter the transmit mode */ hcec->State = HAL_CEC_STATE_BUSY_TX; hcec->ErrorCode = HAL_CEC_ERROR_NONE; /* Initialize the number of bytes to send, * 0 means only one header is sent (ping operation) */ hcec->TxXferCount = Size; /* Send header block */ temp = (uint8_t)((uint32_t)(hcec->Init.InitiatorAddress) << CEC_INITIATOR_LSB_POS) | DestinationAddress; hcec->Instance->TXD = temp; /* In case no data to be sent, sender is only pinging the system */ if (Size != 0) { /* Set TX Start of Message (TXSOM) bit */ hcec->Instance->CSR = CEC_FLAG_TSOM; } else { /* Send a ping command */ hcec->Instance->CSR = CEC_FLAG_TEOM|CEC_FLAG_TSOM; } /* Polling TBTRF bit with timeout handling*/ while (hcec->TxXferCount > 0) { /* Decreasing of the number of remaining data to receive */ hcec->TxXferCount--; /* Timeout handling */ tickstart = HAL_GetTick(); /* Waiting for the next data transmission */ while(HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_TBTRF)) { /* Timeout handling */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { hcec->State = HAL_CEC_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hcec); return HAL_TIMEOUT; } } /* Check if an error occured */ if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR)) { /* Copy ESR for error handling purposes */ hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR); /* Acknowledgement of the error */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR); __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR); hcec->State = HAL_CEC_STATE_READY; __HAL_UNLOCK(hcec); return HAL_ERROR; } } /* Write the next data to TX buffer */ hcec->Instance->TXD = *pData++; /* If this is the last byte of the ongoing transmission */ if (hcec->TxXferCount == 0) { /* Acknowledge byte request and signal end of message */ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, CEC_FLAG_TEOM); } else { /* Acknowledge byte request by writing 0x00 */ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00); } } /* Timeout handling */ tickstart = HAL_GetTick(); /* Wait for message transmission completion (TBTRF is set) */ while (HAL_IS_BIT_CLR(hcec->Instance->CSR, CEC_FLAG_TBTRF)) { /* Timeout handling */ if(Timeout != HAL_MAX_DELAY) { if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) { hcec->State = HAL_CEC_STATE_READY; __HAL_UNLOCK(hcec); return HAL_TIMEOUT; } } /* Check of error during transmission of the last byte */ if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR)) { /* Copy ESR for error handling purposes */ hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR); /* Acknowledgement of the error */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR); __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR); hcec->State = HAL_CEC_STATE_READY; __HAL_UNLOCK(hcec); return HAL_ERROR; } } /* Check of error after the last byte transmission */ if(HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_TERR) || HAL_IS_BIT_SET(hcec->Instance->CSR, CEC_FLAG_RERR)) { /* Copy ESR for error handling purposes */ hcec->ErrorCode = READ_BIT(hcec->Instance->ESR, CEC_ESR_ALL_ERROR); /* Acknowledgement of the error */ __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_TERR); __HAL_CEC_CLEAR_FLAG(hcec, CEC_FLAG_RERR); hcec->State = HAL_CEC_STATE_READY; __HAL_UNLOCK(hcec); return HAL_ERROR; } /* Acknowledge successful completion by writing 0x00 */ MODIFY_REG(hcec->Instance->CSR, CEC_FLAG_TRANSMIT_MASK, 0x00); hcec->State = HAL_CEC_STATE_READY; __HAL_UNLOCK(hcec); return HAL_OK; } else { return HAL_BUSY; } }
/** * @brief Sets wake up timer with interrupt * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains * the configuration information for RTC. * @param WakeUpCounter: Wake up counter * @param WakeUpClock: Wake up clock * @retval HAL status */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock) { uint32_t tickstart = 0; /* Check the parameters */ assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock)); assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); /* Process Locked */ __HAL_LOCK(hrtc); hrtc->State = HAL_RTC_STATE_BUSY; /* Disable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); /*Check RTC WUTWF flag is reset only when wake up timer enabled*/ if((hrtc->Instance->CR & RTC_CR_WUTE) != RESET) { tickstart = HAL_GetTick(); /* Wait till RTC WUTWF flag is reset and if Time out is reached exit */ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == SET) { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); hrtc->State = HAL_RTC_STATE_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_TIMEOUT; } } } __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc); /* Get tick */ tickstart = HAL_GetTick(); /* Wait till RTC WUTWF flag is set and if Time out is reached exit */ while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET) { if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE) { /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); hrtc->State = HAL_RTC_STATE_TIMEOUT; /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_TIMEOUT; } } /* Configure the Wake-up Timer counter */ hrtc->Instance->WUTR = (uint32_t)WakeUpCounter; /* Clear the Wake-up Timer clock source bits in CR register */ hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL; /* Configure the clock source */ hrtc->Instance->CR |= (uint32_t)WakeUpClock; /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */ __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT; /* Configure the Interrupt in the RTC_CR register */ __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT); /* Enable the Wake-up Timer */ __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc); /* Enable the write protection for RTC registers */ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); hrtc->State = HAL_RTC_STATE_READY; /* Process Unlocked */ __HAL_UNLOCK(hrtc); return HAL_OK; }
/** * @brief EXTI line detection callbacks. * @param GPIO_Pin: Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { static JOYState_TypeDef JoyState = JOY_NONE; static uint32_t debounce_time = 0; if(GPIO_Pin == GPIO_PIN_8) { /* Get the Joystick State */ JoyState = BSP_JOY_GetState(); CDC_DEMO_ProbeKey(JoyState); /* Clear joystick interrupt pending bits */ BSP_IO_ITClear(); if((CdcSelectMode == CDC_SELECT_MENU) && (CdcDemo.state != CDC_DEMO_RECEIVE)) { switch(JoyState) { case JOY_LEFT: LCD_LOG_ScrollBack(); break; case JOY_RIGHT: LCD_LOG_ScrollForward(); break; default: break; } } } if(CdcDemo.state == CDC_DEMO_CONFIGURATION) { if(GPIO_Pin == KEY_BUTTON_PIN) { /* Prevent debounce effect for user key */ if((HAL_GetTick() - debounce_time) > 50) { debounce_time = HAL_GetTick(); } else { return; } BSP_LCD_SetBackColor(LCD_COLOR_BLACK); /* Change the selection type */ if(CdcSelectMode == CDC_SELECT_MENU) { CDC_ChangeSelectMode(CDC_SELECT_CONFIG); } else if(CdcSelectMode == CDC_SELECT_CONFIG) { CDC_ChangeSelectMode(CDC_SELECT_MENU); } else if(CdcSelectMode == CDC_SELECT_FILE) { CDC_ChangeSelectMode(CDC_SELECT_FILE); } } } if(CdcDemo.state == CDC_DEMO_SEND) { if(GPIO_Pin == KEY_BUTTON_PIN) { /* Prevent debounce effect for user key */ if((HAL_GetTick() - debounce_time) > 50) { debounce_time = HAL_GetTick(); } else { return; } if(CdcDemo.Send_state == CDC_SEND_SELECT_FILE) { BSP_LCD_SetBackColor(LCD_COLOR_BLACK); /* Change the selection type */ if(CdcSelectMode == CDC_SELECT_MENU) { CDC_ChangeSelectMode(CDC_SELECT_FILE); } else if(CdcSelectMode == CDC_SELECT_FILE) { LCD_ClearTextZone(); LCD_LOG_UpdateDisplay(); CDC_ChangeSelectMode(CDC_SELECT_MENU); CdcDemo.Send_state = CDC_SEND_WAIT; } } } } }