/** ============================================================================
 *   @n@b Init_Cpsw
 *
 *   @b Description
 *   @n This API sets up the entire ethernet subsystem and all its associated
 *      components.
 *
 *   @param[in]  
 *   @n None
 * 
 *   @return
 *   @n None
 * =============================================================================
 */
Int32 Init_Cpsw (Void)
{                      
    Uint32       macPortNum, mtu = 1518;
    Uint8        macSrcAddress [2][6] =  {{0x10, 0x11, 0x12, 0x13, 0x14, 0x15},
                                          {0x0, 0x1, 0x2, 0x3, 0x4, 0x5}};
    Uint8        macAddress2 [6] = {0x20, 0x21, 0x22, 0x23, 0x24, 0x25};  /* MAC address for (EMAC2) Port 2 */
    Uint8        macAddressIPU [6] = {0x00, 0x10, 0xEC, 0x81, 0x35, 0xD8};//{0x10, 0x11, 0x12, 0x13, 0x14, 0x15};  /* MAC address for (EMAC1) Port 1 */
    Uint8		 macAddressPc[6] = {0x2,0x2,0x2,0x2,0x2,0x2};
//
//
//    Gpi HwMacPin;
//	Gpi_Init(&HwMacPin,HW_MAC_ADDR_SELECT,NULL,NULL,NULL,MAX_INTR_ITEM);
////############################ Hard coding  ###########################################
//	//GPIO 6 is driving by FPGA so DSP is not able to identify the switch position for
//		// Distinguishing the SPU board , so for the time being the GPIO read value is hard coding
//
//
//
//	//	Gpi_Read(&HwMacPin,&MacaddrNumber);  // any way read value is not using
//
//
//
//	MacaddrNumber = 0x00 ; // hard coded to SPU1
//
////############################### end of hard coding ###################################
//
//

	/* Initialize the SERDES modules */
	Init_SGMII_SERDES();
    
    /* Initialize the SGMII/Sliver submodules for the 
     * two corresponding MAC ports.
     */
    for (macPortNum = 0; macPortNum < NUM_MAC_PORTS; macPortNum++)
    {
    	if (Init_SGMII (macPortNum))
		  return -1;
        Init_MAC (macPortNum, &macSrcAddress[macPortNum][0], mtu);
    }

    if(cpswLpbkMode == CPSW_LOOPBACK_EXTERNAL)
    {
    	//configure pny in loopback mode for external loopback testing -nachiappan
        /* Setup the Phys by initializing the MDIO */
    	for (macPortNum = 0; macPortNum < NUM_MAC_PORTS; macPortNum++)
    	{
    		Init_MDIO (macPortNum);
    	}
    }

    /* Setup the Ethernet switch finally. */
    Init_Switch (mtu);
    if(Boardnum == SPU_BOARD_1)
    {
    	memcpy(macAddress1,Mac1,sizeof(macAddress1));
    	uart_write("\n MAC ADDR for SPU 1: 0x12, 0x34, 0x56, 0x12, 0x34, 0x56 \n");
    }
    else if(Boardnum == SPU_BOARD_2)
    {
    	memcpy(macAddress1,Mac2,sizeof(macAddress1));
    	uart_write("\n MAC ADDR for SPU 2: 0x12, 0x34, 0x56, 0x12, 0x34, 0x57 \n");
    }
    else
    {
    	uart_write("Invalid board\n");
    	while(1);
    }
    Switch_update_addr(0, macAddress1, 0);
    Switch_update_addr(0, macAddress2, 0);
    Switch_update_addr(2, macAddressIPU, 0);
    Switch_update_addr(1, macAddressPc, 0);

    phy_read_write(0);
    phy_read_write(1);
    /* CPSW subsystem setup done. Return success */
    return 0;    
}
Beispiel #2
0
extern void __interrupt _c_int00()
{
    /*-------------------------------------------------------------------------
    * After a reset, the device should have invalidated caches.  The caches will
    * still be configured as they were prior to the reset.  Since this code was 
    * loaded into L2, we will ensure that L2 is configured as all sram.  
    *------------------------------------------------------------------------*/
    CACHE_setL2Size (CACHE_0KCACHE);
    CACHE_setL1DSize(CACHE_L1_32KCACHE);
    CACHE_setL1PSize(CACHE_L1_32KCACHE);

    /*-------------------------------------------------------------------------
    * Set up the stack pointer in b15.
    * The stack pointer points 1 word past the top of the stack, so subtract
    * 1 word from the size. also the sp must be aligned on an 8-byte boundary
    *------------------------------------------------------------------------*/
    __asm("\t   MVKL\t\t   __TI_STACK_END - 4, SP");
    __asm("\t   MVKH\t\t   __TI_STACK_END - 4, SP");
    __asm("\t   AND\t\t   ~7,SP,SP");               

    /*-------------------------------------------------------------------------
    * Set up the global data page pointer in b14.
    *------------------------------------------------------------------------*/
    __asm("\t   MVKL\t\t   __TI_STATIC_BASE,DP");
    __asm("\t   MVKH\t\t   __TI_STATIC_BASE,DP");

    /*-------------------------------------------------------------------------
    * disable cache for all addrs over 0x1000:0000
    *------------------------------------------------------------------------*/
    memset((void*)0x01848040, 0, 960);

    /*-------------------------------------------------------------------------
    * disable mpax registers 3 and above
    *------------------------------------------------------------------------*/
    memset((void*)0x08000018, 0, 104);

    /*-------------------------------------------------------------------------
    * disable msmc ses mpax registers  except for the first one at each pri lev
    *------------------------------------------------------------------------*/
    if (DNUM == 0) 
    {
        int i;
        for (i=0; i < 16; i++)
            memset((void*)(0x0bc00600 + (i * 0x40) + 8), 0, 0x38);
    }

    /*-------------------------------------------------------------------------
    * Set up floating point registers
    *------------------------------------------------------------------------*/
    FADCR = 0; FMCR  = 0;

    /*-------------------------------------------------------------------------
    * Setup platform specifics, i.e. uarts, ethernet, etc.
    *------------------------------------------------------------------------*/
    if (DNUM == 0)
    {
        /*---------------------------------------------------------------------
        * Check if Boot time init configuration is loaded
        *
        * This code is reading l2 memory written by the host.  The values were
        * written before this code began running, so the cache invalidate at 
        * reset should ensure that when we read these values we will miss l1 and
        * read directly from l2.
        *--------------------------------------------------------------------*/
        platform_init_config config;
        config.pllm  = 0; // Original configuraion : default 0 -> 1 GHz 
        if (init_config.magic_number == 0xBABEFACE)
            config.pllm = init_config.dsp_pll_multiplier;

        /* Platform initialization */
        platform_init_flags flags;
        flags.pll  = 0x1;
        flags.ddr  = 0x1;
        flags.tcsl = 0x1;
        flags.phy  = 0x0;
        flags.ecc  = 0x1;

        platform_init(&flags, &config);
        platform_uart_init();
        platform_uart_set_baudrate(DEF_INIT_CONFIG_UART_BAUDRATE);

        memset((void*)&flags, 0 , sizeof(platform_init_flags));
        memset((void*)&config, 0, sizeof(platform_init_config));

        flags.pll = 0;
        flags.ddr = 0;
        flags.tcsl = 1;
        flags.phy = 1;
        flags.ecc = 0;
        platform_init(&flags, &config);

        Init_MAC(0);
        Init_MAC(1);

        Init_Switch(1506);
    }

    /*-------------------------------------------------------------------------
    * Once we write 0 to the boot magic addr, the host can proceed with the 
    * loading of another program that will subsequently run. We should ensure
    * that the caches are written back and clean at this point so that a 
    * subsequent writeback opertation will not clobber the program loaded 
    * from the host.  It is also clearly important that the loaded program 
    * did not write over the L2 area containing the remainder of this code.
    *------------------------------------------------------------------------*/
    BOOT_MAGIC_CONTENTS = 0;
    CACHE_wbInvL1d((void*)(BOOT_MAGIC_ADDR & ~0x3f), 64, CACHE_WAIT);

    wait_for_interrupt();

    /*-------------------------------------------------------------------------
    * We will now wait until an external entity writes the address to which we 
    * should jump 
    *------------------------------------------------------------------------*/
    while (1)
    {
        /*---------------------------------------------------------------------
        * invalidate the address so that we pick up the actual memory written by
        * the external entity.
        *--------------------------------------------------------------------*/
        CACHE_invL1d((void*)(BOOT_MAGIC_ADDR & ~0x3f), 64, CACHE_WAIT);
        void (*entry)() = (void (*)())(BOOT_MAGIC_CONTENTS);

        /*---------------------------------------------------------------------
        * If we have a non null pointer then we will branch to it. This 
        * essentially marks the end of this routine and the start of another,
        * so we should ensure that the caches are written back and clean at 
        * this point so that the following program starts with a clean cache 
        * system.
        *
        * It is also clearly important that the loaded program did not write 
        * over the L2 area containing this reset code. Since this reset code 
        * is entirely resident in the last 1/4 of L2, this area should not 
        * contain initialized data or code in the following program.
        *--------------------------------------------------------------------*/
        if (entry) 
        {
            flushCache();
            (*entry)();
        }
    }
}