void prom_halt(int halt) { struct pcs *p; /* * Turn off interrupts, for sanity. */ (void) splhigh(); /* * Set "boot request" part of the CPU state depending on what * we want to happen when we halt. */ p = LOCATE_PCS(hwrpb, hwrpb->rpb_primary_cpu_id); p->pcs_flags &= ~(PCS_RC | PCS_HALT_REQ); if (halt) p->pcs_flags |= PCS_HALT_STAY_HALTED; else p->pcs_flags |= PCS_HALT_WARM_BOOT; /* * Halt the machine. */ alpha_pal_halt(); }
void OSFpal() { struct rpb *r; struct pcs *p; r = (struct rpb *)HWRPB_ADDR; /* * Note, cpu_number() is a VMS op, can't necessarily call it. * Real fun: PAL_VMS_mfpr_whami == PAL_OSF1_rti... * We might not be rpb_primary_cpu_id, but it is supposed to go * first so the answer should apply to everyone. */ p = LOCATE_PCS(r, r->rpb_primary_cpu_id); printf("VMS PAL rev: 0x%lx\n", p->pcs_palrevisions[PALvar_OpenVMS]); printf("OSF PAL rev: 0x%lx\n", p->pcs_palrevisions[PALvar_OSF1]); if(p->pcs_pal_type==PAL_TYPE_OSF1) { printf("OSF PAL code already running.\n"); ptbr_save = ((struct alpha_pcb *)p)->apcb_ptbr; printf("PTBR is: 0x%lx\n", ptbr_save); return; } switch_palcode(); memcpy(&p->pcs_pal_rev, &p->pcs_palrevisions[PALvar_OSF1], sizeof(p->pcs_pal_rev)); printf("Switch to OSF PAL code succeeded.\n"); }
void _dec_1000a_init() { u_int64_t variation; platform.family = "AlphaServer 1000/1000A"; if ((platform.model = alpha_dsr_sysname()) == NULL) { variation = hwrpb->rpb_variation & SV_ST_MASK; if ((platform.model = alpha_variation_name(variation, cputype == ST_DEC_1000 ? dec_1000_variations : dec_1000a_variations)) == NULL) platform.model = alpha_unknown_sysname(); } switch(PCS_CPU_MAJORTYPE(LOCATE_PCS(hwrpb, 0))) { case PCS_PROC_EV4: case PCS_PROC_EV45: platform.iobus = "apecs"; break; default: platform.iobus = "cia"; break; } platform.cons_init = dec_1000a_cons_init; platform.device_register = dec_1000a_device_register; }
void hwrpb_primary_init(void) { struct pcb *pcb; struct pcs *p; p = LOCATE_PCS(hwrpb, hwrpb->rpb_primary_cpu_id); /* Initialize the primary's HWPCB and the Virtual Page Table Base. */ pcb = lwp_getpcb(&lwp0); memcpy(p->pcs_hwpcb, &pcb->pcb_hw, sizeof(pcb->pcb_hw)); hwrpb->rpb_vptb = VPTBASE; hwrpb->rpb_checksum = hwrpb_checksum(); }
void hwrpb_restart_setup(void) { struct pcs *p; /* Clear bootstrap-in-progress flag since we're done bootstrapping */ p = LOCATE_PCS(hwrpb, hwrpb->rpb_primary_cpu_id); p->pcs_flags &= ~PCS_BIP; /* when 'c'ontinuing from console halt, do a dump */ hwrpb->rpb_rest_term = (uint64_t)&XentRestart; hwrpb->rpb_rest_term_val = 0x1; hwrpb->rpb_checksum = hwrpb_checksum(); p->pcs_flags |= (PCS_RC | PCS_CV); }
uint64_t console_restart(struct trapframe *framep) { struct pcs *p; /* Clear restart-capable flag, since we can no longer restart. */ p = LOCATE_PCS(hwrpb, hwrpb->rpb_primary_cpu_id); p->pcs_flags &= ~PCS_RC; /* Fill in the missing frame slots */ framep->tf_regs[FRAME_PS] = p->pcs_halt_ps; framep->tf_regs[FRAME_PC] = p->pcs_halt_pc; framep->tf_regs[FRAME_T11] = p->pcs_halt_r25; framep->tf_regs[FRAME_RA] = p->pcs_halt_r26; framep->tf_regs[FRAME_T12] = p->pcs_halt_r27; panic("user requested console halt"); return (1); }
static void mbattach(device_t parent, device_t self, void *aux) { struct mainbus_attach_args ma; struct pcs *pcsp; int i, cpuattachcnt; extern int ncpus; mainbus_found = 1; printf("\n"); /* * Try to find and attach all of the CPUs in the machine. */ cpuattachcnt = 0; for (i = 0; i < hwrpb->rpb_pcs_cnt; i++) { pcsp = LOCATE_PCS(hwrpb, i); if ((pcsp->pcs_flags & PCS_PP) == 0) continue; ma.ma_name = "cpu"; ma.ma_slot = i; if (config_found(self, &ma, mbprint) != NULL) cpuattachcnt++; } if (ncpus != cpuattachcnt) printf("WARNING: %d cpus in machine, %d attached\n", ncpus, cpuattachcnt); if (platform.iobus != NULL) { ma.ma_name = platform.iobus; ma.ma_slot = 0; /* meaningless */ config_found(self, &ma, mbprint); } }