_mali_osk_errcode_t _mali_osk_notification_queue_dequeue( _mali_osk_notification_queue_t *queue, _mali_osk_notification_t **result ) { _mali_osk_errcode_t ret = _MALI_OSK_ERR_ITEM_NOT_FOUND; _mali_osk_notification_wrapper_t *wrapper_object; down(&queue->mutex); if (!list_empty(&queue->head)) { wrapper_object = list_entry(queue->head.next, _mali_osk_notification_wrapper_t, list); *result = &(wrapper_object->data); list_del_init(&wrapper_object->list); if (wrapper_object->data.magic_code != 0x31415926) { MALI_PRINT(("SEC WARNING : list entry magic_code not match : %x\n", wrapper_object->data.magic_code)); MALI_PRINT(("SEC WARNING : list entry notification type : %x\n", wrapper_object->data.notification_type)); MALI_PRINT(("SEC WARNING : list entry result buffer size : %x\n", wrapper_object->data.result_buffer_size)); MALI_PRINT(("SEC WARNING : list entry result buffer : %x\n", wrapper_object->data.result_buffer)); } else { ret = _MALI_OSK_ERR_OK; } } up(&queue->mutex); return ret; }
static mali_bool mali_dvfs_table_update(void) { unsigned int exynos_result_of_asv_group; unsigned int target_asv; unsigned int i; exynos_result_of_asv_group = mali_asv_group = exynos_result_of_asv & 0xf; target_asv = exynos_result_of_asv >> 28; MALI_PRINT(("exynos_result_of_asv_group = 0x%x, target_asv = 0x%x\n", exynos_result_of_asv_group, target_asv)); if (target_asv == 0x8) { //SUPPORT_1400MHZ for (i = 0; i < MALI_DVFS_STEPS; i++) { mali_dvfs[i].vol = asv_3d_volt_5_table[exynos_result_of_asv_group][i]; MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol)); } } else if (target_asv == 0x4){ //SUPPORT_1200MHZ for (i = 0; i < MALI_DVFS_STEPS; i++) { mali_dvfs[i].vol = asv_3d_volt_8_table[exynos_result_of_asv_group][i]; MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol)); } } return MALI_TRUE; }
/* is called from OS specific driver entry point */ _mali_osk_errcode_t mali_kernel_constructor( void ) { _mali_osk_errcode_t err; err = mali_platform_init(); if (_MALI_OSK_ERR_OK != err) goto error1; err = _mali_osk_init(); if (_MALI_OSK_ERR_OK != err) goto error2; MALI_DEBUG_PRINT(2, ("\n")); MALI_DEBUG_PRINT(2, ("Inserting Mali v%d device driver. \n",_MALI_API_VERSION)); MALI_DEBUG_PRINT(2, ("Compiled: %s, time: %s.\n", __DATE__, __TIME__)); MALI_DEBUG_PRINT(2, ("Svn revision: %s\n", SVN_REV_STRING)); err = initialize_subsystems(); if (_MALI_OSK_ERR_OK != err) goto error3; MALI_PRINT(("Mali device driver %s loaded\n", SVN_REV_STRING)); MALI_SUCCESS; error3: MALI_PRINT(("Mali subsystems failed\n")); _mali_osk_term(); error2: MALI_PRINT(("Mali device driver init failed\n")); if (_MALI_OSK_ERR_OK != mali_platform_deinit()) { MALI_PRINT(("Failed to deinit platform\n")); } error1: MALI_PRINT(("Failed to init platform\n")); MALI_ERROR(err); }
_mali_osk_errcode_t malipmm_powerup( u32 cores ) { _mali_osk_errcode_t err = _MALI_OSK_ERR_OK; _mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR; /* If all the cores are powered down, power up the MALI */ if (pmm->cores_powered == 0) { mali_platform_power_mode_change(MALI_POWER_MODE_ON); #if MALI_PMM_RUNTIME_JOB_CONTROL_ON /* Initiate the power up */ if (_mali_osk_pmm_dev_activate() < 0) { MALI_PRINT(("PMM: Try again PD_G3D enable\n")); if (mali_pd_enable() < 0) { MALI_PRINT(("PMM: Mali PMM device activate failed\n")); err = _MALI_OSK_ERR_FAULT; return err; } } #endif } #if USING_MALI_PMU err = mali_pmm_pmu_powerup( cores ); #endif #if MALI_PMM_RUNTIME_JOB_CONTROL_ON mali_platform_powerup(cores); #endif return err; }
static mali_bool init_mali_clock(void) { mali_bool ret = MALI_TRUE; if (mali_clock != 0) return ret; // already initialized mali_dvfs_lock = _mali_osk_lock_init(_MALI_OSK_LOCKFLAG_NONINTERRUPTABLE | _MALI_OSK_LOCKFLAG_ONELOCK, 0, 0); if (mali_dvfs_lock == NULL) return _MALI_OSK_ERR_FAULT; if (mali_clk_set_rate(mali_gpu_clk, GPU_MHZ) == MALI_FALSE) { ret = MALI_FALSE; goto err_clock_get; } MALI_PRINT(("init_mali_clock mali_clock %p \n", mali_clock)); #ifdef CONFIG_REGULATOR #if USING_MALI_PMM g3d_regulator = regulator_get(&mali_gpu_device.dev, "vdd_g3d"); #else g3d_regulator = regulator_get(NULL, "vdd_g3d"); #endif if (IS_ERR(g3d_regulator)) { MALI_PRINT( ("MALI Error : failed to get vdd_g3d\n")); ret = MALI_FALSE; goto err_regulator; } regulator_enable(g3d_regulator); MALI_DEBUG_PRINT(1, ("= regulator_enable -> use cnt: %d \n",mali_regulator_get_usecount())); mali_regulator_set_voltage(mali_gpu_vol, mali_gpu_vol); #endif MALI_DEBUG_PRINT(2, ("MALI Clock is set at mali driver\n")); MALI_DEBUG_PRINT(3,("::clk_put:: %s mali_parent_clock - normal\n", __FUNCTION__)); MALI_DEBUG_PRINT(3,("::clk_put:: %s mpll_clock - normal\n", __FUNCTION__)); mali_clk_put(MALI_FALSE); gpu_power_state = 0; bPoweroff = 1; return MALI_TRUE; #ifdef CONFIG_REGULATOR err_regulator: regulator_put(g3d_regulator); #endif err_clock_get: mali_clk_put(MALI_TRUE); return ret; }
_mali_osk_errcode_t mali_platform_init(_mali_osk_resource_t *resource) { unsigned long rate; int clk_div; int mali_used = 0; //get mali ahb clock h_ahb_mali = clk_get(NULL, "ahb_mali"); if(!h_ahb_mali){ MALI_PRINT(("try to get ahb mali clock failed!\n")); } //get mali clk h_mali_clk = clk_get(NULL, "mali"); if(!h_mali_clk){ MALI_PRINT(("try to get mali clock failed!\n")); } h_ve_pll = clk_get(NULL, "ve_pll"); if(!h_ve_pll){ MALI_PRINT(("try to get ve pll clock failed!\n")); } //set mali parent clock if(clk_set_parent(h_mali_clk, h_ve_pll)){ MALI_PRINT(("try to set mali clock source failed!\n")); } //set mali clock rate = clk_get_rate(h_ve_pll); if(!script_parser_fetch("mali_para", "mali_used", &mali_used, 1)) { if (mali_used == 1) { if (!script_parser_fetch("mali_para", "mali_clkdiv", &clk_div, 1)) { if (clk_div > 0) { pr_info("mali: use config clk_div %d\n", clk_div); mali_clk_div = clk_div; } } } } pr_info("mali: clk_div %d\n", mali_clk_div); rate /= mali_clk_div; if(clk_set_rate(h_mali_clk, rate)){ MALI_PRINT(("try to set mali clock failed!\n")); } if(clk_enable(h_ahb_mali)){ MALI_PRINT(("try to enable mali ahb failed!\n")); } if(clk_enable(h_mali_clk)){ MALI_PRINT(("try to enable mali clock failed!\n")); } if(clk_reset(h_mali_clk,0)){ MALI_PRINT(("try to reset release failed!\n")); } MALI_PRINT(("mali clock set completed, clock is %d Mhz\n", rate)); MALI_SUCCESS; }
static mali_bool mali_dvfs_table_update(void) { unsigned int i; for (i = 0; i < MALI_DVFS_STEPS; i++) { MALI_PRINT((":::exynos_result_of_asv : %d\n", exynos_result_of_asv)); mali_dvfs[i].vol = asv_3d_volt_9_table[i][exynos_result_of_asv]; MALI_PRINT(("mali_dvfs[%d].vol = %d\n", i, mali_dvfs[i].vol)); } return MALI_TRUE; }
/***************************************************************************** function name : mali_clk_get description : clock get input vars : void output vars : NA return value : mali_bool calls : clk_get called : mali_platform_powerup history : 1.data : 04/03/2014 author : s00250033 modify : new *****************************************************************************/ mali_bool mali_clk_get(struct platform_device *pdev) { MALI_DEBUG_PRINT(3, ("mali_clk_get begin\n")); #if 0 /* open and get the clk and regulator without mali pmm */ gpu_pll = clk_get(&pdev->dev,"clk_gpupll_src"); if (IS_ERR(gpu_pll)) { MALI_PRINT( ("MALI Error : failed to get source gpu_pll\n")); return _MALI_OSK_ERR_FAULT; } /* open and get the clk and regulator without mali pmm */ sys_pll = clk_get(&pdev->dev,"clk_syspll_src"); if (IS_ERR(sys_pll)) { MALI_PRINT( ("MALI Error : failed to get source sys_pll\n")); return _MALI_OSK_ERR_FAULT; } /* open and get the clk and regulator without mali pmm */ media_pll = clk_get(&pdev->dev,"clk_medpll_src"); if (IS_ERR(media_pll)) { MALI_PRINT( ("MALI Error : failed to get source media_pll\n")); return _MALI_OSK_ERR_FAULT; } #endif /* open and get the clk and regulator without mali pmm */ mali_clock = clk_get(&pdev->dev,"clk_g3d"); if (IS_ERR(mali_clock)) { MALI_PRINT( ("MALI Error : failed to get source CLK_G3D\n")); return _MALI_OSK_ERR_FAULT; } media_clk_g3d = clk_get(&pdev->dev,"pclk_g3d"); if (IS_ERR(media_clk_g3d)) { MALI_PRINT( ("MALI Error : failed to get source PCLK_G3D\n")); return _MALI_OSK_ERR_FAULT; } MALI_DEBUG_PRINT(3, ("mali_clk_get end\n")); return MALI_TRUE; }
_mali_osk_errcode_t mali_platform_powerup(u32 cores) { #if USING_MALI_PMM u32 cores_pmu; u32 stat; u32 timeout; MALI_DEBUG_ASSERT_POINTER(pmu_info); MALI_DEBUG_ASSERT( cores != 0 ); /* Shouldn't receive zero from PMM */ MALI_DEBUG_PRINT( 4, ("PLATFORM mali400-pmu: power up (0x%x)\n", cores) ); /*enable mali axi/apb clock*/ if(mali_clk_flag == 0) { //printk(KERN_WARNING "enable mali clock\n"); //MALI_PRINT(("enable mali clock\n")); mali_clk_flag = 1; if(clk_enable(h_ahb_mali)) { MALI_PRINT(("try to enable mali ahb failed!\n")); } if(clk_enable(h_mali_clk)) { MALI_PRINT(("try to enable mali clock failed!\n")); } } /* Don't use interrupts - just poll status */ pmu_reg_write( pmu_info, (u32)PMU_REG_ADDR_MGMT_INT_MASK, 0 ); cores_pmu = pmu_translate_cores_to_pmu(cores); pmu_reg_write( pmu_info, (u32)PMU_REG_ADDR_MGMT_POWER_UP, cores_pmu ); timeout = 10; /* 10ms */ do { /* Get status of sleeping cores */ stat = pmu_reg_read( pmu_info, (u32)PMU_REG_ADDR_MGMT_STATUS ); stat &= cores_pmu; if( stat == 0 ) break; /* All cores we wanted are now awake */ _mali_osk_time_ubusydelay(1000); /* 1ms */ timeout--; } while( timeout > 0 ); if( timeout == 0 ) MALI_ERROR(_MALI_OSK_ERR_TIMEOUT); MALI_SUCCESS; #else /* Nothing to do when not using PMM */ MALI_SUCCESS; #endif }
int mali_dvfs_bottom_lock_pop(void) { int prev_status = _mali_osk_atomic_read(&bottomlock_status); if (prev_status <= 0) { MALI_PRINT(("gpu bottom lock status is not valid for pop\n")); return -1; } else if (prev_status == 1) { bottom_lock_step = 0; MALI_PRINT(("gpu bottom lock release\n")); } return _mali_osk_atomic_dec_return(&bottomlock_status); }
static mali_bool mali_dvfs_table_update(void) { unsigned int i; unsigned int step_num = MALI_DVFS_STEPS; if(samsung_rev() < EXYNOS4412_REV_2_0) step_num = MALI_DVFS_STEPS - 1; if(soc_is_exynos4412()) { if (exynos_armclk_max == 1000000) { MALI_PRINT(("::C::exynos_result_of_asv : %d\n", exynos_result_of_asv)); for (i = 0; i < step_num; i++) { mali_dvfs[i].vol = asv_3d_volt_9_table_1ghz_type[i][exynos_result_of_asv]; MALI_PRINT(("mali_dvfs[%d].vol = %d \n", i, mali_dvfs[i].vol)); } } else if(((is_special_flag() >> G3D_LOCK_FLAG) & 0x1) && (samsung_rev() >= EXYNOS4412_REV_2_0)) { MALI_PRINT(("::L::exynos_result_of_asv : %d\n", exynos_result_of_asv)); for (i = 0; i < step_num; i++) { mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv] + 25000; MALI_PRINT(("mali_dvfs[%d].vol = %d \n ", i, mali_dvfs[i].vol)); } } else if (samsung_rev() >= EXYNOS4412_REV_2_0) { MALI_PRINT(("::P::exynos_result_of_asv : %d\n", exynos_result_of_asv)); for (i = 0; i < step_num; i++) { mali_dvfs[i].vol = asv_3d_volt_9_table_for_prime[i][exynos_result_of_asv]; MALI_PRINT(("mali_dvfs[%d].vol = %d \n", i, mali_dvfs[i].vol)); } } else { MALI_PRINT(("::Q::exynos_result_of_asv : %d\n", exynos_result_of_asv)); for (i = 0; i < step_num; i++) { mali_dvfs[i].vol = asv_3d_volt_9_table[i][exynos_result_of_asv]; MALI_PRINT(("mali_dvfs[%d].vol = %d \n", i, mali_dvfs[i].vol)); } } }
void malipmm_state_dump() { _mali_pmm_internal_state_t *pmm = GET_PMM_STATE_PTR; if( !pmm ) { MALI_PRINT(("PMM: Null state\n")); } else { MALI_PRINT(("PMM state:\nstatus=%d\npolicy=%d\ncheck_policy=%d\nstate=%d\n", pmm->status, pmm->policy, pmm->check_policy, pmm->state)); MALI_PRINT(("PMM cores:\ncores_registered=%d\ncores_powered=%d\ncores_idle=%d\ncores_pend_down=%d\ncores_pend_up=%d\ncores_ack_down=%d\ncores_ack_up=%d\n", pmm->cores_registered, pmm->cores_powered, pmm->cores_idle, pmm->cores_pend_down, pmm->cores_pend_up, pmm->cores_ack_down, pmm->cores_ack_up)); MALI_PRINT(("PMM misc:\npmu_init=%d\nmessages_queued=%d\nwaiting=%d\nno_events=%d\nmissed=%d\nfatal_power_err=%d\n", pmm->pmu_initialized, _mali_osk_atomic_read( &(pmm->messages_queued) ), pmm->waiting, pmm->no_events, pmm->missed, pmm->fatal_power_err)); } }
void _mali_pmm_trace_state_change( mali_pmm_state old, mali_pmm_state newstate ) { if( old != newstate ) { MALI_PRINT( ("PMM Trace: State changed from %s to %s", pmm_trace_state[old], pmm_trace_state[newstate]) ); } }
static void mali_pm_shutdown(struct platform_device *pdev) { MALI_PRINT(("Mali shutdown!!\n")); mali_dvfs_device_state =_MALI_DEVICE_SHUTDOWN; exynos_pd_enable(&exynos4_device_pd[PD_G3D].dev); return; }
void mali_driver_exit(void) { MALI_DEBUG_PRINT(2, ("\n")); MALI_DEBUG_PRINT(2, ("Unloading Mali v%d device driver.\n",_MALI_API_VERSION)); /* No need to terminate sysfs, this will be done automatically along with device termination */ mali_terminate_subsystems(); mali_osk_low_level_mem_term(); mali_platform_deinit(); terminate_kernel_device(); _mali_dev_platform_unregister(); #if MALI_LICENSE_IS_GPL /* @@@@ clean up the work queues! This should not be terminated here, since it isn't inited in the function above! */ flush_workqueue(mali_wq); destroy_workqueue(mali_wq); mali_wq = NULL; #endif MALI_PRINT(("Mali device driver unloaded\n")); }
int init_mali(void) { int ret = 0; ret = map_errcode(initialize_kernel_device()); if (0 != ret) goto initialize_kernel_device_failed; ret = map_errcode(mali_platform_init()); if (0 != ret) goto platform_init_failed; mali_osk_low_level_mem_init(); ret = map_errcode(mali_initialize_subsystems()); if (0 != ret) goto initialize_subsystems_failed; ret = initialize_sysfs(); if (0 != ret) goto initialize_sysfs_failed; MALI_PRINT(("Mali device driver loaded\n")); return 0; /* Success */ /* Error handling */ initialize_sysfs_failed: mali_terminate_subsystems(); initialize_subsystems_failed: mali_osk_low_level_mem_term(); mali_platform_deinit(); platform_init_failed: terminate_kernel_device(); initialize_kernel_device_failed: _mali_dev_platform_unregister(); platform_register_failed: return ret; }
void mali_clk_set_rate(unsigned int clk, unsigned int mhz) { int err; unsigned long rate = (unsigned long)clk * (unsigned long)mhz; _mali_osk_lock_wait(mali_freq_lock, _MALI_OSK_LOCKMODE_RW); MALI_DEBUG_PRINT(3, ("Mali platform: Setting frequency to %d mhz\n", clk)); if (mali_clk_get() == MALI_FALSE) { _mali_osk_lock_signal(mali_freq_lock, _MALI_OSK_LOCKMODE_RW); return; } err = clk_set_rate(mali_clock, rate); if (err) MALI_PRINT_ERROR(("Failed to set Mali clock: %d\n", err)); rate = clk_get_rate(mali_clock); GPU_MHZ = mhz; mali_gpu_clk = rate / mhz; MALI_PRINT(("Mali freq %dMhz\n", rate / mhz)); mali_clk_put(MALI_FALSE); _mali_osk_lock_signal(mali_freq_lock, _MALI_OSK_LOCKMODE_RW); }
/***************************************************************************** function name : mali_platform_powerdown description : powerdown mali by calling interface of low software input vars : void output vars : NA return value : _mali_osk_errcode_t calls : AMAPI_mali_clk_off AMAPI_mali_power_down called : mali_platform_power_mode_change history : 1.data : 04/03/2014 author : s00250033 modify : new *****************************************************************************/ _mali_osk_errcode_t mali_platform_powerdown(void) { MALI_DEBUG_PRINT(3,("before mali_platform_powerdown state %x \n", g_swGpuPowerState)); /* debug fs Powerdown */ if (0==s_uwDebugFsPowerDown) MALI_SUCCESS; if (g_swGpuPowerState != MALI_FALSE) { MALI_DEBUG_PRINT( 3,("disable clock\n")); /*clk and regulator off*/ mali_regulator_disable(); mali_clock_off(); g_swGpuPowerState = MALI_FALSE; /*info DVFS to stop*/ #if MALI_DVFS_ENABLED pwrctrl_dfs_gpu_disable(); #endif } else { MALI_PRINT(("mali_platform_powerdown gpu_power_state == 0 \n")); } MALI_DEBUG_PRINT(3,("after mali_platform_powerdown state %x \n", g_swGpuPowerState)); MALI_SUCCESS; }
int change_dvfs_tableset(int change_clk, int change_step) { int err; if (change_clk < mali_dvfs_all[1].clock) { mali_dvfs[change_step].clock = mali_dvfs_all[0].clock; } else if (change_clk < mali_dvfs_all[2].clock && change_clk >= mali_dvfs_all[1].clock) { mali_dvfs[change_step].clock = mali_dvfs_all[1].clock; } else if (change_clk < mali_dvfs_all[3].clock && change_clk >= mali_dvfs_all[2].clock) { mali_dvfs[change_step].clock = mali_dvfs_all[2].clock; } else { mali_dvfs[change_step].clock = mali_dvfs_all[3].clock; } MALI_PRINT((":::mali dvfs step %d clock and voltage = %d Mhz, %d V\n",change_step, mali_dvfs[change_step].clock, mali_dvfs[change_step].vol)); if (maliDvfsStatus.currentStep == change_step) { #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[change_step].vol, mali_dvfs[change_step].vol); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[change_step].clock, mali_dvfs[change_step].freq); #if CPUFREQ_LOCK_DURING_440 /* lock/unlock CPU freq by Mali */ if (mali_dvfs[change_step].clock == 440) err = cpufreq_lock_by_mali(1200); else cpufreq_unlock_by_mali(); #endif } return mali_dvfs[change_step].clock; }
void mali_driver_exit(void) { MALI_DEBUG_PRINT(2, ("\n")); MALI_DEBUG_PRINT(2, ("Unloading Mali v%d device driver.\n",_MALI_API_VERSION)); #if MALI_LICENSE_IS_GPL && defined(CONFIG_MALI_UMP_R3P1_DEBUG_MEM_USAGE_FOR_OOM) unregister_oom_notifier(&mali_oom_notifier); #endif /* No need to terminate sysfs, this will be done automatically along with device termination */ #if MALI_INTERNAL_TIMELINE_PROFILING_ENABLED _mali_internal_profiling_term(); #endif mali_terminate_subsystems(); mali_osk_low_level_mem_term(); mali_platform_deinit(); terminate_kernel_device(); _mali_dev_platform_unregister(); #if MALI_LICENSE_IS_GPL /* @@@@ clean up the work queues! This should not be terminated here, since it isn't inited in the function above! */ flush_workqueue(mali_wq); destroy_workqueue(mali_wq); mali_wq = NULL; #endif MALI_PRINT(("Mali device driver unloaded\n")); }
int change_dvfs_tableset(int change_clk, int change_step) { if (change_clk < mali_dvfs_all[1].clock) { mali_dvfs[change_step].clock = mali_dvfs_all[0].clock; mali_dvfs[change_step].vol = mali_dvfs[0].vol; } else if (change_clk < mali_dvfs_all[2].clock && change_clk >= mali_dvfs_all[1].clock) { mali_dvfs[change_step].clock = mali_dvfs_all[1].clock; mali_dvfs[change_step].vol = mali_dvfs[1].vol; } else if (change_clk < mali_dvfs_all[3].clock && change_clk >= mali_dvfs_all[2].clock) { mali_dvfs[change_step].clock = mali_dvfs_all[2].clock; mali_dvfs[change_step].vol = mali_dvfs[2].vol; } else { mali_dvfs[change_step].clock = mali_dvfs_all[3].clock; mali_dvfs[change_step].vol = mali_dvfs[3].vol; } MALI_PRINT((":::mali dvfs step %d clock and voltage = %d Mhz, %d V\n",change_step, mali_dvfs[change_step].clock, mali_dvfs[change_step].vol)); if (maliDvfsStatus.currentStep == change_step) { #ifdef CONFIG_REGULATOR /*change the voltage*/ mali_regulator_set_voltage(mali_dvfs[change_step].vol, mali_dvfs[change_step].vol); #endif /*change the clock*/ mali_clk_set_rate(mali_dvfs[change_step].clock, mali_dvfs[change_step].freq); } return mali_dvfs[change_step].clock; }
int mali_driver_init(void) { int err; #if USING_MALI_PMM #if MALI_LICENSE_IS_GPL #ifdef CONFIG_PM err = _mali_dev_platform_register(); if (err) { return err; } #endif #endif #endif err = mali_kernel_constructor(); if (_MALI_OSK_ERR_OK != err) { #if USING_MALI_PMM #if MALI_LICENSE_IS_GPL #ifdef CONFIG_PM _mali_dev_platform_unregister(); #endif #endif #endif MALI_PRINT(("Failed to initialize driver (error %d)\n", err)); return -EFAULT; } /* print build options */ MALI_DEBUG_PRINT(2, ("%s\n", __malidrv_build_info())); return 0; }
void _mali_pmm_trace_policy_change( mali_pmm_policy old, mali_pmm_policy newpolicy ) { if( old != newpolicy ) { MALI_PRINT( ("PMM Trace: Policy changed from %s to %s", pmm_trace_policy[old], pmm_trace_policy[newpolicy]) ); } }
_mali_osk_errcode_t mali_platform_powerdown(u32 cores) { MALI_DEBUG_PRINT(3,("power down is called in mali_platform_powerdown state %x core %x \n", gpu_power_state, cores)); if (gpu_power_state != 0) // power down after state is 0 { gpu_power_state = gpu_power_state & (~cores); if (gpu_power_state == 0) { MALI_DEBUG_PRINT( 3,("disable clock\n")); disable_mali_clocks(); g3d_power_domain_control(0); } } else { MALI_PRINT(("mali_platform_powerdown gpu_power_state == 0 and cores %x \n", cores)); } bPoweroff=1; MALI_SUCCESS; }
static unsigned int decideNextStatus(unsigned int utilization) { static unsigned int level = 0; // 0:stay, 1:up static int mali_dvfs_clk = 0; if (mali_runtime_resumed >= 0) { level = mali_runtime_resumed; mali_runtime_resumed = -1; return level; } if (mali_dvfs_threshold[maliDvfsStatus.currentStep].upthreshold <= mali_dvfs_threshold[maliDvfsStatus.currentStep].downthreshold) { MALI_PRINT(("upthreadshold is smaller than downthreshold: %d < %d\n", mali_dvfs_threshold[maliDvfsStatus.currentStep].upthreshold, mali_dvfs_threshold[maliDvfsStatus.currentStep].downthreshold)); return level; } if (utilization > (int)(255 * mali_dvfs_threshold[maliDvfsStatus.currentStep].upthreshold / 100) && level < MALI_DVFS_STEPS - 1) { level++; } if (utilization < (int)(255 * mali_dvfs_threshold[maliDvfsStatus.currentStep].downthreshold / 100) && level > 0) { level--; } if (_mali_osk_atomic_read(&bottomlock_status) > 0) { if (level < bottom_lock_step) level = bottom_lock_step; } return level; }
int mali_dvfs_bottom_lock_push(int lock_step) { int prev_status = _mali_osk_atomic_read(&bottomlock_status); if (prev_status < 0) { MALI_PRINT(("gpu bottom lock status is not valid for push\n")); return -1; } // not a bad idea to limit locking to 4th step, so let's leave this -gm if (samsung_rev() < EXYNOS4412_REV_2_0) lock_step = min(lock_step, MALI_DVFS_STEPS - 2); else lock_step = min(lock_step, MALI_DVFS_STEPS - 1); if (bottom_lock_step < lock_step) { bottom_lock_step = lock_step; if (get_mali_dvfs_status() < lock_step) { mali_regulator_set_voltage(mali_dvfs[lock_step].vol, mali_dvfs[lock_step].vol); mali_clk_set_rate(mali_dvfs[lock_step].clock, mali_dvfs[lock_step].freq); set_mali_dvfs_current_step(lock_step); } } return _mali_osk_atomic_inc_return(&bottomlock_status); }
_mali_osk_errcode_t mali_platform_deinit(_mali_osk_resource_type_t *type) { //close clock MALI_PRINT(("free mali clk\n")); clk_disable(h_mali_clk); clk_disable(h_ahb_mali); MALI_SUCCESS; }
int mali_voltage_lock_pop(void) { if (_mali_osk_atomic_read(&voltage_lock_status) <= 0) { MALI_PRINT(("gpu voltage lock status is not valid for pop\n")); return -1; } return _mali_osk_atomic_dec_return(&voltage_lock_status); }
static void pmu_dump_regs( platform_pmu_t *pmu ) { u32 addr; for( addr = 0x0; addr < PMU_REGISTER_ADDRESS_SPACE_SIZE; addr += 0x4 ) { MALI_PRINT( ("PMU_REG: 0x%08x: 0x%04x\n", (addr + pmu->reg_base_addr), pmu_reg_read( pmu, addr ) ) ); } }
int mali_dvfs_bottom_lock_pop(void) { if (_mali_osk_atomic_read(&bottomlock_status) <= 0) { MALI_PRINT(("gpu bottom lock status is not valid for pop")); return -1; } return _mali_osk_atomic_dec_return(&bottomlock_status); }