static void enable_clock_gating(device_t dev) { u32 reg32; u16 reg16; RCBA32_AND_OR(0x2234, ~0UL, 0xf); reg16 = pci_read_config16(dev, GEN_PMCON_1); reg16 |= (1 << 2) | (1 << 11); pci_write_config16(dev, GEN_PMCON_1, reg16); pch_iobp_update(0xEB007F07, ~0UL, (1 << 31)); pch_iobp_update(0xEB004000, ~0UL, (1 << 7)); pch_iobp_update(0xEC007F07, ~0UL, (1 << 31)); pch_iobp_update(0xEC004000, ~0UL, (1 << 7)); reg32 = RCBA32(CG); reg32 |= (1 << 31); reg32 |= (1 << 29) | (1 << 28); reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); reg32 |= (1 << 16); reg32 |= (1 << 17); reg32 |= (1 << 18); reg32 |= (1 << 22); reg32 |= (1 << 23); reg32 &= ~(1 << 20); reg32 |= (1 << 19); reg32 |= (1 << 0); reg32 |= (0xf << 1); RCBA32(CG) = reg32; RCBA32_OR(0x38c0, 0x7); RCBA32_OR(0x36d4, 0x6680c004); RCBA32_OR(0x3564, 0x3); }
void mainboard_romstage_entry(unsigned long bist) { const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 }; if (bist == 0) enable_lapic(); /* Disable watchdog timer */ RCBA32(0x3410) = RCBA32(0x3410) | 0x20; /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init(); nm10_enable_lpc(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); enable_smbus(); pineview_early_initialization(); post_code(0x30); printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(0, spd_addrmap); printk(BIOS_DEBUG, "Memory initialized\n"); post_code(0x31); ram_check(0x200000,0x300000); rcba_config(); }
static void enable_port80_on_lpc(void) { /* Enable port 80 POST on LPC. The chipset does this by deafult, * but it doesn't appear to hurt anything. */ u32 gcs = RCBA32(GCS); gcs = gcs & ~0x4; RCBA32(GCS) = gcs; }
static void mainboard_init(device_t dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; RCBA32(0x38c0) = 0x00000007; pc_keyboard_init(); }
static void enable_hpet(void) { u32 reg32; /* Move HPET to default address 0xfed00000 and enable it */ reg32 = RCBA32(RCBA_HPTC); reg32 |= (1 << 7); // HPET Address Enable reg32 &= ~(3 << 0); RCBA32(RCBA_HPTC) = reg32; }
static void rcba_config(void) { /* Set up virtual channel 0 */ RCBA32(0x0014) = 0x80000001; RCBA32(0x001c) = 0x03128010; /* Device 1f interrupt pin register */ RCBA32(0x3100) = 0x00042210; RCBA32(0x3108) = 0x10004321; RCBA32(0x3104) = 0x00002100; /* PCIe Interrupts */ RCBA32(0x310c) = 0x00214321; /* HD Audio Interrupt */ RCBA32(0x3110) = 0x00000001; /* dev irq route register */ RCBA16(0x3140) = 0x0132; RCBA16(0x3142) = 0x0146; RCBA16(0x3144) = 0x0237; RCBA16(0x3146) = 0x3201; RCBA16(0x3148) = 0x0146; /* Enable IOAPIC */ RCBA8(0x31ff) = 0x03; RCBA32(0x3418) = 0x003000e2; RCBA32(0x3418) |= 1; }
static void rcba_config(void) { u32 reg32; /* * GFX INTA -> PIRQA (MSI) * D28IP_P2IP WLAN INTA -> PIRQB * D28IP_P3IP ETH0 INTC -> PIRQD * D29IP_E1P EHCI1 INTA -> PIRQE * D26IP_E2P EHCI2 INTA -> PIRQE * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQG * D31IP_TTIP THRT INTC -> PIRQH * D27IP_ZIP HDA INTA -> PIRQG (MSI) * * Trackpad DVT PIRQA (16) * Trackpad DVT PIRQE (20) */ /* Device interrupt pin register (board specific) */ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); RCBA32(D30IP) = (NOINT << D30IP_PIP); RCBA32(D29IP) = (INTA << D29IP_E1P); RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) | (INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) | (NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) | (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); RCBA32(D25IP) = (NOINT << D25IP_LIP); RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); /* Device interrupt route registers */ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); reg32 |= PCH_DISABLE_ALWAYS; /* Disable PCI bridge so MRC does not probe this bus */ reg32 |= PCH_DISABLE_P2P; RCBA32(FD) = reg32; }
void rcba_config(void) { u32 reg32; /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); reg32 |= PCH_DISABLE_ALWAYS; /* Disable PCI bridge so MRC does not probe this bus */ reg32 |= PCH_DISABLE_P2P; RCBA32(FD) = reg32; }
static void rcba_config(void) { u32 reg32; southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); reg32 |= PCH_DISABLE_ALWAYS; RCBA32(FD) = reg32; }
static void mainboard_init(device_t dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; RCBA32(0x38c0) = 0x00000007; /* This sneaked in here, because X201 SuperIO chip isn't really connected to anything and hence we don't init it. */ pc_keyboard_init(); }
static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save) { #define IOTRAP(x) (trap_sts & (1 << x)) u32 trap_sts, trap_cycle; u32 data, mask = 0; int i; trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR trap_cycle = RCBA32(0x1e10); for (i=16; i<20; i++) { if (trap_cycle & (1 << i)) mask |= (0xff << ((i - 16) << 3)); } /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { if (gnvs && gnvs->smif) io_trap_handler(gnvs->smif); // call function smif return; } /* IOTRAP(2) currently unused * IOTRAP(1) currently unused */ /* IOTRAP(0) SMIC */ if (IOTRAP(0)) { if (!(trap_cycle & (1 << 24))) { // It's a write printk(BIOS_DEBUG, "SMI1 command\n"); data = RCBA32(0x1e18); data &= mask; // if (smi1) // southbridge_smi_command(data); // return; } // Fall through to debug } printk(BIOS_DEBUG, " trapped io address = 0x%x\n", trap_cycle & 0xfffc); for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i); printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf); printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask); printk(BIOS_DEBUG, " read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write"); if (!(trap_cycle & (1 << 24))) { /* Write Cycle */ data = RCBA32(0x1e18); printk(BIOS_DEBUG, " iotrap written data = 0x%08x\n", data); } #undef IOTRAP }
void pineview_early_initialization(void) { /* Print some chipset specific information */ printk(BIOS_DEBUG, "Intel Pineview northbridge\n"); /* Setup all BARs required for early PCIe and raminit */ pineview_setup_bars(); /* Change port80 to LPC */ RCBA32(GCS) &= (~0x04); RCBA32(0x2010) |= (1 << 10); }
static void enable_hpet(void) { u32 reg32; /* Move HPET to default address 0xfed00000 and enable it */ reg32 = RCBA32(HPTC); reg32 |= (1 << 7); // HPET Address Enable reg32 &= ~(3 << 0); RCBA32(HPTC) = reg32; write32((u32 *)0xfed00010, read32((u32 *)0xfed00010) | 1); }
static inline int iobp_poll(void) { unsigned int try; for (try = IOBP_RETRY; try > 0; try--) { u16 status = RCBA16(IOBPS); if ((status & IOBPS_READY) == 0) return 1; udelay(10); } printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n"); return 0; } u32 pch_iobp_read(u32 address) { u16 status; if (!iobp_poll()) return 0; /* Set the address */ RCBA32(IOBPIRI) = address; /* READ OPCODE */ status = RCBA16(IOBPS); status &= ~IOBPS_MASK; status |= IOBPS_READ; RCBA16(IOBPS) = status; /* Undocumented magic */ RCBA16(IOBPU) = IOBPU_MAGIC; /* Set ready bit */ status = RCBA16(IOBPS); status |= IOBPS_READY; RCBA16(IOBPS) = status; if (!iobp_poll()) return 0; /* Check for successful transaction */ status = RCBA16(IOBPS); if (status & IOBPS_TX_MASK) { printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address); return 0; } /* Read IOBP data */ return RCBA32(IOBPD); }
static void i82801ix_hide_functions(void) { int i; u32 reg32; /* FIXME: This works pretty good if the devicetree is consistent. But some functions have to be disabled in right order and/or have other constraints. */ if (i82801ix_function_disabled(PCI_DEVFN(0x19, 0))) RCBA32(RCBA_BUC) |= BUC_LAND; reg32 = RCBA32(RCBA_FD); struct { int devfn; u32 mask; } functions[] = { { PCI_DEVFN(0x1a, 0), FD_U4D }, /* UHCI #4 */ { PCI_DEVFN(0x1a, 1), FD_U5D }, /* UHCI #5 */ { PCI_DEVFN(0x1a, 2), FD_U6D }, /* UHCI #6 */ { PCI_DEVFN(0x1a, 7), FD_EHCI2D }, /* EHCI #2 */ { PCI_DEVFN(0x1b, 0), FD_HDAD }, /* HD Audio */ { PCI_DEVFN(0x1c, 0), FD_PE1D }, /* PCIe #1 */ { PCI_DEVFN(0x1c, 1), FD_PE2D }, /* PCIe #2 */ { PCI_DEVFN(0x1c, 2), FD_PE3D }, /* PCIe #3 */ { PCI_DEVFN(0x1c, 3), FD_PE4D }, /* PCIe #4 */ { PCI_DEVFN(0x1c, 4), FD_PE5D }, /* PCIe #5 */ { PCI_DEVFN(0x1c, 5), FD_PE6D }, /* PCIe #6 */ { PCI_DEVFN(0x1d, 0), FD_U1D }, /* UHCI #1 */ { PCI_DEVFN(0x1d, 1), FD_U2D }, /* UHCI #2 */ { PCI_DEVFN(0x1d, 2), FD_U3D }, /* UHCI #3 */ { PCI_DEVFN(0x1d, 7), FD_EHCI1D }, /* EHCI #1 */ { PCI_DEVFN(0x1f, 0), FD_LBD }, /* LPC */ { PCI_DEVFN(0x1f, 2), FD_SAD1 }, /* SATA #1 */ { PCI_DEVFN(0x1f, 3), FD_SD }, /* SMBus */ { PCI_DEVFN(0x1f, 5), FD_SAD2 }, /* SATA #2 */ { PCI_DEVFN(0x1f, 6), FD_TTD }, /* Thermal Throttle */ }; for (i = 0; i < ARRAY_SIZE(functions); ++i) { if (i82801ix_function_disabled(functions[i].devfn)) reg32 |= functions[i].mask; } RCBA32(RCBA_FD) = reg32; RCBA32(RCBA_FD) |= (1 << 0); /* BIOS must write this... */ RCBA32(RCBA_FDSW) |= (1 << 7); /* Lock function-disable? */ /* Hide PCIe root port PCI functions. RPFN is partially R/WO. */ reg32 = RCBA32(RCBA_RPFN); for (i = 0; i < 6; ++i) { if (i82801ix_function_disabled(PCI_DEVFN(0x1c, i))) reg32 |= (1 << ((i * 4) + 3)); } RCBA32(RCBA_RPFN) = reg32; /* Lock R/WO UHCI controller #6 remapping. */ RCBA32(RCBA_MAP) = RCBA32(RCBA_MAP); }
static void rcba_config(void) { u32 reg32; southbridge_configure_default_intmap(); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); reg32 |= PCH_DISABLE_ALWAYS; /* Disable PCI bridge so MRC does not probe this bus */ reg32 |= PCH_DISABLE_P2P; RCBA32(FD) = reg32; }
static void usb_ehci_init(struct device *dev) { u32 reg32; /* Disable Wake on Disconnect in RMH */ reg32 = RCBA32(0x35b0); reg32 |= 0x22; RCBA32(0x35b0) = reg32; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); /* For others, done in MRC. */ #if CONFIG(USE_NATIVE_RAMINIT) pci_write_config32(dev, 0x84, 0x930c8811); pci_write_config32(dev, 0x88, 0x24000d30); pci_write_config32(dev, 0xf4, 0x80408588); pci_write_config32(dev, 0xf4, 0x80808588); pci_write_config32(dev, 0xf4, 0x00808588); pci_write_config32(dev, 0xfc, 0x205b1708); #endif reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER; //reg32 |= PCI_COMMAND_SERR; pci_write_config32(dev, PCI_COMMAND, reg32); /* For others, done in MRC. */ #if CONFIG(USE_NATIVE_RAMINIT) struct resource *res; u8 access_cntl; access_cntl = pci_read_config8(dev, 0x80); /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { /* Number of ports and companion controllers. */ reg32 = read32((void *)(uintptr_t)(res->base + 4)); write32((void *)(uintptr_t)(res->base + 4), (reg32 & 0xfff00000) | 3); } /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); #endif printk(BIOS_DEBUG, "done.\n"); }
static void rcba_config(void) { u32 reg32; /* * GFX INTA -> PIRQA (MSI) * D28IP_P3IP WLAN INTA -> PIRQB * D29IP_E1P EHCI1 INTA -> PIRQD * D26IP_E2P EHCI2 INTA -> PIRQF * D31IP_SIP SATA INTA -> PIRQF (MSI) * D31IP_SMIP SMBUS INTB -> PIRQH * D31IP_TTIP THRT INTC -> PIRQA * D27IP_ZIP HDA INTA -> PIRQA (MSI) * * TRACKPAD -> PIRQE (Edge Triggered) * TOUCHSCREEN -> PIRQG (Edge Triggered) */ /* Device interrupt pin register (board specific) */ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); RCBA32(D30IP) = (NOINT << D30IP_PIP); RCBA32(D29IP) = (INTA << D29IP_E1P); RCBA32(D28IP) = (INTA << D28IP_P3IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); RCBA32(D25IP) = (NOINT << D25IP_LIP); RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); /* Device interrupt route registers */ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); reg32 |= PCH_DISABLE_ALWAYS; RCBA32(FD) = reg32; }
void mainboard_rcba_config(void) { u32 reg32; /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB * D28IP_P2IP ETH0 INTB -> PIRQF * D28IP_P3IP SDCARD INTC -> PIRQD * D29IP_E1P EHCI1 INTA -> PIRQD * D26IP_E2P EHCI2 INTA -> PIRQF * D31IP_SIP SATA INTA -> PIRQB (MSI) * D31IP_SMIP SMBUS INTB -> PIRQH * D31IP_TTIP THRT INTC -> PIRQA * D27IP_ZIP HDA INTA -> PIRQA (MSI) * * Trackpad interrupt is edge triggered and cannot be shared. * TRACKPAD -> PIRQG */ /* Device interrupt pin register (board specific) */ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); RCBA32(D29IP) = (INTA << D29IP_E1P); RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | (INTC << D28IP_P3IP); RCBA32(D27IP) = (INTA << D27IP_ZIP); RCBA32(D26IP) = (INTA << D26IP_E2P); RCBA32(D25IP) = (NOINT << D25IP_LIP); RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); /* Device interrupt route registers */ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); /* Enable IOAPIC (generic) */ RCBA16(OIC) = 0x0100; /* PCH BWG says to read back the IOAPIC enable register */ (void) RCBA16(OIC); /* Disable unused devices (board specific) */ reg32 = RCBA32(FD); /* Disable PCI bridge so MRC does not probe this bus */ reg32 |= PCH_DISABLE_P2P; RCBA32(FD) = reg32; }
static void mainboard_init(device_t dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; RCBA32(0x38c0) = 0x00000007; pc_keyboard_init(); /* Enable expresscard hotplug events. */ pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), 0xd8, pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), 0xd8) | (1 << 30)); pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), 0x42, 0x142); }
static void usb_ehci_init(struct device *dev) { u32 reg32; /* Disable Wake on Disconnect in RMH */ reg32 = RCBA32(0x35b0); reg32 |= 0x22; RCBA32(0x35b0) = reg32; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER; //reg32 |= PCI_COMMAND_SERR; pci_write_config32(dev, PCI_COMMAND, reg32); printk(BIOS_DEBUG, "done.\n"); }
static void bootblock_southbridge_init(void) { enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); }
static void enable_clock_gating(void) { u32 reg32; /* Enable Clock Gating for most devices */ reg32 = RCBA32(CG); reg32 |= (1 << 31); // LPC clock gating reg32 |= (1 << 30); // PATA clock gating // SATA clock gating reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24); reg32 |= (1 << 23); // AC97 clock gating reg32 |= (1 << 19); // USB EHCI clock gating reg32 |= (1 << 3) | (1 << 1); // DMI clock gating reg32 |= (1 << 2); // PCIe clock gating; reg32 &= ~(1 << 20); // No static clock gating for USB reg32 &= ~( (1 << 29) | (1 << 28) ); // Disable UHCI clock gating RCBA32(CG) = reg32; }
static void usb_ehci_init(struct device *dev) { u32 reg32; struct resource *res; u8 access_cntl; /* Disable Wake on Disconnect in RMH */ reg32 = RCBA32(0x35b0); reg32 |= 0x22; RCBA32(0x35b0) = reg32; printk(BIOS_DEBUG, "EHCI: Setting up controller.. "); pci_write_config32(dev, 0x84, 0x130c8911); pci_write_config32(dev, 0x88, 0xa0); pci_write_config32(dev, 0xf4, 0x80808588); pci_write_config32(dev, 0xf4, 0x00808588); pci_write_config32(dev, 0xf4, 0x00808588); pci_write_config32(dev, 0xfc, 0x301b1728); reg32 = pci_read_config32(dev, PCI_COMMAND); reg32 |= PCI_COMMAND_MASTER; //reg32 |= PCI_COMMAND_SERR; pci_write_config32(dev, PCI_COMMAND, reg32); access_cntl = pci_read_config8(dev, 0x80); /* Enable writes to protected registers. */ pci_write_config8(dev, 0x80, access_cntl | 1); res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { /* Number of ports and companion controllers. */ reg32 = read32((u32 *)(uintptr_t)(res->base + 4)); write32((u32 *)(uintptr_t)(res->base + 4), (reg32 & 0xfff00000) | 2); } /* Restore protection. */ pci_write_config8(dev, 0x80, access_cntl); printk(BIOS_DEBUG, "done.\n"); }
static void mainboard_init(device_t dev) { RCBA32(0x38c8) = 0x00002005; RCBA32(0x38c4) = 0x00802005; RCBA32(0x38c0) = 0x00000007; /* This sneaked in here, because X201 SuperIO chip isn't really connected to anything and hence we don't init it. */ pc_keyboard_init(); /* Enable expresscard hotplug events. */ pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), 0xd8, pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), 0xd8) | (1 << 30)); pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), 0x42, 0x142); }
static void set_spi_speed(void) { u32 fdod; u8 ssfc; /* Observe SPI Descriptor Component Section 0 */ RCBA32(0x38b0) = 0x1000; /* Extract the Write/Erase SPI Frequency from descriptor */ fdod = RCBA32(0x38b4); fdod >>= 24; fdod &= 7; /* Set Software Sequence frequency to match */ ssfc = RCBA8(0x3893); ssfc &= ~7; ssfc |= fdod; RCBA8(0x3893) = ssfc; }
/** * @brief Interrupt handler for SMI# * @param node * @param state_save */ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) { // FIXME: the necessary magic isn't available yet. the code // below is a partially adapted ICH7 version of the handler #if 0 u8 reg8; u16 pmctrl; u16 pm1_sts; u32 smi_sts, gpe0_sts, tco_sts; pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x48) & 0xfffc; printk(BIOS_SPEW, "SMI#: pmbase = 0x%04x\n", pmbase); /* We need to clear the SMI status registers, or we won't see what's * happening in the following calls. */ smi_sts = reset_smi_status(); dump_smi_status(smi_sts); if (smi_sts & (1 << 21)) { // MONITOR global_nvs_t *gnvs = (global_nvs_t *)0xc00; u32 reg32; reg32 = RCBA32(0x1e00); TRSR - Trap Status Register //#if 0 /* Comment in for some useful debug */ for (i=0; i<4; i++) { if (reg32 & (1 << i)) { printk(BIOS_DEBUG, " io trap #%d\n", i); } } //#endif RCBA32(0x1e00) = reg32; TRSR reg32 = RCBA32(0x1e10); if ((reg32 & 0xfffc) != 0x808) { printk(BIOS_DEBUG, " trapped io address = 0x%x\n", reg32 & 0xfffc); printk(BIOS_DEBUG, " AHBE = %x\n", (reg32 >> 16) & 0xf); printk(BIOS_DEBUG, " read/write: %s\n", (reg32 & (1 << 24)) ? "read" : "write"); }
static void i82801gx_fixups(struct device *dev) { /* This needs to happen after PCI enumeration */ RCBA32(0x1d40) |= 1; /* USB Transient Disconnect Detect: * Prevent a SE0 condition on the USB ports from being * interpreted by the UHCI controller as a disconnect */ pci_write_config8(dev, 0xad, 0x3); }
static void bootblock_southbridge_init(void) { #if CONFIG_COLLECT_TIMESTAMPS store_initial_timestamp(); #endif enable_spi_prefetch(); enable_port80_on_lpc(); set_spi_speed(); /* Enable upper 128bytes of CMOS */ RCBA32(RC) = (1 << 2); }
void intel_pch_finalize_smm(void) { /* Set SPI opcode menu */ RCBA16(0x3894) = SPI_OPPREFIX; RCBA16(0x3896) = SPI_OPTYPE; RCBA32(0x3898) = SPI_OPMENU_LOWER; RCBA32(0x389c) = SPI_OPMENU_UPPER; /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); #if CONFIG_SPI_FLASH_SMM /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif /* TCLOCKDN: TC Lockdown */ RCBA32_OR(0x0050, (1 << 31)); /* BIOS Interface Lockdown */ RCBA32_OR(0x3410, (1 << 0)); /* Function Disable SUS Well Lockdown */ RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); /* GEN_PMCON Lock */ pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); pcie_write_config32(PCI_DEV(0, 27, 0), 0x74, pcie_read_config32(PCI_DEV(0, 27, 0), 0x74)); /* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); }