static void _bme3200_interrupt(bde_ctrl_t *ctrl) { SSOC_WRITEL(0xffffffff, ctrl->ba + 0x54/sizeof(uint32)); /* PI_PT_ERROR0 */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x5c/sizeof(uint32)); /* PI_PT_ERROR1 */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x64/sizeof(uint32)); /* PI_PT_ERROR2 */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x6c/sizeof(uint32)); /* PI_PT_ERROR3 */ atomic_set(&_interrupt_has_taken_place, 1); #ifdef BDE_LINUX_NON_INTERRUPTIBLE wake_up(&_interrupt_wq); #else wake_up_interruptible(&_interrupt_wq); #endif }
static void _fe2kxt_interrupt(bde_ctrl_t *ctrl) { SSOC_WRITEL(0xffffffff, ctrl->ba + 0x2c/sizeof(uint32)); /* PC_INTERRUPT_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x38/sizeof(uint32)); /* PC_ERROR0_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x40/sizeof(uint32)); /* PC_ERROR1_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x50/sizeof(uint32)); /* PC_UNIT_MASK */ atomic_set(&_interrupt_has_taken_place, 1); #ifdef BDE_LINUX_NON_INTERRUPTIBLE wake_up(&_interrupt_wq); #else wake_up_interruptible(&_interrupt_wq); #endif }
static void _bme3200_interrupt(bde_ctrl_t *ctrl) { bde_inst_resource_t *res; res = &_bde_inst_resource[ctrl->inst]; SSOC_WRITEL(0xffffffff, ctrl->ba + 0x54/sizeof(uint32)); /* PI_PT_ERROR0 */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x5c/sizeof(uint32)); /* PI_PT_ERROR1 */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x64/sizeof(uint32)); /* PI_PT_ERROR2 */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x6c/sizeof(uint32)); /* PI_PT_ERROR3 */ atomic_set(&res->intr, 1); #ifdef BDE_LINUX_NON_INTERRUPTIBLE wake_up(&res->intr_wq); #else wake_up_interruptible(&res->intr_wq); #endif }
static void _fe2kxt_interrupt(bde_ctrl_t *ctrl) { bde_inst_resource_t *res; res = &_bde_inst_resource[ctrl->inst]; SSOC_WRITEL(0xffffffff, ctrl->ba + 0x2c/sizeof(uint32)); /* PC_INTERRUPT_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x38/sizeof(uint32)); /* PC_ERROR0_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x40/sizeof(uint32)); /* PC_ERROR1_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x50/sizeof(uint32)); /* PC_UNIT_MASK */ atomic_set(&res->intr, 1); #ifdef BDE_LINUX_NON_INTERRUPTIBLE wake_up(&res->intr_wq); #else wake_up_interruptible(&res->intr_wq); #endif }
static void _qe2k_interrupt(bde_ctrl_t *ctrl) { SSOC_WRITEL(0xffffffff, ctrl->ba + 0x20/sizeof(uint32)); atomic_set(&_interrupt_has_taken_place, 1); #ifdef BDE_LINUX_NON_INTERRUPTIBLE wake_up(&_interrupt_wq); #else wake_up_interruptible(&_interrupt_wq); #endif }
static void _qe2k_interrupt(bde_ctrl_t *ctrl) { bde_inst_resource_t *res; res = &_bde_inst_resource[ctrl->inst]; SSOC_WRITEL(0xffffffff, ctrl->ba + 0x20/sizeof(uint32)); atomic_set(&res->intr, 1); #ifdef BDE_LINUX_NON_INTERRUPTIBLE wake_up(&res->intr_wq); #else wake_up_interruptible(&res->intr_wq); #endif }
/* The actual interrupt handler of ethernet devices */ static void _ether_interrupt(bde_ctrl_t *ctrl) { #ifdef KEYSTONE /* * Since the two GMAC cores are sharing the same IRQ. * Add the checking to handle the interrupt events. */ if ((ctrl->devid == BCM53000_GMAC_ID)) { if ((readl(ctrl->ba + 0x020/4) & readl(ctrl->ba + 0x024/4)) == 0) { return; } } #endif SSOC_WRITEL(0, ctrl->ba + 0x024/4); atomic_set(&_ether_interrupt_has_taken_place, 1); #ifdef BDE_LINUX_NON_INTERRUPTIBLE wake_up(&_ether_interrupt_wq); #else wake_up_interruptible(&_ether_interrupt_wq); #endif }
static void _bm9600_interrupt(bde_ctrl_t *ctrl) { bde_inst_resource_t *res; res = &_bde_inst_resource[ctrl->inst]; SSOC_WRITEL(0xffffffff, ctrl->ba + 0x5c/sizeof(uint32)); /* PI_INTERRUPT_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0xc/sizeof(uint32)); /* PI_UNIT_INTERRUPT0_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x14/sizeof(uint32)); /* PI_UNIT_INTERRUPT1_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x1c/sizeof(uint32)); /* PI_UNIT_INTERRUPT2_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x24/sizeof(uint32)); /* PI_UNIT_INTERRUPT3_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x2c/sizeof(uint32)); /* PI_UNIT_INTERRUPT4_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x34/sizeof(uint32)); /* PI_UNIT_INTERRUPT5_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x3c/sizeof(uint32)); /* PI_UNIT_INTERRUPT6_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x44/sizeof(uint32)); /* PI_UNIT_INTERRUPT7_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x4c/sizeof(uint32)); /* PI_UNIT_INTERRUPT8_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x54/sizeof(uint32)); /* PI_UNIT_INTERRUPT9_MASK */ atomic_set(&res->intr, 1); #ifdef BDE_LINUX_NON_INTERRUPTIBLE wake_up(&res->intr_wq); #else wake_up_interruptible(&res->intr_wq); #endif }
static void _bm9600_interrupt(bde_ctrl_t *ctrl) { SSOC_WRITEL(0xffffffff, ctrl->ba + 0x5c/sizeof(uint32)); /* PI_INTERRUPT_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0xc/sizeof(uint32)); /* PI_UNIT_INTERRUPT0_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x14/sizeof(uint32)); /* PI_UNIT_INTERRUPT1_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x1c/sizeof(uint32)); /* PI_UNIT_INTERRUPT2_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x24/sizeof(uint32)); /* PI_UNIT_INTERRUPT3_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x2c/sizeof(uint32)); /* PI_UNIT_INTERRUPT4_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x34/sizeof(uint32)); /* PI_UNIT_INTERRUPT5_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x3c/sizeof(uint32)); /* PI_UNIT_INTERRUPT6_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x44/sizeof(uint32)); /* PI_UNIT_INTERRUPT7_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x4c/sizeof(uint32)); /* PI_UNIT_INTERRUPT8_MASK */ SSOC_WRITEL(0xffffffff, ctrl->ba + 0x54/sizeof(uint32)); /* PI_UNIT_INTERRUPT9_MASK */ atomic_set(&_interrupt_has_taken_place, 1); #ifdef BDE_LINUX_NON_INTERRUPTIBLE wake_up(&_interrupt_wq); #else wake_up_interruptible(&_interrupt_wq); #endif }