Beispiel #1
0
void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data)
{
	BUG_ON(!data);

	data->have_intensity_bit = true;

	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDHSYNC */
	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDDOTCK */
	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDDEN */
	at91_set_B_periph(AT91_PIN_PB9, 0);	/* LCDCC */
	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD2 */
	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD3 */
	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD4 */
	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD5 */
	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD6 */
	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD7 */
	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD10 */
	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD13 */
	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD18 */
	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD19 */
	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDD20 */
	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD21 */
	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDD22 */
	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDD23 */

	add_generic_device("atmel_lcdfb", DEVICE_ID_SINGLE, NULL, AT91SAM9263_LCDC_BASE, SZ_4K,
			   IORESOURCE_MEM, data);
}
void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
{
	if (!data)
		return;

	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDHSYNC */
	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDDOTCK */
	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDDEN */
	at91_set_B_periph(AT91_PIN_PB9, 0);	/* LCDCC */
	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD2 */
	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD3 */
	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD4 */
	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD5 */
	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD6 */
	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD7 */
	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD10 */
	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD13 */
	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD18 */
	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD19 */
	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDD20 */
	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD21 */
	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDD22 */
	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDD23 */

	lcdc_data = *data;
	platform_device_register(&at91_lcdc_device);
}
Beispiel #3
0
static inline void configure_dbgu_pins(void)
{
	at91_set_A_periph(AT91_PIN_PC30, 0);		/* DRXD */
	at91_set_A_periph(AT91_PIN_PC31, 1);		/* DTXD */
}
static inline void configure_usart2_pins(void)
{
	at91_set_A_periph(AT91_PIN_PA22, 0);		/* RXD2 */
	at91_set_A_periph(AT91_PIN_PA23, 1);		/* TXD2 */
}
void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
{
	if (!data) {
		return;
	}

#if defined(CONFIG_FB_ATMEL_STN)
	at91_set_A_periph(AT91_PIN_PB0, 0);     /* LCDVSYNC */
	at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
	at91_set_A_periph(AT91_PIN_PB2, 0);     /* LCDDOTCK */
	at91_set_A_periph(AT91_PIN_PB3, 0);     /* LCDDEN */
	at91_set_A_periph(AT91_PIN_PB4, 0);     /* LCDCC */
	at91_set_A_periph(AT91_PIN_PB5, 0);     /* LCDD0 */
	at91_set_A_periph(AT91_PIN_PB6, 0);     /* LCDD1 */
	at91_set_A_periph(AT91_PIN_PB7, 0);     /* LCDD2 */
	at91_set_A_periph(AT91_PIN_PB8, 0);     /* LCDD3 */
#else
	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
	at91_set_A_periph(AT91_PIN_PB4, 0);	/* LCDCC */
	at91_set_A_periph(AT91_PIN_PB7, 0);	/* LCDD2 */
	at91_set_A_periph(AT91_PIN_PB8, 0);	/* LCDD3 */
	at91_set_A_periph(AT91_PIN_PB9, 0);	/* LCDD4 */
	at91_set_A_periph(AT91_PIN_PB10, 0);	/* LCDD5 */
	at91_set_A_periph(AT91_PIN_PB11, 0);	/* LCDD6 */
	at91_set_A_periph(AT91_PIN_PB12, 0);	/* LCDD7 */
	at91_set_A_periph(AT91_PIN_PB15, 0);	/* LCDD10 */
	at91_set_A_periph(AT91_PIN_PB16, 0);	/* LCDD11 */
	at91_set_A_periph(AT91_PIN_PB17, 0);	/* LCDD12 */
	at91_set_A_periph(AT91_PIN_PB18, 0);	/* LCDD13 */
	at91_set_A_periph(AT91_PIN_PB19, 0);	/* LCDD14 */
	at91_set_A_periph(AT91_PIN_PB20, 0);	/* LCDD15 */
	at91_set_B_periph(AT91_PIN_PB23, 0);	/* LCDD18 */
	at91_set_B_periph(AT91_PIN_PB24, 0);	/* LCDD19 */
	at91_set_B_periph(AT91_PIN_PB25, 0);	/* LCDD20 */
	at91_set_B_periph(AT91_PIN_PB26, 0);	/* LCDD21 */
	at91_set_B_periph(AT91_PIN_PB27, 0);	/* LCDD22 */
	at91_set_B_periph(AT91_PIN_PB28, 0);	/* LCDD23 */
#endif

	if (ARRAY_SIZE(lcdc_resources) > 2) {
		void __iomem *fb;
		struct resource *fb_res = &lcdc_resources[2];
		size_t fb_len = fb_res->end - fb_res->start + 1;

		fb = ioremap(fb_res->start, fb_len);
		if (fb) {
			memset(fb, 0, fb_len);
			iounmap(fb);
		}
	}

	lcdc_data = *data;
	platform_device_register(&at91_lcdc_device);
}
Beispiel #6
0
void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
{
	unsigned int i;
	unsigned int slot_count = 0;

	if (!data)
		return;

	for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {

		if (!data->slot[i].bus_width)
			continue;

		/* input/irq */
		if (gpio_is_valid(data->slot[i].detect_pin)) {
			at91_set_gpio_input(data->slot[i].detect_pin,
					1);
			at91_set_deglitch(data->slot[i].detect_pin,
					1);
		}
		if (gpio_is_valid(data->slot[i].wp_pin))
			at91_set_gpio_input(data->slot[i].wp_pin, 1);

		if (mmc_id == 0) {				/* MCI0 */
			switch (i) {
			case 0:					/* slot A */
				/* CMD */
				at91_set_A_periph(AT91_PIN_PA1, 1);
				/* DAT0, maybe DAT1..DAT3 */
				at91_set_A_periph(AT91_PIN_PA0, 1);
				if (data->slot[i].bus_width == 4) {
					at91_set_A_periph(AT91_PIN_PA3, 1);
					at91_set_A_periph(AT91_PIN_PA4, 1);
					at91_set_A_periph(AT91_PIN_PA5, 1);
				}
				slot_count++;
				break;
			case 1:					/* slot B */
				/* CMD */
				at91_set_A_periph(AT91_PIN_PA16, 1);
				/* DAT0, maybe DAT1..DAT3 */
				at91_set_A_periph(AT91_PIN_PA17, 1);
				if (data->slot[i].bus_width == 4) {
					at91_set_A_periph(AT91_PIN_PA18, 1);
					at91_set_A_periph(AT91_PIN_PA19, 1);
					at91_set_A_periph(AT91_PIN_PA20, 1);
				}
				slot_count++;
				break;
			default:
				printk(KERN_ERR
				       "AT91: SD/MMC slot %d not available\n", i);
				break;
			}
			if (slot_count) {
				/* CLK */
				at91_set_A_periph(AT91_PIN_PA12, 0);

				mmc0_data = *data;
				platform_device_register(&at91sam9263_mmc0_device);
			}
		} else if (mmc_id == 1) {			/* MCI1 */
			switch (i) {
			case 0:					/* slot A */
				/* CMD */
				at91_set_A_periph(AT91_PIN_PA7, 1);
				/* DAT0, maybe DAT1..DAT3 */
				at91_set_A_periph(AT91_PIN_PA8, 1);
				if (data->slot[i].bus_width == 4) {
					at91_set_A_periph(AT91_PIN_PA9, 1);
					at91_set_A_periph(AT91_PIN_PA10, 1);
					at91_set_A_periph(AT91_PIN_PA11, 1);
				}
				slot_count++;
				break;
			case 1:					/* slot B */
				/* CMD */
				at91_set_A_periph(AT91_PIN_PA21, 1);
				/* DAT0, maybe DAT1..DAT3 */
				at91_set_A_periph(AT91_PIN_PA22, 1);
				if (data->slot[i].bus_width == 4) {
					at91_set_A_periph(AT91_PIN_PA23, 1);
					at91_set_A_periph(AT91_PIN_PA24, 1);
					at91_set_A_periph(AT91_PIN_PA25, 1);
				}
				slot_count++;
				break;
			default:
				printk(KERN_ERR
				       "AT91: SD/MMC slot %d not available\n", i);
				break;
			}
			if (slot_count) {
				/* CLK */
				at91_set_A_periph(AT91_PIN_PA6, 0);

				mmc1_data = *data;
				platform_device_register(&at91sam9263_mmc1_device);
			}
		}
	}
}
Beispiel #7
0
void lcd_disable(void)
{
	at91_set_A_periph(AT91_PIN_PE6, 0);	/* power down */
}
Beispiel #8
0
/* Consider only one slot : slot 0 */
void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
{

	if (!data)
		return;

	/* Must have at least one usable slot */
	if (!data->slot[0].bus_width)
		return;

#if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
	{
	struct at_dma_slave	*atslave;
	struct mci_dma_data	*alt_atslave;

	alt_atslave = kzalloc(sizeof(struct mci_dma_data), GFP_KERNEL);
	atslave = &alt_atslave->sdata;

	/* DMA slave channel configuration */
	atslave->dma_dev = &at_hdmac_device.dev;
	atslave->cfg = ATC_FIFOCFG_HALFFIFO
			| ATC_SRC_H2SEL_HW | ATC_DST_H2SEL_HW;
	if (mmc_id == 0)	/* MCI0 */
		atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI0)
			      | ATC_DST_PER(AT_DMA_ID_MCI0);

	else			/* MCI1 */
		atslave->cfg |= ATC_SRC_PER(AT_DMA_ID_MCI1)
			      | ATC_DST_PER(AT_DMA_ID_MCI1);

	data->dma_slave = alt_atslave;
	}
#endif


	/* input/irq */
	if (gpio_is_valid(data->slot[0].detect_pin)) {
		at91_set_gpio_input(data->slot[0].detect_pin, 1);
		at91_set_deglitch(data->slot[0].detect_pin, 1);
	}
	if (gpio_is_valid(data->slot[0].wp_pin))
		at91_set_gpio_input(data->slot[0].wp_pin, 1);

	if (mmc_id == 0) {		/* MCI0 */

		/* CLK */
		at91_set_A_periph(AT91_PIN_PA0, 0);

		/* CMD */
		at91_set_A_periph(AT91_PIN_PA1, 1);

		/* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
		at91_set_A_periph(AT91_PIN_PA2, 1);
		if (data->slot[0].bus_width == 4) {
			at91_set_A_periph(AT91_PIN_PA3, 1);
			at91_set_A_periph(AT91_PIN_PA4, 1);
			at91_set_A_periph(AT91_PIN_PA5, 1);
			if (data->slot[0].bus_width == 8) {
				at91_set_A_periph(AT91_PIN_PA6, 1);
				at91_set_A_periph(AT91_PIN_PA7, 1);
				at91_set_A_periph(AT91_PIN_PA8, 1);
				at91_set_A_periph(AT91_PIN_PA9, 1);
			}
		}

		mmc0_data = *data;
		platform_device_register(&at91sam9g45_mmc0_device);

	} else {			/* MCI1 */

		/* CLK */
		at91_set_A_periph(AT91_PIN_PA31, 0);

		/* CMD */
		at91_set_A_periph(AT91_PIN_PA22, 1);

		/* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
		at91_set_A_periph(AT91_PIN_PA23, 1);
		if (data->slot[0].bus_width == 4) {
			at91_set_A_periph(AT91_PIN_PA24, 1);
			at91_set_A_periph(AT91_PIN_PA25, 1);
			at91_set_A_periph(AT91_PIN_PA26, 1);
			if (data->slot[0].bus_width == 8) {
				at91_set_A_periph(AT91_PIN_PA27, 1);
				at91_set_A_periph(AT91_PIN_PA28, 1);
				at91_set_A_periph(AT91_PIN_PA29, 1);
				at91_set_A_periph(AT91_PIN_PA30, 1);
			}
		}

		mmc1_data = *data;
		platform_device_register(&at91sam9g45_mmc1_device);

	}
}
Beispiel #9
0
void __init at91_add_device_isi(struct isi_platform_data *data,
		bool use_pck_as_mck)
{
	struct clk *pck;
	struct clk *parent;

	if (!data)
		return;
	isi_data = *data;

	at91_set_A_periph(AT91_PIN_PB20, 0);	/* ISI_D0 */
	at91_set_A_periph(AT91_PIN_PB21, 0);	/* ISI_D1 */
	at91_set_A_periph(AT91_PIN_PB22, 0);	/* ISI_D2 */
	at91_set_A_periph(AT91_PIN_PB23, 0);	/* ISI_D3 */
	at91_set_A_periph(AT91_PIN_PB24, 0);	/* ISI_D4 */
	at91_set_A_periph(AT91_PIN_PB25, 0);	/* ISI_D5 */
	at91_set_A_periph(AT91_PIN_PB26, 0);	/* ISI_D6 */
	at91_set_A_periph(AT91_PIN_PB27, 0);	/* ISI_D7 */
	at91_set_A_periph(AT91_PIN_PB28, 0);	/* ISI_PCK */
	at91_set_A_periph(AT91_PIN_PB30, 0);	/* ISI_HSYNC */
	at91_set_A_periph(AT91_PIN_PB29, 0);	/* ISI_VSYNC */
	at91_set_B_periph(AT91_PIN_PB8, 0);	/* ISI_PD8 */
	at91_set_B_periph(AT91_PIN_PB9, 0);	/* ISI_PD9 */
	at91_set_B_periph(AT91_PIN_PB10, 0);	/* ISI_PD10 */
	at91_set_B_periph(AT91_PIN_PB11, 0);	/* ISI_PD11 */

	platform_device_register(&at91sam9g45_isi_device);

	if (use_pck_as_mck) {
		at91_set_B_periph(AT91_PIN_PB31, 0);	/* ISI_MCK (PCK1) */

		pck = clk_get(NULL, "pck1");
		parent = clk_get(NULL, "plla");

		BUG_ON(IS_ERR(pck) || IS_ERR(parent));

		if (clk_set_parent(pck, parent)) {
			pr_err("Failed to set PCK's parent\n");
		} else {
			/* Register PCK as ISI_MCK */
			isi_mck_lookups[0].clk = pck;
			clkdev_add_table(isi_mck_lookups,
					ARRAY_SIZE(isi_mck_lookups));
		}

		clk_put(pck);
		clk_put(parent);
	}
}
void at91_serial3_hw_init(void)
{
	at91_set_A_periph(AT91_PIN_PB12, 0);	/* DRXD */
	at91_set_A_periph(AT91_PIN_PB13, 1);	/* DTXD */
	at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);;
}
void __init at91_add_device_isi(void)
{
	at91_set_A_periph(AT91_PIN_PE0, 0);	/* ISI_D0 */
	at91_set_A_periph(AT91_PIN_PE1, 0);	/* ISI_D1 */
	at91_set_A_periph(AT91_PIN_PE2, 0);	/* ISI_D2 */
	at91_set_A_periph(AT91_PIN_PE3, 0);	/* ISI_D3 */
	at91_set_A_periph(AT91_PIN_PE4, 0);	/* ISI_D4 */
	at91_set_A_periph(AT91_PIN_PE5, 0);	/* ISI_D5 */
	at91_set_A_periph(AT91_PIN_PE6, 0);	/* ISI_D6 */
	at91_set_A_periph(AT91_PIN_PE7, 0);	/* ISI_D7 */
	at91_set_A_periph(AT91_PIN_PE8, 0);	/* ISI_PCK */
	at91_set_A_periph(AT91_PIN_PE9, 0);	/* ISI_HSYNC */
	at91_set_A_periph(AT91_PIN_PE10, 0);	/* ISI_VSYNC */
	at91_set_B_periph(AT91_PIN_PE11, 0);	/* ISI_MCK (PCK3) */
	at91_set_B_periph(AT91_PIN_PE12, 0);	/* ISI_PD8 */
	at91_set_B_periph(AT91_PIN_PE13, 0);	/* ISI_PD9 */
	at91_set_B_periph(AT91_PIN_PE14, 0);	/* ISI_PD10 */
	at91_set_B_periph(AT91_PIN_PE15, 0);	/* ISI_PD11 */
}
void at91_serial2_hw_init(void)
{
	at91_set_A_periph(AT91_PIN_PD6, 1);		/* TXD2 */
	at91_set_A_periph(AT91_PIN_PD7, 0);		/* RXD2 */
	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US2);
}
void at91_serial1_hw_init(void)
{
	at91_set_A_periph(AT91_PIN_PB4, 1);		/* TXD1 */
	at91_set_A_periph(AT91_PIN_PB5, 0);		/* RXD1 */
	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US1);
}
void at91_serial0_hw_init(void)
{
	at91_set_A_periph(AT91_PIN_PB19, 1);	/* TXD0 */
	at91_set_A_periph(AT91_PIN_PB18, 0);	/* RXD0 */
	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9G45_ID_US0);
}
Beispiel #15
0
/* Consider only one slot : slot 0 */
void __init at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
{
	resource_size_t start = ~0;

	if (!data)
		return;

	/* Must have at least one usable slot */
	if (!data->bus_width)
		return;

	/* input/irq */
	if (gpio_is_valid(data->detect_pin)) {
		at91_set_gpio_input(data->detect_pin, 1);
		at91_set_deglitch(data->detect_pin, 1);
	}
	if (gpio_is_valid(data->wp_pin))
		at91_set_gpio_input(data->wp_pin, 1);

	switch (mmc_id) {
	case 0:		/* MCI0 */
		start = SAMA5D3_BASE_HSMCI0;

		/* CLK */
		at91_set_A_periph(AT91_PIN_PD9, 0);

		/* CMD */
		at91_set_A_periph(AT91_PIN_PD0, 1);

		/* DAT0, maybe DAT1..DAT3 */
		at91_set_A_periph(AT91_PIN_PD1, 1);
		switch (data->bus_width) {
		case 8:
			at91_set_A_periph(AT91_PIN_PD5, 1);
			at91_set_A_periph(AT91_PIN_PD6, 1);
			at91_set_A_periph(AT91_PIN_PD7, 1);
			at91_set_A_periph(AT91_PIN_PD8, 1);
		case 4:
			at91_set_A_periph(AT91_PIN_PD2, 1);
			at91_set_A_periph(AT91_PIN_PD3, 1);
			at91_set_A_periph(AT91_PIN_PD4, 1);
		};

		break;
	case 1:			/* MCI1 */
		start = SAMA5D3_BASE_HSMCI1;

		/* CLK */
		at91_set_A_periph(AT91_PIN_PB24, 0);

		/* CMD */
		at91_set_A_periph(AT91_PIN_PB19, 1);

		/* DAT0, maybe DAT1..DAT3 */
		at91_set_A_periph(AT91_PIN_PB20, 1);
		if (data->bus_width == 4) {
			at91_set_A_periph(AT91_PIN_PB21, 1);
			at91_set_A_periph(AT91_PIN_PB22, 1);
			at91_set_A_periph(AT91_PIN_PB23, 1);
		}
		break;
	case 2:			/* MCI2 */
		start = SAMA5D3_BASE_HSMCI2;

		/* CLK */
		at91_set_A_periph(AT91_PIN_PC15, 0);

		/* CMD */
		at91_set_A_periph(AT91_PIN_PC10, 1);

		/* DAT0, maybe DAT1..DAT3 */
		at91_set_A_periph(AT91_PIN_PC11, 1);
		if (data->bus_width == 4) {
			at91_set_A_periph(AT91_PIN_PC12, 1);
			at91_set_A_periph(AT91_PIN_PC13, 1);
			at91_set_A_periph(AT91_PIN_PC14, 1);
		}
	}

	add_generic_device("atmel_mci", mmc_id, NULL, start, SZ_16K,
			   IORESOURCE_MEM, data);
}
Beispiel #16
0
void __init at91_add_device_lcdc(struct atmel_lcdfb_pdata *data)
{
	if (!data)
		return;

	if (cpu_is_at91sam9g45es())
		at91_lcdc_device.name = "at91sam9g45es-lcdfb";
	else
		at91_lcdc_device.name = "at91sam9g45-lcdfb";

	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */

	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
	at91_set_A_periph(AT91_PIN_PE6, 0);	/* LCDDEN */
	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
	at91_set_A_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
	at91_set_A_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */

	lcdc_data = *data;
	platform_device_register(&at91_lcdc_device);
}
Beispiel #17
0
void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data)
{
	BUG_ON(!data);

	if (cpu_is_sama5d35()) {
		pr_warn("AT91: no lcd on sama5d35\n");
		return;
	}

	at91_set_A_periph(AT91_PIN_PA24, 0);	/* LCDPWM */
	at91_set_A_periph(AT91_PIN_PA25, 0);	/* LCDDISP */
	at91_set_A_periph(AT91_PIN_PA26, 0);	/* LCDVSYNC */
	at91_set_A_periph(AT91_PIN_PA27, 0);	/* LCDHSYNC */
	at91_set_A_periph(AT91_PIN_PA28, 0);	/* LCDDOTCK */
	at91_set_A_periph(AT91_PIN_PA29, 0);	/* LCDDEN */

	at91_set_A_periph(AT91_PIN_PA0, 0);	/* LCDD0 */
	at91_set_A_periph(AT91_PIN_PA1, 0);	/* LCDD1 */
	at91_set_A_periph(AT91_PIN_PA2, 0);	/* LCDD2 */
	at91_set_A_periph(AT91_PIN_PA3, 0);	/* LCDD3 */
	at91_set_A_periph(AT91_PIN_PA4, 0);	/* LCDD4 */
	at91_set_A_periph(AT91_PIN_PA5, 0);	/* LCDD5 */
	at91_set_A_periph(AT91_PIN_PA6, 0);	/* LCDD6 */
	at91_set_A_periph(AT91_PIN_PA7, 0);	/* LCDD7 */
	at91_set_A_periph(AT91_PIN_PA8, 0);	/* LCDD8 */
	at91_set_A_periph(AT91_PIN_PA9, 0);	/* LCDD9 */
	at91_set_A_periph(AT91_PIN_PA10, 0);	/* LCDD10 */
	at91_set_A_periph(AT91_PIN_PA11, 0);	/* LCDD11 */
	at91_set_A_periph(AT91_PIN_PA12, 0);	/* LCDD12 */
	at91_set_A_periph(AT91_PIN_PA13, 0);	/* LCDD13 */
	at91_set_A_periph(AT91_PIN_PA14, 0);	/* LCDD14 */
	at91_set_A_periph(AT91_PIN_PA15, 0);	/* LCDD15 */
	at91_set_C_periph(AT91_PIN_PC14, 0);	/* LCDD16 */
	at91_set_C_periph(AT91_PIN_PC13, 0);	/* LCDD17 */
	at91_set_C_periph(AT91_PIN_PC12, 0);	/* LCDD18 */
	at91_set_C_periph(AT91_PIN_PC11, 0);	/* LCDD19 */
	at91_set_C_periph(AT91_PIN_PC10, 0);	/* LCDD20 */
	at91_set_C_periph(AT91_PIN_PC15, 0);	/* LCDD21 */
	at91_set_C_periph(AT91_PIN_PE27, 0);	/* LCDD22 */
	at91_set_C_periph(AT91_PIN_PE28, 0);	/* LCDD23 */

	add_generic_device("atmel_hlcdfb", DEVICE_ID_SINGLE, NULL, SAMA5D3_BASE_LCDC, SZ_4K,
			   IORESOURCE_MEM, data);
}
void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
{
	if (!data)
		return;

	if (cpu_is_at91cap9_revB())
		irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);

	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDHSYNC */
	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDDOTCK */
	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDDEN */
	at91_set_B_periph(AT91_PIN_PB9, 0);	/* LCDCC */
	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD2 */
	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD3 */
	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD4 */
	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD5 */
	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD6 */
	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD7 */
	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD10 */
	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
	at91_set_A_periph(AT91_PIN_PC17, 0);	/* LCDD13 */
	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD18 */
	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD19 */
	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDD20 */
	at91_set_A_periph(AT91_PIN_PC25, 0);	/* LCDD21 */
	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDD22 */
	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDD23 */

	lcdc_data = *data;
	platform_device_register(&at91_lcdc_device);
}
Beispiel #19
0
void lcd_enable(void)
{
	at91_set_A_periph(AT91_PIN_PE6, 1);	/* power up */
}
/* Consider only one slot : slot 0 */
void at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data)
{
	resource_size_t start;

	if (!data)
		return;

	/* need bus_width */
	if (!data->bus_width)
		return;

	/* input/irq */
	if (gpio_is_valid(data->detect_pin)) {
		at91_set_gpio_input(data->detect_pin, 1);
		at91_set_deglitch(data->detect_pin, 1);
	}

	if (gpio_is_valid(data->wp_pin))
		at91_set_gpio_input(data->wp_pin, 1);

	if (mmc_id == 0) {		/* MCI0 */
		start = AT91SAM9G45_BASE_MCI0;
		/* CLK */
		at91_set_A_periph(AT91_PIN_PA0, 0);

		/* CMD */
		at91_set_A_periph(AT91_PIN_PA1, 1);

		/* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
		at91_set_A_periph(AT91_PIN_PA2, 1);
		if (data->bus_width >= 4) {
			at91_set_A_periph(AT91_PIN_PA3, 1);
			at91_set_A_periph(AT91_PIN_PA4, 1);
			at91_set_A_periph(AT91_PIN_PA5, 1);
			if (data->bus_width == 8) {
				at91_set_A_periph(AT91_PIN_PA6, 1);
				at91_set_A_periph(AT91_PIN_PA7, 1);
				at91_set_A_periph(AT91_PIN_PA8, 1);
				at91_set_A_periph(AT91_PIN_PA9, 1);
			}
		}
	} else {			/* MCI1 */
		data->slot_b = 1;
		start = AT91SAM9G45_BASE_MCI1;
		/* CLK */
		at91_set_A_periph(AT91_PIN_PA31, 0);

		/* CMD */
		at91_set_A_periph(AT91_PIN_PA22, 1);

		/* DAT0, maybe DAT1..DAT3 and maybe DAT4..DAT7 */
		at91_set_A_periph(AT91_PIN_PA23, 1);
		if (data->bus_width >= 4) {
			at91_set_A_periph(AT91_PIN_PA24, 1);
			at91_set_A_periph(AT91_PIN_PA25, 1);
			at91_set_A_periph(AT91_PIN_PA26, 1);
			if (data->bus_width == 8) {
				at91_set_A_periph(AT91_PIN_PA27, 1);
				at91_set_A_periph(AT91_PIN_PA28, 1);
				at91_set_A_periph(AT91_PIN_PA29, 1);
				at91_set_A_periph(AT91_PIN_PA30, 1);
			}
		}
	}

	add_generic_device("atmel_mci", mmc_id, NULL, start, 4096,
			   IORESOURCE_MEM, data);
}
Beispiel #21
0
static void picosam9g45_lcd_hw_init(void)
{
	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;

	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */
	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */

	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
	at91_set_B_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
	at91_set_B_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */

	writel(1 << ATMEL_ID_LCDC, &pmc->pcer);

	gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
}
void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data)
{
	BUG_ON(!data);

	at91_set_A_periph(AT91_PIN_PE0, 0);	/* LCDDPWR */

	at91_set_A_periph(AT91_PIN_PE2, 0);	/* LCDCC */
	at91_set_A_periph(AT91_PIN_PE3, 0);	/* LCDVSYNC */
	at91_set_A_periph(AT91_PIN_PE4, 0);	/* LCDHSYNC */
	at91_set_A_periph(AT91_PIN_PE5, 0);	/* LCDDOTCK */
	at91_set_A_periph(AT91_PIN_PE6, 0);	/* LCDDEN */
	at91_set_A_periph(AT91_PIN_PE7, 0);	/* LCDD0 */
	at91_set_A_periph(AT91_PIN_PE8, 0);	/* LCDD1 */
	at91_set_A_periph(AT91_PIN_PE9, 0);	/* LCDD2 */
	at91_set_A_periph(AT91_PIN_PE10, 0);	/* LCDD3 */
	at91_set_A_periph(AT91_PIN_PE11, 0);	/* LCDD4 */
	at91_set_A_periph(AT91_PIN_PE12, 0);	/* LCDD5 */
	at91_set_A_periph(AT91_PIN_PE13, 0);	/* LCDD6 */
	at91_set_A_periph(AT91_PIN_PE14, 0);	/* LCDD7 */
	at91_set_A_periph(AT91_PIN_PE15, 0);	/* LCDD8 */
	at91_set_A_periph(AT91_PIN_PE16, 0);	/* LCDD9 */
	at91_set_A_periph(AT91_PIN_PE17, 0);	/* LCDD10 */
	at91_set_A_periph(AT91_PIN_PE18, 0);	/* LCDD11 */
	at91_set_A_periph(AT91_PIN_PE19, 0);	/* LCDD12 */
	at91_set_A_periph(AT91_PIN_PE20, 0);	/* LCDD13 */
	at91_set_A_periph(AT91_PIN_PE21, 0);	/* LCDD14 */
	at91_set_A_periph(AT91_PIN_PE22, 0);	/* LCDD15 */
	at91_set_A_periph(AT91_PIN_PE23, 0);	/* LCDD16 */
	at91_set_A_periph(AT91_PIN_PE24, 0);	/* LCDD17 */
	at91_set_A_periph(AT91_PIN_PE25, 0);	/* LCDD18 */
	at91_set_A_periph(AT91_PIN_PE26, 0);	/* LCDD19 */
	at91_set_A_periph(AT91_PIN_PE27, 0);	/* LCDD20 */
	at91_set_A_periph(AT91_PIN_PE28, 0);	/* LCDD21 */
	at91_set_A_periph(AT91_PIN_PE29, 0);	/* LCDD22 */
	at91_set_A_periph(AT91_PIN_PE30, 0);	/* LCDD23 */

	add_generic_device("atmel_lcdfb", DEVICE_ID_SINGLE, NULL, AT91SAM9G45_LCDC_BASE, SZ_4K,
			   IORESOURCE_MEM, data);
}
Beispiel #23
0
static inline void configure_usart5_pins(void)
{
	at91_set_A_periph(AT91_PIN_PB12, 1);		/* TXD5 */
	at91_set_A_periph(AT91_PIN_PB13, 0);		/* RXD5 */
}
void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
{
	if (!data) {
		return;
	}

	at91_set_A_periph(AT91_PIN_PB1, 0);	/* LCDHSYNC */
	at91_set_A_periph(AT91_PIN_PB2, 0);	/* LCDDOTCK */
	at91_set_A_periph(AT91_PIN_PB3, 0);	/* LCDDEN */
	at91_set_A_periph(AT91_PIN_PB4, 0);	/* LCDCC */
	at91_set_A_periph(AT91_PIN_PB7, 0);	/* LCDD2 */
	at91_set_A_periph(AT91_PIN_PB8, 0);	/* LCDD3 */
	at91_set_A_periph(AT91_PIN_PB9, 0);	/* LCDD4 */
	at91_set_A_periph(AT91_PIN_PB10, 0);	/* LCDD5 */
	at91_set_A_periph(AT91_PIN_PB11, 0);	/* LCDD6 */
	at91_set_A_periph(AT91_PIN_PB12, 0);	/* LCDD7 */
	at91_set_A_periph(AT91_PIN_PB15, 0);	/* LCDD10 */
	at91_set_A_periph(AT91_PIN_PB16, 0);	/* LCDD11 */
	at91_set_A_periph(AT91_PIN_PB17, 0);	/* LCDD12 */
	at91_set_A_periph(AT91_PIN_PB18, 0);	/* LCDD13 */
	at91_set_A_periph(AT91_PIN_PB19, 0);	/* LCDD14 */
	at91_set_A_periph(AT91_PIN_PB20, 0);	/* LCDD15 */
	at91_set_B_periph(AT91_PIN_PB23, 0);	/* LCDD18 */
	at91_set_B_periph(AT91_PIN_PB24, 0);	/* LCDD19 */
	at91_set_B_periph(AT91_PIN_PB25, 0);	/* LCDD20 */
	at91_set_B_periph(AT91_PIN_PB26, 0);	/* LCDD21 */
	at91_set_B_periph(AT91_PIN_PB27, 0);	/* LCDD22 */
	at91_set_B_periph(AT91_PIN_PB28, 0);	/* LCDD23 */

	lcdc_data = *data;
	platform_device_register(&at91_lcdc_device);
}
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
{
	if (!data)
		return;

	/* input/irq */
	if (gpio_is_valid(data->det_pin)) {
		at91_set_gpio_input(data->det_pin, 1);
		at91_set_deglitch(data->det_pin, 1);
	}
	if (gpio_is_valid(data->wp_pin))
		at91_set_gpio_input(data->wp_pin, 1);
	if (gpio_is_valid(data->vcc_pin))
		at91_set_gpio_output(data->vcc_pin, 0);

	if (mmc_id == 0) {		/* MCI0 */
		/* CLK */
		at91_set_A_periph(AT91_PIN_PA12, 0);

		if (data->slot_b) {
			/* CMD */
			at91_set_A_periph(AT91_PIN_PA16, 1);

			/* DAT0, maybe DAT1..DAT3 */
			at91_set_A_periph(AT91_PIN_PA17, 1);
			if (data->wire4) {
				at91_set_A_periph(AT91_PIN_PA18, 1);
				at91_set_A_periph(AT91_PIN_PA19, 1);
				at91_set_A_periph(AT91_PIN_PA20, 1);
			}
		} else {
			/* CMD */
			at91_set_A_periph(AT91_PIN_PA1, 1);

			/* DAT0, maybe DAT1..DAT3 */
			at91_set_A_periph(AT91_PIN_PA0, 1);
			if (data->wire4) {
				at91_set_A_periph(AT91_PIN_PA3, 1);
				at91_set_A_periph(AT91_PIN_PA4, 1);
				at91_set_A_periph(AT91_PIN_PA5, 1);
			}
		}

		mmc0_data = *data;
		platform_device_register(&at91sam9263_mmc0_device);
	} else {			/* MCI1 */
		/* CLK */
		at91_set_A_periph(AT91_PIN_PA6, 0);

		if (data->slot_b) {
			/* CMD */
			at91_set_A_periph(AT91_PIN_PA21, 1);

			/* DAT0, maybe DAT1..DAT3 */
			at91_set_A_periph(AT91_PIN_PA22, 1);
			if (data->wire4) {
				at91_set_A_periph(AT91_PIN_PA23, 1);
				at91_set_A_periph(AT91_PIN_PA24, 1);
				at91_set_A_periph(AT91_PIN_PA25, 1);
			}
		} else {
			/* CMD */
			at91_set_A_periph(AT91_PIN_PA7, 1);

			/* DAT0, maybe DAT1..DAT3 */
			at91_set_A_periph(AT91_PIN_PA8, 1);
			if (data->wire4) {
				at91_set_A_periph(AT91_PIN_PA9, 1);
				at91_set_A_periph(AT91_PIN_PA10, 1);
				at91_set_A_periph(AT91_PIN_PA11, 1);
			}
		}

		mmc1_data = *data;
		platform_device_register(&at91sam9263_mmc1_device);
	}
}
void __init at91_add_device_cf(struct at91_cf_data *data)
{
	struct platform_device *pdev;
	unsigned long csa;

	if (!data)
		return;

	csa = at91_sys_read(AT91_MATRIX_EBICSA);

	switch (data->chipselect) {
	case 4:
		at91_set_multi_drive(AT91_PIN_PC8, 0);
		at91_set_A_periph(AT91_PIN_PC8, 0);
		csa |= AT91_MATRIX_CS4A_SMC_CF1;
		cf0_data = *data;
		pdev = &cf0_device;
		break;
	case 5:
		at91_set_multi_drive(AT91_PIN_PC9, 0);
		at91_set_A_periph(AT91_PIN_PC9, 0);
		csa |= AT91_MATRIX_CS5A_SMC_CF2;
		cf1_data = *data;
		pdev = &cf1_device;
		break;
	default:
		printk(KERN_ERR "AT91 CF: bad chip-select requested (%u)\n",
		       data->chipselect);
		return;
	}

	at91_sys_write(AT91_MATRIX_EBICSA, csa);

	if (data->rst_pin) {
		at91_set_multi_drive(data->rst_pin, 0);
		at91_set_gpio_output(data->rst_pin, 1);
	}

	if (data->irq_pin) {
		at91_set_gpio_input(data->irq_pin, 0);
		at91_set_deglitch(data->irq_pin, 1);
	}

	if (data->det_pin) {
		at91_set_gpio_input(data->det_pin, 0);
		at91_set_deglitch(data->det_pin, 1);
	}

	at91_set_B_periph(AT91_PIN_PC6, 0);     /* CFCE1 */
	at91_set_B_periph(AT91_PIN_PC7, 0);     /* CFCE2 */
	at91_set_A_periph(AT91_PIN_PC10, 0);    /* CFRNW */
	at91_set_A_periph(AT91_PIN_PC15, 1);    /* NWAIT */

	if (data->flags & AT91_CF_TRUE_IDE)
#if defined(CONFIG_PATA_AT91) || defined(CONFIG_PATA_AT91_MODULE)
		pdev->name = "pata_at91";
#elif defined(CONFIG_BLK_DEV_IDE_AT91) || defined(CONFIG_BLK_DEV_IDE_AT91_MODULE)
		pdev->name = "at91_ide";
#else
#warning "board requires AT91_CF_TRUE_IDE: enable either at91_ide or pata_at91"
#endif
	else
void __init at91_add_device_isi(struct isi_platform_data *data,
		bool use_pck_as_mck)
{
	at91_set_A_periph(AT91_PIN_PE0, 0);	/* ISI_D0 */
	at91_set_A_periph(AT91_PIN_PE1, 0);	/* ISI_D1 */
	at91_set_A_periph(AT91_PIN_PE2, 0);	/* ISI_D2 */
	at91_set_A_periph(AT91_PIN_PE3, 0);	/* ISI_D3 */
	at91_set_A_periph(AT91_PIN_PE4, 0);	/* ISI_D4 */
	at91_set_A_periph(AT91_PIN_PE5, 0);	/* ISI_D5 */
	at91_set_A_periph(AT91_PIN_PE6, 0);	/* ISI_D6 */
	at91_set_A_periph(AT91_PIN_PE7, 0);	/* ISI_D7 */
	at91_set_A_periph(AT91_PIN_PE8, 0);	/* ISI_PCK */
	at91_set_A_periph(AT91_PIN_PE9, 0);	/* ISI_HSYNC */
	at91_set_A_periph(AT91_PIN_PE10, 0);	/* ISI_VSYNC */
	at91_set_B_periph(AT91_PIN_PE12, 0);	/* ISI_PD8 */
	at91_set_B_periph(AT91_PIN_PE13, 0);	/* ISI_PD9 */
	at91_set_B_periph(AT91_PIN_PE14, 0);	/* ISI_PD10 */
	at91_set_B_periph(AT91_PIN_PE15, 0);	/* ISI_PD11 */

	if (use_pck_as_mck) {
		at91_set_B_periph(AT91_PIN_PE11, 0);	/* ISI_MCK (PCK3) */

		/* TODO: register the PCK for ISI_MCK and set its parent */
	}
}
Beispiel #28
0
void at91_add_device_eth(int id, struct macb_platform_data *data)
{
	if (!data)
		return;

	switch (id) {
	case 0:
		if (cpu_is_sama5d31()) {
			pr_warn("AT91: no gmac on sama5d31\n");
			return;
		}

		at91_set_A_periph(AT91_PIN_PB16, 0);	/* GMDC */
		at91_set_A_periph(AT91_PIN_PB17, 0);	/* GMDIO */

		at91_set_A_periph(AT91_PIN_PB9, 0);	/* GTXEN */
		at91_set_A_periph(AT91_PIN_PB11, 0);	/* GRXCK */
		at91_set_A_periph(AT91_PIN_PB13, 0);	/* GRXER */

		switch (data->phy_interface) {
		case PHY_INTERFACE_MODE_GMII:
			at91_set_B_periph(AT91_PIN_PB19, 0);	/* GTX4 */
			at91_set_B_periph(AT91_PIN_PB20, 0);	/* GTX5 */
			at91_set_B_periph(AT91_PIN_PB21, 0);	/* GTX6 */
			at91_set_B_periph(AT91_PIN_PB22, 0);	/* GTX7 */
			at91_set_B_periph(AT91_PIN_PB23, 0);	/* GRX4 */
			at91_set_B_periph(AT91_PIN_PB24, 0);	/* GRX5 */
			at91_set_B_periph(AT91_PIN_PB25, 0);	/* GRX6 */
			at91_set_B_periph(AT91_PIN_PB26, 0);	/* GRX7 */
		case PHY_INTERFACE_MODE_MII:
		case PHY_INTERFACE_MODE_RGMII:
			at91_set_A_periph(AT91_PIN_PB0, 0);	/* GTX0 */
			at91_set_A_periph(AT91_PIN_PB1, 0);	/* GTX1 */
			at91_set_A_periph(AT91_PIN_PB2, 0);	/* GTX2 */
			at91_set_A_periph(AT91_PIN_PB3, 0);	/* GTX3 */
			at91_set_A_periph(AT91_PIN_PB4, 0);	/* GRX0 */
			at91_set_A_periph(AT91_PIN_PB5, 0);	/* GRX1 */
			at91_set_A_periph(AT91_PIN_PB6, 0);	/* GRX2 */
			at91_set_A_periph(AT91_PIN_PB7, 0);	/* GRX3 */
			break;
		default:
			return;
		}

		switch (data->phy_interface) {
		case PHY_INTERFACE_MODE_MII:
			at91_set_A_periph(AT91_PIN_PB8, 0);	/* GTXCK */
			at91_set_A_periph(AT91_PIN_PB10, 0);	/* GTXER */
			at91_set_A_periph(AT91_PIN_PB12, 0);	/* GRXDV */
			at91_set_A_periph(AT91_PIN_PB14, 0);	/* GCRS */
			at91_set_A_periph(AT91_PIN_PB15, 0);	/* GCOL */
			break;
		case PHY_INTERFACE_MODE_RGMII:
			at91_set_A_periph(AT91_PIN_PB8, 0);	/* GTXCK */
			at91_set_A_periph(AT91_PIN_PB18, 0);	/* G125CK */
			break;
		case PHY_INTERFACE_MODE_GMII:
			at91_set_A_periph(AT91_PIN_PB10, 0);	/* GTXER */
			at91_set_A_periph(AT91_PIN_PB12, 0);	/* GRXDV */
			at91_set_A_periph(AT91_PIN_PB14, 0);	/* GCRS */
			at91_set_A_periph(AT91_PIN_PB15, 0);	/* GCOL */
			at91_set_A_periph(AT91_PIN_PB27, 0);	/* G125CK0 */
			break;
		default:
			return;
		}

		add_generic_device("macb", id, NULL, SAMA5D3_BASE_GMAC, SZ_16K,
			   IORESOURCE_MEM, data);
		break;
	case 1:
		if (cpu_is_sama5d33() || cpu_is_sama5d34()) {
			pr_warn("AT91: no macb on sama5d33/d34\n");
			return;
		}

		if (data->phy_interface != PHY_INTERFACE_MODE_RMII) {
			pr_warn("AT91: Only RMII available on interfacr macb%d.\n", id);
			return;
		}

		at91_set_A_periph(AT91_PIN_PC7, 0);	/* ETXCK_EREFCK */
		at91_set_A_periph(AT91_PIN_PC5, 0);	/* ERXDV */
		at91_set_A_periph(AT91_PIN_PC2, 0);	/* ERX0 */
		at91_set_A_periph(AT91_PIN_PC3, 0);	/* ERX1 */
		at91_set_A_periph(AT91_PIN_PC6, 0);	/* ERXER */
		at91_set_A_periph(AT91_PIN_PC4, 0);	/* ETXEN */
		at91_set_A_periph(AT91_PIN_PC0, 0);	/* ETX0 */
		at91_set_A_periph(AT91_PIN_PC1, 0);	/* ETX1 */
		at91_set_A_periph(AT91_PIN_PC9, 0);	/* EMDIO */
		at91_set_A_periph(AT91_PIN_PC8, 0);	/* EMDC */
		add_generic_device("macb", id, NULL, SAMA5D3_BASE_EMAC, SZ_16K,
			   IORESOURCE_MEM, data);
		break;
	default:
		return;
	}

}
Beispiel #29
0
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
{
	if (!data)
		return;

	/* input/irq */
	if (data->det_pin) {
		at91_set_gpio_input(data->det_pin, 1);
		at91_set_deglitch(data->det_pin, 1);
	}
	if (data->wp_pin)
		at91_set_gpio_input(data->wp_pin, 1);
	if (data->vcc_pin)
		at91_set_gpio_output(data->vcc_pin, 0);

	if (mmc_id == 0) {		/* MCI0 */
		/* CLK */
		at91_set_A_periph(AT91_PIN_PA2, 0);

		/* CMD */
		at91_set_A_periph(AT91_PIN_PA1, 1);

		/* DAT0, maybe DAT1..DAT3 */
		at91_set_A_periph(AT91_PIN_PA0, 1);
		if (data->wire4) {
			at91_set_A_periph(AT91_PIN_PA3, 1);
			at91_set_A_periph(AT91_PIN_PA4, 1);
			at91_set_A_periph(AT91_PIN_PA5, 1);
		}

		mmc0_data = *data;
		at91_clock_associate("mci0_clk", &at91cap9_mmc0_device.dev, "mci_clk");
		platform_device_register(&at91cap9_mmc0_device);
	} else {			/* MCI1 */
		/* CLK */
		at91_set_A_periph(AT91_PIN_PA16, 0);

		/* CMD */
		at91_set_A_periph(AT91_PIN_PA17, 1);

		/* DAT0, maybe DAT1..DAT3 */
		at91_set_A_periph(AT91_PIN_PA18, 1);
		if (data->wire4) {
			at91_set_A_periph(AT91_PIN_PA19, 1);
			at91_set_A_periph(AT91_PIN_PA20, 1);
			at91_set_A_periph(AT91_PIN_PA21, 1);
		}

		mmc1_data = *data;
		at91_clock_associate("mci1_clk", &at91cap9_mmc1_device.dev, "mci_clk");
		platform_device_register(&at91cap9_mmc1_device);
	}
}
Beispiel #30
0
static void afeb9260_macb_hw_init(void)
{
	/* Enable clock */
	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);

	/*
	 * Disable pull-up on:
	 *	RXDV (PA17) => PHY normal mode (not Test mode)
	 *	ERX0 (PA14) => PHY ADDR0
	 *	ERX1 (PA15) => PHY ADDR1
	 *	ERX2 (PA25) => PHY ADDR2
	 *	ERX3 (PA26) => PHY ADDR3
	 *	ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
	 *
	 * PHY has internal pull-down
	 */
	writel(pin_to_mask(AT91_PIN_PA14) |
	       pin_to_mask(AT91_PIN_PA15) |
	       pin_to_mask(AT91_PIN_PA17) |
	       pin_to_mask(AT91_PIN_PA25) |
	       pin_to_mask(AT91_PIN_PA26) |
	       pin_to_mask(AT91_PIN_PA28),
	       pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);

	/* Need to reset PHY -> 500ms reset */
	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
				     AT91_RSTC_ERSTL | (0x0D << 8) |
				     AT91_RSTC_URSTEN);

	at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);

	/* Wait for end hardware reset */
	while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));

	/* Restore NRST value */
	at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
				     AT91_RSTC_ERSTL | (0x0 << 8) |
				     AT91_RSTC_URSTEN);

	/* Re-enable pull-up */
	writel(pin_to_mask(AT91_PIN_PA14) |
	       pin_to_mask(AT91_PIN_PA15) |
	       pin_to_mask(AT91_PIN_PA17) |
	       pin_to_mask(AT91_PIN_PA25) |
	       pin_to_mask(AT91_PIN_PA26) |
	       pin_to_mask(AT91_PIN_PA28),
	       pin_to_controller(AT91_PIN_PA0) + PIO_PUER);

	at91_set_A_periph(AT91_PIN_PA19, 0);	/* ETXCK_EREFCK */
	at91_set_A_periph(AT91_PIN_PA17, 0);	/* ERXDV */
	at91_set_A_periph(AT91_PIN_PA14, 0);	/* ERX0 */
	at91_set_A_periph(AT91_PIN_PA15, 0);	/* ERX1 */
	at91_set_A_periph(AT91_PIN_PA18, 0);	/* ERXER */
	at91_set_A_periph(AT91_PIN_PA16, 0);	/* ETXEN */
	at91_set_A_periph(AT91_PIN_PA12, 0);	/* ETX0 */
	at91_set_A_periph(AT91_PIN_PA13, 0);	/* ETX1 */
	at91_set_A_periph(AT91_PIN_PA21, 0);	/* EMDIO */
	at91_set_A_periph(AT91_PIN_PA20, 0);	/* EMDC */

#ifndef CONFIG_RMII
	at91_set_B_periph(AT91_PIN_PA28, 0);	/* ECRS */
	at91_set_B_periph(AT91_PIN_PA29, 0);	/* ECOL */
	at91_set_B_periph(AT91_PIN_PA25, 0);	/* ERX2 */
	at91_set_B_periph(AT91_PIN_PA26, 0);	/* ERX3 */
	at91_set_B_periph(AT91_PIN_PA27, 0);	/* ERXCK */
	at91_set_B_periph(AT91_PIN_PA10, 0);	/* ETX2 */
	at91_set_B_periph(AT91_PIN_PA11, 0);	/* ETX3 */
	at91_set_B_periph(AT91_PIN_PA22, 0);	/* ETXER */
#endif

}