static int dpi_check_timings(struct omap_dss_device *dssdev,
struct omap_video_timings *timings)
{
bool is_tft;
int r;
int lck_div, pck_div;
unsigned long fck;
unsigned long pck;
if (!dispc_lcd_timings_ok(timings))
return -EINVAL;
if (timings->pixel_clock == 0)
return -EINVAL;
is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
{
struct dsi_clock_info cinfo;
r = dsi_pll_calc_pck(is_tft, timings->pixel_clock * 1000,
&cinfo);
if (r)
return r;
fck = cinfo.dsi1_pll_fclk;
lck_div = cinfo.lck_div;
pck_div = cinfo.pck_div;
}
#else
{
struct dispc_clock_info cinfo;
r = dispc_calc_clock_div(is_tft, timings->pixel_clock * 1000,
&cinfo);
if (r)
return r;
fck = cinfo.fck;
lck_div = cinfo.lck_div;
pck_div = cinfo.pck_div;
}
#endif
pck = fck / lck_div / pck_div / 1000;
timings->pixel_clock = pck;
return 0;
}
static int dpi_set_dispc_clk(bool is_tft, unsigned long pck_req,
unsigned long *fck, int *lck_div, int *pck_div)
{
struct dispc_clock_info cinfo;
int r;
r = dispc_calc_clock_div(is_tft, pck_req, &cinfo);
if (r)
return r;
r = dispc_set_clock_div(&cinfo);
if (r)
return r;
*fck = cinfo.fck;
*lck_div = cinfo.lck_div;
*pck_div = cinfo.pck_div;
return 0;
}
static int sdi_display_enable(struct omap_display *display)
{
struct dispc_clock_info cinfo;
u16 lck_div, pck_div;
unsigned long fck;
struct omap_panel *panel = display->panel;
unsigned long pck;
int r;
if (display->state != OMAP_DSS_DISPLAY_DISABLED) {
DSSERR("display already enabled\n");
return -EINVAL;
}
twl4030_enable_regulator(RES_VAUX1);
sdi_pad_config(display, 1);
/* In case of skip_init sdi_init has already enabled the clocks */
if (!sdi.skip_init)
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
sdi_basic_init();
/* 15.5.9.1.2 */
panel->config |= OMAP_DSS_LCD_RF | OMAP_DSS_LCD_ONOFF;
dispc_set_pol_freq(panel);
if (!sdi.skip_init)
r = dispc_calc_clock_div(1, panel->timings.pixel_clock * 1000,
&cinfo);
else
r = dispc_get_clock_div(&cinfo);
if (r)
goto err0;
fck = cinfo.fck;
lck_div = cinfo.lck_div;
pck_div = cinfo.pck_div;
pck = fck / lck_div / pck_div / 1000;
if (pck != panel->timings.pixel_clock) {
DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
"got %lu kHz\n",
panel->timings.pixel_clock, pck);
panel->timings.pixel_clock = pck;
}
dispc_set_lcd_timings(&panel->timings);
r = dispc_set_clock_div(&cinfo);
if (r)
goto err1;
if (!sdi.skip_init) {
dss_sdi_init(display->hw_config.u.sdi.datapairs);
r = dss_sdi_enable();
if (r)
goto err1;
mdelay(2);
}
dispc_enable_lcd_out(1);
r = panel->enable(display);
if (r)
goto err2;
display->state = OMAP_DSS_DISPLAY_ACTIVE;
sdi.skip_init = 0;
return 0;
err2:
dispc_enable_lcd_out(0);
err1:
err0:
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
twl4030_disable_regulator(RES_VAUX1);
return r;
}
static int dpi_check_timings(struct omap_display *display,
struct omap_video_timings *timings)
{
bool is_tft;
int r;
int lck_div, pck_div;
unsigned long fck;
unsigned long pck;
if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
if (timings->hsw < 1 || timings->hsw > 64 ||
timings->hfp < 1 || timings->hfp > 256 ||
timings->hbp < 1 || timings->hbp > 256) {
return -EINVAL;
}
if (timings->vsw < 1 || timings->vsw > 64 ||
timings->vfp > 255 || timings->vbp > 255) {
return -EINVAL;
}
} else {
if (timings->hsw < 1 || timings->hsw > 256 ||
timings->hfp < 1 || timings->hfp > 4096 ||
timings->hbp < 1 || timings->hbp > 4096) {
return -EINVAL;
}
if (timings->vsw < 1 || timings->vsw > 64 ||
timings->vfp > 4095 || timings->vbp > 4095) {
return -EINVAL;
}
}
if (timings->pixel_clock == 0)
return -EINVAL;
is_tft = (display->panel->config & OMAP_DSS_LCD_TFT) != 0;
#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
{
struct dsi_clock_info cinfo;
r = dsi_pll_calc_pck(is_tft, timings->pixel_clock * 1000,
&cinfo);
if (r)
return r;
fck = cinfo.dsi1_pll_fclk;
lck_div = cinfo.lck_div;
pck_div = cinfo.pck_div;
}
#else
{
struct dispc_clock_info cinfo;
r = dispc_calc_clock_div(is_tft, timings->pixel_clock * 1000,
&cinfo);
if (r)
return r;
fck = cinfo.fck;
lck_div = cinfo.lck_div;
pck_div = cinfo.pck_div;
}
#endif
pck = fck / lck_div / pck_div / 1000;
timings->pixel_clock = pck;
return 0;
}
