static int do_sdhci_init(struct sdhci_host *host)
{
int dev_id, flag, ret;
flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
dev_id = host->index + PERIPH_ID_SDMMC0;
ret = exynos_pinmux_config(dev_id, flag);
if (ret) {
printf("external SD not configured\n");
return ret;
}
if (dm_gpio_is_valid(&host->pwr_gpio)) {
dm_gpio_set_value(&host->pwr_gpio, 1);
ret = exynos_pinmux_config(dev_id, flag);
if (ret) {
debug("MMC not configured\n");
return ret;
}
}
if (dm_gpio_is_valid(&host->cd_gpio)) {
ret = dm_gpio_get_value(&host->cd_gpio);
if (ret) {
debug("no SD card detected (%d)\n", ret);
return -ENODEV;
}
}
return s5p_sdhci_core_init(host);
}
static int do_sdhci_init(struct sdhci_host *host)
{
int dev_id, flag;
int err = 0;
flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
dev_id = host->index + PERIPH_ID_SDMMC0;
if (dm_gpio_is_valid(&host->pwr_gpio)) {
dm_gpio_set_value(&host->pwr_gpio, 1);
err = exynos_pinmux_config(dev_id, flag);
if (err) {
debug("MMC not configured\n");
return err;
}
}
if (dm_gpio_is_valid(&host->cd_gpio)) {
if (dm_gpio_get_value(&host->cd_gpio))
return -ENODEV;
err = exynos_pinmux_config(dev_id, flag);
if (err) {
printf("external SD not configured\n");
return err;
}
}
return s5p_sdhci_core_init(host);
}
int board_mmc_init(bd_t *bis)
{
int err, ret = 0, index, bus_width;
u32 base;
err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
if (err)
debug("SDMMC0 not configured\n");
ret |= err;
/*EMMC: dwmmc Channel-0 with 8 bit bus width */
index = 0;
base = samsung_get_base_mmc() + (0x10000 * index);
bus_width = 8;
err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
if (err)
debug("dwmmc Channel-0 init failed\n");
ret |= err;
err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
if (err)
debug("SDMMC2 not configured\n");
ret |= err;
/*SD: dwmmc Channel-2 with 4 bit bus width */
index = 2;
base = samsung_get_base_mmc() + (0x10000 * index);
bus_width = 4;
err = exynos_dwmci_add_port(index, base, bus_width, (u32)NULL);
if (err)
debug("dwmmc Channel-2 init failed\n");
ret |= err;
return ret;
}
static int board_uart_init(void)
{
int err;
err = exynos_pinmux_config(PERIPH_ID_UART0, PINMUX_FLAG_NONE);
if (err) {
debug("UART0 not configured\n");
return err;
}
err = exynos_pinmux_config(PERIPH_ID_UART1, PINMUX_FLAG_NONE);
if (err) {
debug("UART1 not configured\n");
return err;
}
err = exynos_pinmux_config(PERIPH_ID_UART2, PINMUX_FLAG_NONE);
if (err) {
debug("UART2 not configured\n");
return err;
}
err = exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
if (err) {
debug("UART3 not configured\n");
return err;
}
return 0;
}
int board_mmc_init(bd_t *bis)
{
int err;
switch (get_hwrev()) {
case 0:
/*
* Set the low to enable LDO_EN
* But when you use the test board for eMMC booting
* you should set it HIGH since it removes the inverter
*/
/* MASSMEMORY_EN: XMDMDATA_6: GPE3[6] */
s5p_gpio_direction_output(&gpio1->e3, 6, 0);
break;
default:
/*
* Default reset state is High and there's no inverter
* But set it as HIGH to ensure
*/
/* MASSMEMORY_EN: XMDMADDR_3: GPE1[3] */
s5p_gpio_direction_output(&gpio1->e1, 3, 1);
break;
}
/*
* MMC device init
* mmc0 : eMMC (8-bit buswidth)
* mmc2 : SD card (4-bit buswidth)
*/
err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
if (err)
debug("SDMMC0 not configured\n");
else
err = s5p_mmc_init(0, 8);
/* T-flash detect */
s5p_gpio_cfg_pin(&gpio2->x3, 4, 0xf);
s5p_gpio_set_pull(&gpio2->x3, 4, GPIO_PULL_UP);
/*
* Check the T-flash detect pin
* GPX3[4] T-flash detect pin
*/
if (!s5p_gpio_get_value(&gpio2->x3, 4)) {
err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
if (err)
debug("SDMMC2 not configured\n");
else
err = s5p_mmc_init(2, 4);
}
return err;
}
static void initialize_s5p_mshc(void)
{
/* MMC0: Fixed, 8 bit mode, connected with GPIO. */
if (clock_set_mshci(PERIPH_ID_SDMMC0))
printk(BIOS_CRIT, "Failed to set clock for SDMMC0.\n");
if (gpio_direction_output(MMC0_GPIO_PIN, 1)) {
printk(BIOS_CRIT, "Unable to power on SDMMC0.\n");
}
gpio_set_pull(MMC0_GPIO_PIN, EXYNOS_GPIO_PULL_NONE);
gpio_set_drv(MMC0_GPIO_PIN, EXYNOS_GPIO_DRV_4X);
exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
/* MMC2: Removable, 4 bit mode, no GPIO. */
clock_set_mshci(PERIPH_ID_SDMMC2);
exynos_pinmux_config(PERIPH_ID_SDMMC2, 0);
}
static int smc9115_pre_init(void)
{
u32 smc_bw_conf, smc_bc_conf;
int err;
/* Ethernet needs data bus width of 16 bits */
smc_bw_conf = SROMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK)
| SROMC_BYTE_ENABLE(CONFIG_ENV_SROM_BANK);
smc_bc_conf = SROMC_BC_TACS(0x01) | SROMC_BC_TCOS(0x01)
| SROMC_BC_TACC(0x06) | SROMC_BC_TCOH(0x01)
| SROMC_BC_TAH(0x0C) | SROMC_BC_TACP(0x09)
| SROMC_BC_PMC(0x01);
/* Select and configure the SROMC bank */
err = exynos_pinmux_config(PERIPH_ID_SROMC,
CONFIG_ENV_SROM_BANK | PINMUX_FLAG_16BIT);
if (err) {
debug("SROMC not configured\n");
return err;
}
s5p_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
return 0;
}
static int board_uart_init(void)
{
int err;
err = exynos_pinmux_config(PERIPH_ID_UART, PINMUX_FLAG_NONE);
if (err)
debug("UART%d not configured\n",
PERIPH_ID_UART - PERIPH_ID_UART0);
return err;
}
void board_i2c_init(const void *blob)
{
int i;
for (i = 0; i < CONFIG_MAX_I2C_NUM; i++) {
exynos_pinmux_config((PERIPH_ID_I2C0 + i),
PINMUX_FLAG_NONE);
}
}
int lowlevel_init_subsystems(void)
{
// uint32_t reset_status;
int actions = 0;
// do_barriers();
/* Setup cpu info which is needed to select correct register offsets */
cpu_info_init();
#if 0
reset_status = power_read_reset_status();
switch (reset_status) {
case S5P_CHECK_SLEEP:
actions = DO_CLOCKS | DO_WAKEUP;
break;
case S5P_CHECK_DIDLE:
case S5P_CHECK_LPA:
actions = DO_WAKEUP;
default:
/* This is a normal boot (not a wake from sleep) */
actions = DO_UART | DO_CLOCKS | DO_POWER;
}
#endif
actions = DO_UART | DO_CLOCKS | DO_POWER;
if (actions & DO_POWER)
power_init();
if (actions & DO_CLOCKS)
system_clock_init();
if (actions & DO_UART) {
/* Set up serial UART so we can printf() */
/* FIXME(dhendrix): add a function for mapping
CONFIG_CONSOLE_SERIAL_UART_ADDRESS to PERIPH_ID_UARTn */
// exynos_pinmux_config(EXYNOS_UART, PINMUX_FLAG_NONE);
exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
console_init();
while (1) {
console_tx_byte('C');
}
}
init_timer(); /* FIXME(dhendrix): was timer_init() */
#if 0
if (actions & DO_CLOCKS) {
mem_ctrl_init();
tzpc_init();
}
#endif
// return actions & DO_WAKEUP;
return 0;
}
int board_emmc_init(void)
{
int err;
err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
if (err) {
debug("SDMMC0 not configured\n");
return err;
}
return s5p_mmc_init(0, 8);
}
int board_sdmmc_init(void)
{
int err;
err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
if (err) {
debug("SDMMC2 not configured\n");
return err;
}
return s5p_mmc_init(2, 4);
}
int board_mmc_init(bd_t *bis)
{
struct exynos4_gpio_part2 *gpio =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
int err;
/* eMMC_EN: SD_0_CDn: GPK0[2] Output High */
s5p_gpio_direction_output(&gpio->k0, 2, 1);
s5p_gpio_set_pull(&gpio->k0, 2, GPIO_PULL_NONE);
/*
* MMC device init
* mmc0 : eMMC (8-bit buswidth)
* mmc2 : SD card (4-bit buswidth)
*/
err = exynos_pinmux_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
if (err)
debug("SDMMC0 not configured\n");
else
err = s5p_mmc_init(0, 8);
/* T-flash detect */
s5p_gpio_cfg_pin(&gpio->x3, 4, 0xf);
s5p_gpio_set_pull(&gpio->x3, 4, GPIO_PULL_UP);
/*
* Check the T-flash detect pin
* GPX3[4] T-flash detect pin
*/
if (!s5p_gpio_get_value(&gpio->x3, 4)) {
err = exynos_pinmux_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
if (err)
debug("SDMMC2 not configured\n");
else
err = s5p_mmc_init(2, 4);
}
return err;
}
static int board_uart_init(void)
{
int err, uart_id, ret = 0;
for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
if (err) {
debug("UART%d not configured\n",
(uart_id - PERIPH_ID_UART0));
ret |= err;
}
}
return ret;
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SMC911X
u32 smc_bw_conf, smc_bc_conf;
struct fdt_sromc config;
fdt_addr_t base_addr;
int node;
node = decode_sromc(gd->fdt_blob, &config);
if (node < 0) {
debug("%s: Could not find sromc configuration\n", __func__);
return 0;
}
node = fdtdec_next_compatible(gd->fdt_blob, node, COMPAT_SMSC_LAN9215);
if (node < 0) {
debug("%s: Could not find lan9215 configuration\n", __func__);
return 0;
}
/* We now have a node, so any problems from now on are errors */
base_addr = fdtdec_get_addr(gd->fdt_blob, node, "reg");
if (base_addr == FDT_ADDR_T_NONE) {
debug("%s: Could not find lan9215 address\n", __func__);
return -1;
}
/* Ethernet needs data bus width of 16 bits */
if (config.width != 2) {
debug("%s: Unsupported bus width %d\n", __func__,
config.width);
return -1;
}
smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
| SROMC_BYTE_ENABLE(config.bank);
smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |
SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |
SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |
SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |
SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |
SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |
SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
/* Select and configure the SROMC bank */
exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
return smc911x_initialize(0, base_addr);
#endif
return 0;
}
static int do_sdhci_init(struct sdhci_host *host)
{
char str[20];
int dev_id, flag;
int err = 0;
flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
dev_id = host->index + PERIPH_ID_SDMMC0;
if (fdt_gpio_isvalid(&host->pwr_gpio)) {
sprintf(str, "sdhci%d_power", host->index & 0xf);
gpio_request(host->pwr_gpio.gpio, str);
gpio_direction_output(host->pwr_gpio.gpio, 1);
err = exynos_pinmux_config(dev_id, flag);
if (err) {
debug("MMC not configured\n");
return err;
}
}
if (fdt_gpio_isvalid(&host->cd_gpio)) {
sprintf(str, "sdhci%d_cd", host->index & 0xf);
gpio_request(host->cd_gpio.gpio, str);
gpio_direction_input(host->cd_gpio.gpio);
if (gpio_get_value(host->cd_gpio.gpio))
return -ENODEV;
err = exynos_pinmux_config(dev_id, flag);
if (err) {
printf("external SD not configured\n");
return err;
}
}
return s5p_sdhci_core_init(host);
}
void i2c_init_board(void)
{
int err;
/* I2C_5 -> PMIC */
err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
if (err) {
debug("I2C%d not configured\n", (I2C_5));
return;
}
/* I2C_8 -> FG */
gpio_direction_output(EXYNOS4_GPIO_Y40, 1);
gpio_direction_output(EXYNOS4_GPIO_Y41, 1);
}
static void board_init_i2c(void)
{
int err;
/* I2C_1 */
err = exynos_pinmux_config(PERIPH_ID_I2C1, PINMUX_FLAG_NONE);
if (err) {
debug("I2C%d not configured\n", (I2C_1));
return;
}
/* I2C_1 */
/*
gpio_direction_output(EXYNOS4X12_GPIO_D12, 1);
gpio_direction_output(EXYNOS4X12_GPIO_D13, 1);
*/
}
void i2c_init_board(void)
{
int err;
struct exynos4_gpio_part2 *gpio2 =
(struct exynos4_gpio_part2 *)samsung_get_base_gpio_part2();
/* I2C_5 -> PMIC */
err = exynos_pinmux_config(PERIPH_ID_I2C5, PINMUX_FLAG_NONE);
if (err) {
debug("I2C%d not configured\n", (I2C_5));
return;
}
/* I2C_8 -> FG */
s5p_gpio_direction_output(&gpio2->y4, 0, 1);
s5p_gpio_direction_output(&gpio2->y4, 1, 1);
}
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_SMC911X
u32 smc_bw_conf, smc_bc_conf;
struct fdt_sromc config;
fdt_addr_t base_addr;
/* Non-FDT configuration - bank number and timing parameters*/
config.bank = CONFIG_ENV_SROM_BANK;
config.width = 2;
config.timing[FDT_SROM_TACS] = 0x01;
config.timing[FDT_SROM_TCOS] = 0x01;
config.timing[FDT_SROM_TACC] = 0x06;
config.timing[FDT_SROM_TCOH] = 0x01;
config.timing[FDT_SROM_TAH] = 0x0C;
config.timing[FDT_SROM_TACP] = 0x09;
config.timing[FDT_SROM_PMC] = 0x01;
base_addr = CONFIG_SMC911X_BASE;
/* Ethernet needs data bus width of 16 bits */
if (config.width != 2) {
debug("%s: Unsupported bus width %d\n", __func__,
config.width);
return -1;
}
smc_bw_conf = SROMC_DATA16_WIDTH(config.bank)
| SROMC_BYTE_ENABLE(config.bank);
smc_bc_conf = SROMC_BC_TACS(config.timing[FDT_SROM_TACS]) |\
SROMC_BC_TCOS(config.timing[FDT_SROM_TCOS]) |\
SROMC_BC_TACC(config.timing[FDT_SROM_TACC]) |\
SROMC_BC_TCOH(config.timing[FDT_SROM_TCOH]) |\
SROMC_BC_TAH(config.timing[FDT_SROM_TAH]) |\
SROMC_BC_TACP(config.timing[FDT_SROM_TACP]) |\
SROMC_BC_PMC(config.timing[FDT_SROM_PMC]);
/* Select and configure the SROMC bank */
exynos_pinmux_config(PERIPH_ID_SROMC, config.bank);
s5p_config_sromc(config.bank, smc_bw_conf, smc_bc_conf);
return smc911x_initialize(0, base_addr);
#endif
return 0;
}
int i2s_tx_init(struct i2stx_info *pi2s_tx)
{
int ret;
struct i2s_reg *i2s_reg =
(struct i2s_reg *)pi2s_tx->base_address;
/* Initialize GPIO for I2s */
exynos_pinmux_config(PERIPH_ID_I2S1, 0);
/* Set EPLL Clock */
ret = set_epll_clk(pi2s_tx->audio_pll_clk);
if (ret != 0) {
debug("%s: epll clock set rate falied\n", __func__);
return -1;
}
/* Select Clk Source for Audio1 */
set_i2s_clk_source();
/* Set Prescaler to get MCLK */
set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk,
(pi2s_tx->samplingrate * (pi2s_tx->rfs)));
/* Configure I2s format */
ret = i2s_set_fmt(i2s_reg, (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM));
if (ret == 0) {
i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs);
ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample);
if (ret != 0) {
debug("%s:set sample rate failed\n", __func__);
return -1;
}
i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs);
/* disable i2s transfer flag and flush the fifo */
i2s_txctrl(i2s_reg, I2S_TX_OFF);
i2s_fifo(i2s_reg, FIC_TXFLUSH);
} else {
debug("%s: failed\n", __func__);
}
return ret;
}
int board_dp_bridge_setup(const void *blob, unsigned *wait_ms)
{
int ret;
ret = board_dp_fill_gpios(blob);
if (ret)
return ret;
/* Mux HPHPD to the special hotplug detect mode */
exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
/* Setup the GPIOs */
ret = fdtdec_setup_gpio(&local.dp_pd);
if (ret) {
debug("%s: Could not setup pd gpio (%d)\n", __func__, ret);
return ret;
}
ret = fdtdec_setup_gpio(&local.dp_rst);
if (ret) {
debug("%s: Could not setup rst gpio (%d)\n", __func__, ret);
return ret;
}
ret = fdtdec_setup_gpio(&local.dp_hpd);
if (ret) {
debug("%s: Could not setup hpd gpio (%d)\n", __func__, ret);
return ret;
}
fdtdec_set_gpio(&local.dp_pd, 0);
gpio_cfg_pin(local.dp_pd.gpio, EXYNOS_GPIO_OUTPUT);
gpio_set_pull(local.dp_pd.gpio, EXYNOS_GPIO_PULL_NONE);
if (fdt_gpio_isvalid(&local.dp_rst)) {
fdtdec_set_gpio(&local.dp_rst, 1);
gpio_cfg_pin(local.dp_rst.gpio, EXYNOS_GPIO_OUTPUT);
gpio_set_pull(local.dp_rst.gpio, EXYNOS_GPIO_PULL_NONE);
udelay(10);
fdtdec_set_gpio(&local.dp_rst, 0);
}
*wait_ms = 0;
return 0;
}
int lowlevel_init_subsystems(void)
{
uint32_t reset_status;
int actions = 0;
do_barriers();
/* Setup cpu info which is needed to select correct register offsets */
cpu_info_init();
reset_status = power_read_reset_status();
switch (reset_status) {
case S5P_CHECK_SLEEP:
actions = DO_CLOCKS | DO_WAKEUP;
break;
case S5P_CHECK_DIDLE:
case S5P_CHECK_LPA:
actions = DO_WAKEUP;
break;
default:
/* This is a normal boot (not a wake from sleep) */
actions = DO_UART | DO_CLOCKS | DO_POWER | DO_MEM_RESET;
}
if (actions & DO_POWER)
power_init();
if (actions & DO_CLOCKS)
system_clock_init();
if (actions & DO_UART) {
/* Set up serial UART so we can printf() */
exynos_pinmux_config(EXYNOS_UART, PINMUX_FLAG_NONE);
serial_init();
timer_init();
}
if (actions & DO_CLOCKS) {
mem_ctrl_init(actions & DO_MEM_RESET);
tzpc_init();
}
return actions & DO_WAKEUP;
}
static int board_dp_bridge_setup(const void *blob)
{
const int max_tries = 2;
int num_tries;
struct udevice *dev;
int ret;
/* Configure I2C registers for Parade bridge */
ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &dev);
if (ret) {
debug("video bridge init failed: %d\n", ret);
return ret;
}
if (strncmp(dev->driver->name, "parade", 6)) {
/* Mux HPHPD to the special hotplug detect mode */
exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
}
for (num_tries = 0; num_tries < max_tries; num_tries++) {
ret = board_dp_bridge_init(dev);
if (!ret)
return 0;
if (num_tries == max_tries - 1)
break;
/*
* If we're here, the bridge chip failed to initialise.
* Power down the bridge in an attempt to reset.
*/
video_bridge_set_active(dev, false);
/*
* Arbitrarily wait 300ms here with DP_N low. Don't know for
* sure how long we should wait, but we're being paranoid.
*/
mdelay(300);
}
return ret;
}
static void board_init_i2c(void)
{
int err;
gpio1 = (struct exynos4x12_gpio_part1 *)samsung_get_base_gpio_part1();
gpio2 = (struct exynos4x12_gpio_part2 *)samsung_get_base_gpio_part2();
/* I2C_7 */
err = exynos_pinmux_config(PERIPH_ID_I2C7, PINMUX_FLAG_NONE);
if (err) {
debug("I2C%d not configured\n", (I2C_7));
return;
}
/* I2C_8 */
s5p_gpio_direction_output(&gpio1->f1, 4, 1);
s5p_gpio_direction_output(&gpio1->f1, 5, 1);
/* I2C_9 */
s5p_gpio_direction_output(&gpio2->m2, 1, 1);
s5p_gpio_direction_output(&gpio2->m2, 0, 1);
}
static int s3c_i2c_ofdata_to_platdata(struct udevice *dev)
{
const void *blob = gd->fdt_blob;
struct s3c24x0_i2c_bus *i2c_bus = dev_get_priv(dev);
int node;
node = dev_of_offset(dev);
i2c_bus->regs = (struct s3c24x0_i2c *)dev_get_addr(dev);
i2c_bus->id = pinmux_decode_periph_id(blob, node);
i2c_bus->clock_frequency = fdtdec_get_int(blob, node,
"clock-frequency", 100000);
i2c_bus->node = node;
i2c_bus->bus_num = dev->seq;
exynos_pinmux_config(i2c_bus->id, 0);
i2c_bus->active = true;
return 0;
}
int exynos_dwmmc_init(const void *blob)
{
int index, bus_width;
int node_list[DWMMC_MAX_CH_NUM];
int err = 0, dev_id, flag, count, i;
u32 clksel_val, base, timing[3];
count = fdtdec_find_aliases_for_id(blob, "mmc",
COMPAT_SAMSUNG_EXYNOS5_DWMMC, node_list,
DWMMC_MAX_CH_NUM);
for (i = 0; i < count; i++) {
int node = node_list[i];
if (node <= 0)
continue;
/* Extract device id for each mmc channel */
dev_id = pinmux_decode_periph_id(blob, node);
/* Get the bus width from the device node */
bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
if (bus_width <= 0) {
debug("DWMMC: Can't get bus-width\n");
return -1;
}
if (8 == bus_width)
flag = PINMUX_FLAG_8BIT_MODE;
else
flag = PINMUX_FLAG_NONE;
/* config pinmux for each mmc channel */
err = exynos_pinmux_config(dev_id, flag);
if (err) {
debug("DWMMC not configured\n");
return err;
}
index = dev_id - PERIPH_ID_SDMMC0;
/* Get the base address from the device node */
base = fdtdec_get_addr(blob, node, "reg");
if (!base) {
debug("DWMMC: Can't get base address\n");
return -1;
}
/* Extract the timing info from the node */
err = fdtdec_get_int_array(blob, node, "samsung,timing",
timing, 3);
if (err) {
debug("Can't get sdr-timings for divider\n");
return -1;
}
clksel_val = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
DWMCI_SET_DRV_CLK(timing[1]) |
DWMCI_SET_DIV_RATIO(timing[2]));
/* Initialise each mmc channel */
err = exynos_dwmci_add_port(index, base, bus_width, clksel_val);
if (err)
debug("dwmmc Channel-%d init failed\n", index);
}
return 0;
}
static void graphics(void)
{
exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
}
int board_early_init_f(void)
{
exynos_pinmux_config(EXYNOS_UART, PINMUX_FLAG_NONE);
return 0;
}
static int i2s_tx_init(struct i2s_uc_priv *pi2s_tx)
{
int ret;
struct i2s_reg *i2s_reg = (struct i2s_reg *)pi2s_tx->base_address;
if (pi2s_tx->id == 0) {
/* Initialize GPIO for I2S-0 */
exynos_pinmux_config(PERIPH_ID_I2S0, 0);
/* Set EPLL Clock */
ret = set_epll_clk(pi2s_tx->samplingrate * pi2s_tx->rfs * 4);
} else if (pi2s_tx->id == 1) {
/* Initialize GPIO for I2S-1 */
exynos_pinmux_config(PERIPH_ID_I2S1, 0);
/* Set EPLL Clock */
ret = set_epll_clk(pi2s_tx->audio_pll_clk);
} else {
debug("%s: unsupported i2s-%d bus\n", __func__, pi2s_tx->id);
return -ERANGE;
}
if (ret) {
debug("%s: epll clock set rate failed\n", __func__);
return ret;
}
/* Select Clk Source for Audio 0 or 1 */
ret = set_i2s_clk_source(pi2s_tx->id);
if (ret) {
debug("%s: unsupported clock for i2s-%d\n", __func__,
pi2s_tx->id);
return ret;
}
if (pi2s_tx->id == 0) {
/*Reset the i2s module */
writel(CON_RESET, &i2s_reg->con);
writel(MOD_OP_CLK | MOD_RCLKSRC, &i2s_reg->mod);
/* set i2s prescaler */
writel(PSREN | PSVAL, &i2s_reg->psr);
} else {
/* Set Prescaler to get MCLK */
ret = set_i2s_clk_prescaler(pi2s_tx->audio_pll_clk,
(pi2s_tx->samplingrate * (pi2s_tx->rfs)),
pi2s_tx->id);
}
if (ret) {
debug("%s: unsupported prescalar for i2s-%d\n", __func__,
pi2s_tx->id);
return ret;
}
/* Configure I2s format */
ret = i2s_set_fmt(i2s_reg, SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM);
if (ret == 0) {
i2s_set_lr_framesize(i2s_reg, pi2s_tx->rfs);
ret = i2s_set_samplesize(i2s_reg, pi2s_tx->bitspersample);
if (ret != 0) {
debug("%s:set sample rate failed\n", __func__);
return ret;
}
i2s_set_bitclk_framesize(i2s_reg, pi2s_tx->bfs);
/* disable i2s transfer flag and flush the fifo */
i2s_txctrl(i2s_reg, I2S_TX_OFF);
i2s_fifo(i2s_reg, FIC_TXFLUSH);
} else {
debug("%s: failed\n", __func__);
}
return ret;
}
