/**
* \brief Callback function for PDCA interrupt.
*/
static void pdca_transfer_done(enum pdca_channel_status status)
{
if (status == PDCA_CH_TRANSFER_COMPLETED) {
pdca_channel_write_load(CONFIG_ADC_PDCA_RX_CHANNEL,
g_adc_sample_data, 2);
pdca_channel_write_load(CONFIG_ADC_PDCA_TX_CHANNEL,
g_adc_cdma_first_cfg, 2);
pdca_channel_disable_interrupt(CONFIG_ADC_PDCA_RX_CHANNEL,
PDCA_IER_TRC);
pdca_channel_disable_interrupt(CONFIG_ADC_PDCA_TX_CHANNEL,
PDCA_IER_TRC);
}
}
/**
* \brief Interrupt handler for PDCA interrupt.
*/
static void PDCA_TX_Handler(enum pdca_channel_status status)
{
/* Check if PDCA transfer complete */
if (status == PDCA_CH_TRANSFER_COMPLETED) {
/* Transmit continuously. */
g_state = TRANSMITTED;
pdca_channel_disable_interrupt(PDCA_TX_CHANNEL, PDCA_IER_TRC);
}
}
/**
* \brief Interrupt handler for PDCA interrupt.
*/
static void PDCA_RX_Handler(enum pdca_channel_status status)
{
/* Check if PDCA transfer complete */
if (status == PDCA_CH_TRANSFER_COMPLETED) {
/* Indicate receiving finished. */
g_state = RECEIVED;
pdca_channel_disable_interrupt(PDCA_RX_CHANNEL, PDCA_IER_TRC);
}
}
/**
* \brief The callback function for PDCA channel of PARC
*
* \param status PDCA channel status
*/
static void pdca_parc_callback(enum pdca_channel_status status)
{
UNUSED(status);
printf("End of capture.\r\n");
for (uint32_t uc_i = 0; uc_i < BUFFER_SIZE; uc_i++) {
printf("0x%02X ", gs_puc_buffer[uc_i]);
}
printf("\r\n");
/* disable interrupt for pdca channel of PARC*/
pdca_channel_disable_interrupt(PDCA_PARC_CHANNEL,PDCA_IER_RCZ);
pdca_channel_disable(PDCA_PARC_CHANNEL);
puts("\n\rThe example is done!\n\r");
}
/**
* \brief Start ADC sample.
* Initialize ADC, set clock and timing, and set ADC to given mode.
*/
static void start_adc(void)
{
struct adc_config adc_cfg = {
/* System clock division factor is 16 */
.prescal = ADC_PRESCAL_DIV16,
/* The APB clock is used */
.clksel = ADC_CLKSEL_APBCLK,
/* Max speed is 150K */
.speed = ADC_SPEED_150K,
/* ADC Reference voltage is 0.625*VCC */
.refsel = ADC_REFSEL_1,
/* Enables the Startup time */
.start_up = CONFIG_ADC_STARTUP
};
struct adc_seq_config adc_seq_cfg = {
/* Select Vref for shift cycle */
.zoomrange = ADC_ZOOMRANGE_0,
/* Pad Ground */
.muxneg = ADC_MUXNEG_1,
/* DAC internal */
.muxpos = ADC_MUXPOS_3,
/* Enables the internal voltage sources */
.internal = ADC_INTERNAL_3,
/* Disables the ADC gain error reduction */
.gcomp = ADC_GCOMP_DIS,
/* Disables the HWLA mode */
.hwla = ADC_HWLA_DIS,
/* 12-bits resolution */
.res = ADC_RES_12_BIT,
/* Enables the single-ended mode */
.bipolar = ADC_BIPOLAR_SINGLEENDED
};
struct adc_ch_config adc_ch_cfg = {
.seq_cfg = &adc_seq_cfg,
/* Internal Timer Max Counter */
.internal_timer_max_count = 60,
/* Window monitor mode is off */
.window_mode = 0,
.low_threshold = 0,
.high_threshold = 0,
};
if(adc_init(&g_adc_inst, ADCIFE, &adc_cfg) != STATUS_OK) {
puts("-F- ADC Init Fail!\n\r");
while(1);
}
if(adc_enable(&g_adc_inst) != STATUS_OK) {
puts("-F- ADC Enable Fail!\n\r");
while(1);
}
if (g_adc_test_mode.uc_pdc_en) {
adc_disable_interrupt(&g_adc_inst, ADC_SEQ_SEOC);
adc_pdca_set_config(&g_adc_pdca_cfg);
pdca_channel_set_callback(CONFIG_ADC_PDCA_RX_CHANNEL, pdca_transfer_done,
PDCA_0_IRQn, 1, PDCA_IER_TRC);
} else {
pdca_channel_disable_interrupt(CONFIG_ADC_PDCA_RX_CHANNEL,
PDCA_IDR_TRC);
pdca_channel_disable_interrupt(CONFIG_ADC_PDCA_TX_CHANNEL,
PDCA_IDR_TRC);
adc_ch_set_config(&g_adc_inst, &adc_ch_cfg);
adc_set_callback(&g_adc_inst, ADC_SEQ_SEOC, adcife_read_conv_result,
ADCIFE_IRQn, 1);
}
/* Configure trigger mode and start convention. */
switch (g_adc_test_mode.uc_trigger_mode) {
case TRIGGER_MODE_SOFTWARE:
adc_configure_trigger(&g_adc_inst, ADC_TRIG_SW);
break;
case TRIGGER_MODE_CON:
adc_configure_trigger(&g_adc_inst, ADC_TRIG_CON);
break;
case TRIGGER_MODE_ITIMER:
adc_configure_trigger(&g_adc_inst, ADC_TRIG_INTL_TIMER);
adc_configure_itimer_period(&g_adc_inst,
adc_ch_cfg.internal_timer_max_count);
adc_start_itimer(&g_adc_inst);
break;
default:
break;
}
if (g_adc_test_mode.uc_gain_en) {
adc_configure_gain(&g_adc_inst, ADC_GAIN_2X);
} else {
adc_configure_gain(&g_adc_inst, ADC_GAIN_1X);
}
}
/**
* \brief Start DAC ouput.
* Initialize DAC, set clock and timing, and set DAC to given mode.
*/
static void start_dac(void)
{
sysclk_enable_peripheral_clock(DACC);
/* Reset DACC registers */
dacc_reset(DACC);
/* Half word transfer mode */
dacc_set_transfer_mode(DACC, 0);
/* Timing:
* startup - 0x10 (17 clocks)
* internal trigger clock - 0x60 (96 clocks)
*/
dacc_set_timing(DACC, 0x10, 0x60);
/* Enable DAC */
dacc_enable(DACC);
/* The DAC is 10-bit resolution, so output voltage should be
* (3300 * 255) / ((1 << 10) - 1) = 823mv */
dacc_write_conversion_data(DACC, 0xFF);
}
