static int load_som_binary(struct linux_binprm * bprm, struct pt_regs * regs) { int som_exec_fileno; int retval; unsigned int size; unsigned long som_entry; struct som_hdr *som_ex; struct som_exec_auxhdr *hpuxhdr; struct files_struct *files; /* Get the exec-header */ som_ex = (struct som_hdr *) bprm->buf; retval = check_som_header(som_ex); if (retval != 0) goto out; /* Now read in the auxiliary header information */ retval = -ENOMEM; size = som_ex->aux_header_size; if (size > SOM_PAGESIZE) goto out; hpuxhdr = kmalloc(size, GFP_KERNEL); if (!hpuxhdr) goto out; retval = kernel_read(bprm->file, som_ex->aux_header_location, (char *) hpuxhdr, size); if (retval != size) { if (retval >= 0) retval = -EIO; goto out_free; } files = current->files; /* Refcounted so ok */ retval = unshare_files(); if (retval < 0) goto out_free; if (files == current->files) { put_files_struct(files); files = NULL; } retval = get_unused_fd(); if (retval < 0) goto out_free; get_file(bprm->file); fd_install(som_exec_fileno = retval, bprm->file); /* Flush all traces of the currently running executable */ retval = flush_old_exec(bprm); if (retval) goto out_free; /* OK, This is the point of no return */ current->flags &= ~PF_FORKNOEXEC; current->personality = PER_HPUX; setup_new_exec(bprm); /* Set the task size for HP-UX processes such that * the gateway page is outside the address space. * This can be fixed later, but for now, this is much * easier. */ current->thread.task_size = 0xc0000000; /* Set map base to allow enough room for hp-ux heap growth */ current->thread.map_base = 0x80000000; retval = map_som_binary(bprm->file, hpuxhdr); if (retval < 0) goto out_free; som_entry = hpuxhdr->exec_entry; kfree(hpuxhdr); set_binfmt(&som_format); compute_creds(bprm); setup_arg_pages(bprm, STACK_TOP, EXSTACK_DEFAULT); create_som_tables(bprm); current->mm->start_stack = bprm->p; #if 0 printk("(start_brk) %08lx\n" , (unsigned long) current->mm->start_brk); printk("(end_code) %08lx\n" , (unsigned long) current->mm->end_code); printk("(start_code) %08lx\n" , (unsigned long) current->mm->start_code); printk("(end_data) %08lx\n" , (unsigned long) current->mm->end_data); printk("(start_stack) %08lx\n" , (unsigned long) current->mm->start_stack); printk("(brk) %08lx\n" , (unsigned long) current->mm->brk); #endif map_hpux_gateway_page(current,current->mm); start_thread_som(regs, som_entry, bprm->p); if (current->ptrace & PT_PTRACED) send_sig(SIGTRAP, current, 0); return 0; /* error cleanup */ out_free: kfree(hpuxhdr); out: return retval; }
static void handle_breakpoint(trapframe_t* tf) { dump_tf(tf); printk("Breakpoint!\n"); tf->epc += 4; }
/* Hardware start transmission. Send a packet to media from the upper layer. */ static int dmfe_start_xmit(struct sk_buff *skb, struct net_device *dev) { board_info_t *db = netdev_priv(dev); char * data_ptr; int i, tmplen; u16 MDWAH, MDWAL; #ifdef TDBUG /* check TX FIFO pointer */ u16 MDWAH1, MDWAL1; u16 tx_ptr; #endif DMFE_DBUG(0, "dmfe_start_xmit", 0); if (db->chip_revision != 0x1A) { if(db->Speed == 10) {if (db->tx_pkt_cnt >= 1) return 1;} else {if (db->tx_pkt_cnt >= 2) return 1;} }else if (db->tx_pkt_cnt >= 2) return 1; /* packet counting */ db->tx_pkt_cnt++; db->stats.tx_packets++; db->stats.tx_bytes+=skb->len; if (db->chip_revision != 0x1A) { if (db->Speed == 10) {if (db->tx_pkt_cnt >= 1) netif_stop_queue(dev);} else {if (db->tx_pkt_cnt >= 2) netif_stop_queue(dev);} }else if (db->tx_pkt_cnt >= 2) netif_stop_queue(dev); /* Disable all interrupt */ iow(db, DM9KS_IMR, DM9KS_DISINTR); MDWAH = ior(db,DM9KS_MDWAH); MDWAL = ior(db,DM9KS_MDWAL); /* Set TX length to reg. 0xfc & 0xfd */ iow(db, DM9KS_TXPLL, (skb->len & 0xff)); iow(db, DM9KS_TXPLH, (skb->len >> 8) & 0xff); /* Move data to TX SRAM */ data_ptr = (char *)skb->data; outb(DM9KS_MWCMD, db->io_addr); // Write data into SRAM trigger switch(db->io_mode) { case DM9KS_BYTE_MODE: for (i = 0; i < skb->len; i++) outb((data_ptr[i] & 0xff), db->io_data); break; case DM9KS_WORD_MODE: tmplen = (skb->len + 1) / 2; for (i = 0; i < tmplen; i++) outw(((u16 *)data_ptr)[i], db->io_data); break; case DM9KS_DWORD_MODE: tmplen = (skb->len + 3) / 4; for (i = 0; i< tmplen; i++) outl(((u32 *)data_ptr)[i], db->io_data); break; } #ifndef ETRANS /* Issue TX polling command */ iow(db, DM9KS_TCR, 0x1); /* Cleared after TX complete*/ #endif #ifdef TDBUG /* check TX FIFO pointer */ MDWAH1 = ior(db,DM9KS_MDWAH); MDWAL1 = ior(db,DM9KS_MDWAL); tx_ptr = (MDWAH<<8)|MDWAL; switch (db->io_mode) { case DM9KS_BYTE_MODE: tx_ptr += skb->len; break; case DM9KS_WORD_MODE: tx_ptr += ((skb->len + 1) / 2)*2; break; case DM9KS_DWORD_MODE: tx_ptr += ((skb->len+3)/4)*4; break; } if (tx_ptr > 0x0bff) tx_ptr -= 0x0c00; if (tx_ptr != ((MDWAH1<<8)|MDWAL1)) printk("[dm9ks:TX FIFO ERROR\n"); #endif /* Saved the time stamp */ dev->trans_start = jiffies; db->cont_rx_pkt_cnt =0; /* Free this SKB */ dev_kfree_skb(skb); /* Re-enable interrupt */ iow(db, DM9KS_IMR, DM9KS_REGFF); return 0; }
// led timer expire kicks in about ~100ms and perform the led operation according to the ledState and // restart the timer according to ledState static void ledTimerExpire(void) { int i; PLED_CTRL pCurLed; unsigned long flags; gTimerOn = FALSE; for (i = 0, pCurLed = gLedCtrl; i < kLedEnd; i++, pCurLed++) { #if defined(DEBUG_LED) printk("led[%d]: Mask=0x%04x, State = %d, blcd=%d\n", i, pCurLed->ledGreenGpio, pCurLed->ledState, pCurLed->blinkCountDown); #endif spin_lock_irqsave(&brcm_ledlock, flags); // LEDs can be changed from ISR switch (pCurLed->ledState) { case kLedStateOn: case kLedStateOff: case kLedStateFail: pCurLed->blinkCountDown = 0; // reset the blink count down spin_unlock_irqrestore(&brcm_ledlock, flags); break; case kLedStateSlowBlinkContinues: if (pCurLed->blinkCountDown-- == 0) { pCurLed->blinkCountDown = kSlowBlinkCount; ledToggle(pCurLed); } spin_unlock_irqrestore(&brcm_ledlock, flags); ledTimerStart(); break; case kLedStateFastBlinkContinues: if (pCurLed->blinkCountDown-- == 0) { pCurLed->blinkCountDown = kFastBlinkCount; ledToggle(pCurLed); } spin_unlock_irqrestore(&brcm_ledlock, flags); ledTimerStart(); break; case kLedStateUserWpsInProgress: /* 200ms on, 100ms off */ if (pCurLed->blinkCountDown-- == 0) { pCurLed->blinkCountDown = (((gLedRunningCounter++)&1)? kFastBlinkCount: kSlowBlinkCount); ledToggle(pCurLed); } spin_unlock_irqrestore(&brcm_ledlock, flags); ledTimerStart(); break; case kLedStateUserWpsError: /* 100ms on, 100ms off */ if (pCurLed->blinkCountDown-- == 0) { pCurLed->blinkCountDown = kFastBlinkCount; ledToggle(pCurLed); } spin_unlock_irqrestore(&brcm_ledlock, flags); ledTimerStart(); break; case kLedStateUserWpsSessionOverLap: /* 100ms on, 100ms off, 5 times, off for 500ms */ if (pCurLed->blinkCountDown-- == 0) { if(((++gLedRunningCounter)%10) == 0) { pCurLed->blinkCountDown = 4; setLed(pCurLed, kLedOff, kLedGreen); pCurLed->ledState = kLedStateUserWpsSessionOverLap; } else { pCurLed->blinkCountDown = kFastBlinkCount; ledToggle(pCurLed); } } spin_unlock_irqrestore(&brcm_ledlock, flags); ledTimerStart(); break; default: spin_unlock_irqrestore(&brcm_ledlock, flags); printk("Invalid state = %d\n", pCurLed->ledState); } } }
void * pcibr_bus_fixup(struct pcibus_bussoft *prom_bussoft, struct pci_controller *controller) { int nasid, cnode, j; struct hubdev_info *hubdev_info; struct pcibus_info *soft; struct sn_flush_device_kernel *sn_flush_device_kernel; struct sn_flush_device_common *common; if (! IS_PCI_BRIDGE_ASIC(prom_bussoft->bs_asic_type)) { return NULL; } /* * Allocate kernel bus soft and copy from prom. */ soft = kmemdup(prom_bussoft, sizeof(struct pcibus_info), GFP_KERNEL); if (!soft) { return NULL; } soft->pbi_buscommon.bs_base = (unsigned long) ioremap(REGION_OFFSET(soft->pbi_buscommon.bs_base), sizeof(struct pic)); spin_lock_init(&soft->pbi_lock); /* * register the bridge's error interrupt handler */ if (request_irq(SGI_PCIASIC_ERROR, pcibr_error_intr_handler, IRQF_SHARED, "PCIBR error", (void *)(soft))) { printk(KERN_WARNING "pcibr cannot allocate interrupt for error handler\n"); } sn_set_err_irq_affinity(SGI_PCIASIC_ERROR); /* * Update the Bridge with the "kernel" pagesize */ if (PAGE_SIZE < 16384) { pcireg_control_bit_clr(soft, PCIBR_CTRL_PAGE_SIZE); } else { pcireg_control_bit_set(soft, PCIBR_CTRL_PAGE_SIZE); } nasid = NASID_GET(soft->pbi_buscommon.bs_base); cnode = nasid_to_cnodeid(nasid); hubdev_info = (struct hubdev_info *)(NODEPDA(cnode)->pdinfo); if (hubdev_info->hdi_flush_nasid_list.widget_p) { sn_flush_device_kernel = hubdev_info->hdi_flush_nasid_list. widget_p[(int)soft->pbi_buscommon.bs_xid]; if (sn_flush_device_kernel) { for (j = 0; j < DEV_PER_WIDGET; j++, sn_flush_device_kernel++) { common = sn_flush_device_kernel->common; if (common->sfdl_slot == -1) continue; if ((common->sfdl_persistent_segment == soft->pbi_buscommon.bs_persist_segment) && (common->sfdl_persistent_busnum == soft->pbi_buscommon.bs_persist_busnum)) common->sfdl_pcibus_info = soft; } } } /* Setup the PMU ATE map */ soft->pbi_int_ate_resource.lowest_free_index = 0; soft->pbi_int_ate_resource.ate = kzalloc(soft->pbi_int_ate_size * sizeof(u64), GFP_KERNEL); if (!soft->pbi_int_ate_resource.ate) { kfree(soft); return NULL; } return soft; }
int __init dmfe_probe1(struct net_device *dev) { struct board_info *db; /* Point a board information structure */ u32 id_val; u16 i, dm9000_found = FALSE; u8 MAC_addr[6]={0x00,0x60,0x6E,0x33,0x44,0x55}; u8 HasEEPROM=0,chip_info; DMFE_DBUG(0, "dmfe_probe1()",0); /* Search All DM9000 serial NIC */ do { outb(DM9KS_VID_L, iobase); /* DM9000C的索引寄存器(cmd引脚为0) */ id_val = inb(iobase + 4); /* 读DM9000C的数据寄存器(cmd引脚为1) */ outb(DM9KS_VID_H, iobase); id_val |= inb(iobase + 4) << 8; outb(DM9KS_PID_L, iobase); id_val |= inb(iobase + 4) << 16; outb(DM9KS_PID_H, iobase); id_val |= inb(iobase + 4) << 24; if (id_val == DM9KS_ID || id_val == DM9010_ID) { /* Request IO from system */ if(!request_region(iobase, 2, dev->name)) return -ENODEV; printk(KERN_ERR"<DM9KS> I/O: %x, VID: %x \n",iobase, id_val); dm9000_found = TRUE; /* Allocated board information structure */ db = netdev_priv(dev); memset(db, 0, sizeof(struct board_info)); dmfe_dev = dev; db->io_addr = iobase; db->io_data = iobase + 4; db->chip_revision = ior(db, DM9KS_CHIPR); chip_info = ior(db,0x43); /* [email protected] */ //if((db->chip_revision!=0x1A) || ((chip_info&(1<<5))!=0) || ((chip_info&(1<<2))!=1)) return -ENODEV; /* driver system function */ dev->netdev_ops = &dm9k_netdev_ops; dev->base_addr = iobase; dev->irq = irq; //dev->open = &dmfe_open; //dev->hard_start_xmit = &dmfe_start_xmit; dev->watchdog_timeo = 5*HZ; //dev->tx_timeout = dmfe_timeout; //dev->stop = &dmfe_stop; //dev->get_stats = &dmfe_get_stats; //dev->set_multicast_list = &dm9000_hash_table; //dev->do_ioctl = &dmfe_do_ioctl; #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,28) dev->ethtool_ops = &dmfe_ethtool_ops; #endif #ifdef CHECKSUM //dev->features |= NETIF_F_IP_CSUM; dev->features |= NETIF_F_IP_CSUM|NETIF_F_SG; #endif db->mii.dev = dev; db->mii.mdio_read = mdio_read; db->mii.mdio_write = mdio_write; db->mii.phy_id = 1; #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) db->mii.phy_id_mask = 0x1F; db->mii.reg_num_mask = 0x1F; #endif //db->msg_enable =(debug == 0 ? DMFE_DEF_MSG_ENABLE : ((1 << debug) - 1)); /* Read SROM content */ for (i=0; i<64; i++) ((u16 *)db->srom)[i] = read_srom_word(db, i); /* Get the PID and VID from EEPROM to check */ id_val = (((u16 *)db->srom)[4])|(((u16 *)db->srom)[5]<<16); printk("id_val=%x\n", id_val); if (id_val == DM9KS_ID || id_val == DM9010_ID) HasEEPROM =1; /* Set Node Address */ for (i=0; i<6; i++) { if (HasEEPROM) /* use EEPROM */ dev->dev_addr[i] = db->srom[i]; else /* No EEPROM */ dev->dev_addr[i] = MAC_addr[i]; } }//end of if() iobase += 0x10; }while(!dm9000_found && iobase <= DM9KS_MAX_IO); return dm9000_found ? 0:-ENODEV; }
static void omap_stop_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) { unsigned long timeout = jiffies + msecs_to_jiffies(100); dev_dbg(omap->dev, "stopping TI EHCI USB Controller\n"); printk(KERN_DEBUG " omap_stop_ehc\n"); /* Reset OMAP modules for insmod/rmmod to work */ ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, OMAP_UHH_SYSCONFIG_SOFTRESET); while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) & (1 << 0))) { cpu_relax(); if (time_after(jiffies, timeout)) dev_dbg(omap->dev, "operation timed out\n"); } while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) & (1 << 1))) { cpu_relax(); if (time_after(jiffies, timeout)) dev_dbg(omap->dev, "operation timed out\n"); } while (!(ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSSTATUS) & (1 << 2))) { cpu_relax(); if (time_after(jiffies, timeout)) dev_dbg(omap->dev, "operation timed out\n"); } ehci_omap_clock_power(omap, 0); if (omap->usbtll_fck != NULL) { clk_put(omap->usbtll_fck); omap->usbtll_fck = NULL; } if (omap->usbhost_ick != NULL) { clk_put(omap->usbhost_ick); omap->usbhost_ick = NULL; } if (omap->usbhost1_48m_fck != NULL) { clk_put(omap->usbhost1_48m_fck); omap->usbhost1_48m_fck = NULL; } if (omap->usbhost2_120m_fck != NULL) { clk_put(omap->usbhost2_120m_fck); omap->usbhost2_120m_fck = NULL; } if (omap->usbtll_ick != NULL) { clk_put(omap->usbtll_ick); omap->usbtll_ick = NULL; } if (omap->phy_reset) { printk(KERN_DEBUG " free the reset the GPIOs\n"); if (gpio_is_valid(omap->reset_gpio_port[0])) gpio_free(omap->reset_gpio_port[0]); if (gpio_is_valid(omap->reset_gpio_port[1])) gpio_free(omap->reset_gpio_port[1]); } dev_dbg(omap->dev, "Clock to USB host has been disabled\n"); gpio_direction_output(23, 0); PHY_reset = 0; #ifndef CONFIG_MODEM_SMS if(!modem_resume_state || !g_sim_carddetect_status){ gpio_direction_output(21, 0); gpio_direction_output(35, 0); gpio_direction_output(36, 0); modem_PW = 0; } #endif }
static void hydra_reset_8390(struct net_device *dev) { printk(KERN_INFO "Hydra hw reset not there\n"); }
static irqreturn_t s3c2410_dma_irq(int irq, void *devpw) { struct s3c2410_dma_chan *chan = (struct s3c2410_dma_chan *)devpw; struct s3c2410_dma_buf *buf; buf = chan->curr; dbg_showchan(chan); /* modify the channel state */ switch (chan->load_state) { case S3C2410_DMALOAD_1RUNNING: /* TODO - if we are running only one buffer, we probably * want to reload here, and then worry about the buffer * callback */ chan->load_state = S3C2410_DMALOAD_NONE; break; case S3C2410_DMALOAD_1LOADED: /* iirc, we should go back to NONE loaded here, we * had a buffer, and it was never verified as being * loaded. */ chan->load_state = S3C2410_DMALOAD_NONE; break; case S3C2410_DMALOAD_1LOADED_1RUNNING: /* we'll worry about checking to see if another buffer is * ready after we've called back the owner. This should * ensure we do not wait around too long for the DMA * engine to start the next transfer */ chan->load_state = S3C2410_DMALOAD_1LOADED; break; case S3C2410_DMALOAD_NONE: printk(KERN_ERR "dma%d: IRQ with no loaded buffer?\n", chan->number); break; default: printk(KERN_ERR "dma%d: IRQ in invalid load_state %d\n", chan->number, chan->load_state); break; } if (buf != NULL) { /* update the chain to make sure that if we load any more * buffers when we call the callback function, things should * work properly */ chan->curr = buf->next; buf->next = NULL; if (buf->magic != BUF_MAGIC) { printk(KERN_ERR "dma%d: %s: buf %p incorrect magic\n", chan->number, __FUNCTION__, buf); return IRQ_HANDLED; } s3c2410_dma_buffdone(chan, buf, S3C2410_RES_OK); /* free resouces */ s3c2410_dma_freebuf(buf); } else { } /* only reload if the channel is still running... our buffer done * routine may have altered the state by requesting the dma channel * to stop or shutdown... */ /* todo: check that when the channel is shut-down from inside this * function, we cope with unsetting reload, etc */ if (chan->next != NULL && chan->state != S3C2410_DMA_IDLE) { unsigned long flags; switch (chan->load_state) { case S3C2410_DMALOAD_1RUNNING: /* don't need to do anything for this state */ break; case S3C2410_DMALOAD_NONE: /* can load buffer immediately */ break; case S3C2410_DMALOAD_1LOADED: if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { /* flag error? */ printk(KERN_ERR "dma%d: timeout waiting for load (%s)\n", chan->number, __FUNCTION__); return IRQ_HANDLED; } break; case S3C2410_DMALOAD_1LOADED_1RUNNING: goto no_load; default: printk(KERN_ERR "dma%d: unknown load_state in irq, %d\n", chan->number, chan->load_state); return IRQ_HANDLED; } local_irq_save(flags); s3c2410_dma_loadbuffer(chan, chan->next); local_irq_restore(flags); } else { s3c2410_dma_lastxfer(chan); /* see if we can stop this channel.. */ if (chan->load_state == S3C2410_DMALOAD_NONE) { pr_debug("dma%d: end of transfer, stopping channel (%ld)\n", chan->number, jiffies); s3c2410_dma_ctrl(chan->number | DMACH_LOW_LEVEL, S3C2410_DMAOP_STOP); } } no_load: return IRQ_HANDLED; }
/* omap_start_ehc * - Start the TI USBHOST controller */ static int omap_start_ehc(struct ehci_hcd_omap *omap, struct usb_hcd *hcd) { unsigned long timeout = jiffies + msecs_to_jiffies(1000); u8 tll_ch_mask = 0; unsigned reg = 0; int ret = 0; printk("omap_start_ehc kernel 2.6.35 V0.7 [09/02/2011] \n"); gpio_direction_output(23, 0); PHY_reset = 0; #ifndef CONFIG_MODEM_SMS gpio_direction_output(21, 1); gpio_direction_output(35, 1); gpio_direction_output(36, 1); EP10_HW_ID=ep_get_hardware_id(); if(EP10_HW_ID==BOARD_VERSION_UNKNOWN) { EP10_HW_ID = BOARD_ID_DVT1 ; } if(EP10_HW_ID>=BOARD_ID_DVT1) { gpio_direction_output(109, 1); //printk("GPIO-109 enabled \n"); } //printk("HW-ver= %d\n",EP10_HW_ID); modem_PW = 1; #endif dev_dbg(omap->dev, "starting TI EHCI USB Controller\n"); /* Get all the clock handles we need */ omap->usbhost_ick = clk_get(omap->dev, "usbhost_ick"); if (IS_ERR(omap->usbhost_ick)) { dev_err(omap->dev, "could not get usbhost_ick\n"); ret = PTR_ERR(omap->usbhost_ick); goto err_host_ick; } omap->usbhost2_120m_fck = clk_get(omap->dev, "usbhost_120m_fck"); if (IS_ERR(omap->usbhost2_120m_fck)) { dev_err(omap->dev, "could not get usbhost2_120m_fck\n"); ret = PTR_ERR(omap->usbhost2_120m_fck); goto err_host_120m_fck; } omap->usbhost1_48m_fck = clk_get(omap->dev, "usbhost_48m_fck"); if (IS_ERR(omap->usbhost1_48m_fck)) { dev_err(omap->dev, "could not get usbhost_48m_fck\n"); ret = PTR_ERR(omap->usbhost1_48m_fck); goto err_host_48m_fck; } if (omap->phy_reset) { printk(KERN_DEBUG "reset the phys\n"); /* Refer: ISSUE1 */ if (gpio_is_valid(omap->reset_gpio_port[0])) { gpio_request(omap->reset_gpio_port[0], "USB1 PHY reset"); gpio_direction_output(omap->reset_gpio_port[0], 0); } if (gpio_is_valid(omap->reset_gpio_port[1])) { gpio_request(omap->reset_gpio_port[1],"USB2 PHY reset"); gpio_direction_output(omap->reset_gpio_port[1], 0); } /* Hold the PHY in RESET for enough time till DIR is high */ udelay(10); } omap->usbtll_fck = clk_get(omap->dev, "usbtll_fck"); if (IS_ERR(omap->usbtll_fck)) { dev_err(omap->dev, "could not get usbtll_fck\n"); ret = PTR_ERR(omap->usbtll_fck); goto err_tll_fck; } omap->usbtll_ick = clk_get(omap->dev, "usbtll_ick"); if (IS_ERR(omap->usbtll_ick)) { dev_err(omap->dev, "could not get usbtll_ick\n"); ret = PTR_ERR(omap->usbtll_ick); goto err_tll_ick; } /* Now enable all the clocks in the correct order */ ehci_omap_clock_power(omap, 1); /* Put UHH in NoIdle/NoStandby mode */ reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_SYSCONFIG); reg |= OMAP_UHH_SYSCONFIG_CACTIVITY | OMAP_UHH_SYSCONFIG_AUTOIDLE | OMAP_UHH_SYSCONFIG_ENAWAKEUP; reg &= ~(OMAP_UHH_SYSCONFIG_SIDLEMASK | OMAP_UHH_SYSCONFIG_MIDLEMASK); reg |= OMAP_UHH_SYSCONFIG_NOIDLE | OMAP_UHH_SYSCONFIG_NOSTDBY; ehci_omap_writel(omap->uhh_base, OMAP_UHH_SYSCONFIG, reg); reg = ehci_omap_readl(omap->uhh_base, OMAP_UHH_HOSTCONFIG); /* setup ULPI bypass and burst configurations */ reg |= (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN); reg &= ~OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN; if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_UNKNOWN) reg &= ~OMAP_UHH_HOSTCONFIG_P1_CONNECT_STATUS; if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_UNKNOWN) reg &= ~OMAP_UHH_HOSTCONFIG_P2_CONNECT_STATUS; if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_UNKNOWN) reg &= ~OMAP_UHH_HOSTCONFIG_P3_CONNECT_STATUS; /* Bypass the TLL module for PHY mode operation */ if (cpu_is_omap3430() && (omap_rev() <= OMAP3430_REV_ES2_1)) { dev_dbg(omap->dev, "OMAP3 ES version <= ES2.1\n"); if ((omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) || (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) || (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY)) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; else reg |= OMAP_UHH_HOSTCONFIG_ULPI_BYPASS; } else { dev_dbg(omap->dev, "OMAP3 ES version > ES2.1\n"); if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_PHY) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; else if (omap->port_mode[0] == EHCI_HCD_OMAP_MODE_TLL) reg |= OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS; if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_PHY) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; else if (omap->port_mode[1] == EHCI_HCD_OMAP_MODE_TLL) reg |= OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS; if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_PHY) reg &= ~OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; else if (omap->port_mode[2] == EHCI_HCD_OMAP_MODE_TLL) reg |= OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS; } ehci_omap_writel(omap->uhh_base, OMAP_UHH_HOSTCONFIG, reg); dev_dbg(omap->dev, "UHH setup done, uhh_hostconfig=%x\n", reg); /* * An undocumented "feature" in the OMAP3 EHCI controller, * causes suspended ports to be taken out of suspend when * the USBCMD.Run/Stop bit is cleared (for example when * we do ehci_bus_suspend). * This breaks suspend-resume if the root-hub is allowed * to suspend. Writing 1 to this undocumented register bit * disables this feature and restores normal behavior. */ ehci_omap_writel(omap->ehci_base, EHCI_INSNREG04, EHCI_INSNREG04_DISABLE_UNSUSPEND); if (omap->phy_reset) { printk(KERN_DEBUG "unreset the phys\n"); /* Refer ISSUE1: * Hold the PHY in RESET for enough time till * PHY is settled and ready */ udelay(10); if (gpio_is_valid(omap->reset_gpio_port[0])) gpio_set_value(omap->reset_gpio_port[0], 1); if (gpio_is_valid(omap->reset_gpio_port[1])) gpio_set_value(omap->reset_gpio_port[1], 1); } //gpio_direction_output(21, 1); //gpio_direction_output(36, 1); //gpio_direction_output(35, 1); //msleep(10); printk("RESET USB PHY\n"); gpio_direction_output(23, 1); PHY_reset = 1; return 0; err_sys_status: ehci_omap_clock_power(omap, 0); clk_put(omap->usbtll_ick); err_tll_ick: clk_put(omap->usbtll_fck); err_tll_fck: clk_put(omap->usbhost1_48m_fck); if (omap->phy_reset) { if (gpio_is_valid(omap->reset_gpio_port[0])) gpio_free(omap->reset_gpio_port[0]); if (gpio_is_valid(omap->reset_gpio_port[1])) gpio_free(omap->reset_gpio_port[1]); } err_host_48m_fck: clk_put(omap->usbhost2_120m_fck); err_host_120m_fck: clk_put(omap->usbhost_ick); err_host_ick: return ret; }
int s3c2410_dma_enqueue(unsigned int channel, void *id, dma_addr_t data, int size) { struct s3c2410_dma_chan *chan = lookup_dma_channel(channel); struct s3c2410_dma_buf *buf; unsigned long flags; if (chan == NULL) return -EINVAL; pr_debug("%s: id=%p, data=%08x, size=%d\n", __FUNCTION__, id, (unsigned int)data, size); buf = kmem_cache_alloc(dma_kmem, GFP_ATOMIC); if (buf == NULL) { pr_debug("%s: out of memory (%ld alloc)\n", __FUNCTION__, (long)sizeof(*buf)); return -ENOMEM; } //pr_debug("%s: new buffer %p\n", __FUNCTION__, buf); //dbg_showchan(chan); buf->next = NULL; buf->data = buf->ptr = data; buf->size = size; buf->id = id; buf->magic = BUF_MAGIC; local_irq_save(flags); if (chan->curr == NULL) { /* we've got nothing loaded... */ pr_debug("%s: buffer %p queued onto empty channel\n", __FUNCTION__, buf); chan->curr = buf; chan->end = buf; chan->next = NULL; } else { pr_debug("dma%d: %s: buffer %p queued onto non-empty channel\n", chan->number, __FUNCTION__, buf); if (chan->end == NULL) pr_debug("dma%d: %s: %p not empty, and chan->end==NULL?\n", chan->number, __FUNCTION__, chan); chan->end->next = buf; chan->end = buf; } /* if necessary, update the next buffer field */ if (chan->next == NULL) chan->next = buf; /* check to see if we can load a buffer */ if (chan->state == S3C2410_DMA_RUNNING) { if (chan->load_state == S3C2410_DMALOAD_1LOADED && 1) { if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { printk(KERN_ERR "dma%d: loadbuffer:" "timeout loading buffer\n", chan->number); dbg_showchan(chan); local_irq_restore(flags); return -EINVAL; } } while (s3c2410_dma_canload(chan) && chan->next != NULL) { s3c2410_dma_loadbuffer(chan, chan->next); } } else if (chan->state == S3C2410_DMA_IDLE) { if (chan->flags & S3C2410_DMAF_AUTOSTART) { s3c2410_dma_ctrl(chan->number, S3C2410_DMAOP_START); } } local_irq_restore(flags); return 0; }
static int s3c2410_dma_start(struct s3c2410_dma_chan *chan) { unsigned long tmp; unsigned long flags; pr_debug("s3c2410_start_dma: channel=%d\n", chan->number); local_irq_save(flags); if (chan->state == S3C2410_DMA_RUNNING) { pr_debug("s3c2410_start_dma: already running (%d)\n", chan->state); local_irq_restore(flags); return 0; } chan->state = S3C2410_DMA_RUNNING; /* check wether there is anything to load, and if not, see * if we can find anything to load */ if (chan->load_state == S3C2410_DMALOAD_NONE) { if (chan->next == NULL) { printk(KERN_ERR "dma%d: channel has nothing loaded\n", chan->number); chan->state = S3C2410_DMA_IDLE; local_irq_restore(flags); return -EINVAL; } s3c2410_dma_loadbuffer(chan, chan->next); } dbg_showchan(chan); /* enable the channel */ if (!chan->irq_enabled) { enable_irq(chan->irq); chan->irq_enabled = 1; } /* start the channel going */ tmp = dma_rdreg(chan, S3C2410_DMA_DMASKTRIG); tmp &= ~S3C2410_DMASKTRIG_STOP; tmp |= S3C2410_DMASKTRIG_ON; dma_wrreg(chan, S3C2410_DMA_DMASKTRIG, tmp); pr_debug("dma%d: %08lx to DMASKTRIG\n", chan->number, tmp); #if 0 /* the dma buffer loads should take care of clearing the AUTO * reloading feature */ tmp = dma_rdreg(chan, S3C2410_DMA_DCON); tmp &= ~S3C2410_DCON_NORELOAD; dma_wrreg(chan, S3C2410_DMA_DCON, tmp); #endif s3c2410_dma_call_op(chan, S3C2410_DMAOP_START); dbg_showchan(chan); /* if we've only loaded one buffer onto the channel, then chec * to see if we have another, and if so, try and load it so when * the first buffer is finished, the new one will be loaded onto * the channel */ if (chan->next != NULL) { if (chan->load_state == S3C2410_DMALOAD_1LOADED) { if (s3c2410_dma_waitforload(chan, __LINE__) == 0) { pr_debug("%s: buff not yet loaded, no more todo\n", __FUNCTION__); } else { chan->load_state = S3C2410_DMALOAD_1RUNNING; s3c2410_dma_loadbuffer(chan, chan->next); } } else if (chan->load_state == S3C2410_DMALOAD_1RUNNING) { s3c2410_dma_loadbuffer(chan, chan->next); } } local_irq_restore(flags); return 0; }
static int __init s3c2410_init_dma(void) { struct s3c2410_dma_chan *cp; int channel; int ret; printk("S3C24XX DMA Driver, (c) 2003-2004,2006 Simtec Electronics\n"); dma_base = ioremap(S3C24XX_PA_DMA, 0x200); if (dma_base == NULL) { printk(KERN_ERR "dma failed to remap register block\n"); return -ENOMEM; } printk("Registering sysclass\n"); ret = sysdev_class_register(&dma_sysclass); if (ret != 0) { printk(KERN_ERR "dma sysclass registration failed\n"); goto err; } dma_kmem = kmem_cache_create("dma_desc", sizeof(struct s3c2410_dma_buf), 0, SLAB_HWCACHE_ALIGN, s3c2410_dma_cache_ctor, NULL); if (dma_kmem == NULL) { printk(KERN_ERR "dma failed to make kmem cache\n"); ret = -ENOMEM; goto err; } for (channel = 0; channel < S3C2410_DMA_CHANNELS; channel++) { cp = &s3c2410_chans[channel]; memset(cp, 0, sizeof(struct s3c2410_dma_chan)); /* dma channel irqs are in order.. */ cp->number = channel; cp->irq = channel + IRQ_DMA0; cp->regs = dma_base + (channel*0x40); /* point current stats somewhere */ cp->stats = &cp->stats_store; cp->stats_store.timeout_shortest = LONG_MAX; /* basic channel configuration */ cp->load_timeout = 1<<18; /* register system device */ cp->dev.cls = &dma_sysclass; cp->dev.id = channel; ret = sysdev_register(&cp->dev); printk("DMA channel %d at %p, irq %d\n", cp->number, cp->regs, cp->irq); } return 0; err: kmem_cache_destroy(dma_kmem); iounmap(dma_base); dma_base = NULL; return ret; }
static int parse_afs_partitions(struct mtd_info *mtd, struct mtd_partition **pparts, unsigned long origin) { struct mtd_partition *parts; u_int mask, off, idx, sz; int ret = 0; char *str; /* * This is the address mask; we use this to mask off out of * range address bits. */ mask = mtd->size - 1; /* * First, calculate the size of the array we need for the * partition information. We include in this the size of * the strings. */ for (idx = off = sz = 0; off < mtd->size; off += mtd->erasesize) { struct image_info_struct iis; u_int iis_ptr, img_ptr; ret = afs_read_footer(mtd, &img_ptr, &iis_ptr, off, mask); if (ret < 0) break; if (ret == 0) continue; ret = afs_read_iis(mtd, &iis, iis_ptr); if (ret < 0) break; if (ret == 0) continue; sz += sizeof(struct mtd_partition); sz += strlen(iis.name) + 1; idx += 1; } if (!sz) return ret; parts = kmalloc(sz, GFP_KERNEL); if (!parts) return -ENOMEM; memset(parts, 0, sz); str = (char *)(parts + idx); /* * Identify the partitions */ for (idx = off = 0; off < mtd->size; off += mtd->erasesize) { struct image_info_struct iis; u_int iis_ptr, img_ptr, size; /* Read the footer. */ ret = afs_read_footer(mtd, &img_ptr, &iis_ptr, off, mask); if (ret < 0) break; if (ret == 0) continue; /* Read the image info block */ ret = afs_read_iis(mtd, &iis, iis_ptr); if (ret < 0) break; if (ret == 0) continue; strcpy(str, iis.name); size = mtd->erasesize + off - img_ptr; /* * In order to support JFFS2 partitions on this layout, * we must lie to MTD about the real size of JFFS2 * partitions; this ensures that the AFS flash footer * won't be erased by JFFS2. Please ensure that your * JFFS2 partitions are given image numbers between * 1000 and 2000 inclusive. */ if (iis.imageNumber >= 1000 && iis.imageNumber < 2000) size -= mtd->erasesize; parts[idx].name = str; parts[idx].size = size; parts[idx].offset = img_ptr; parts[idx].mask_flags = 0; printk(" mtd%d: at 0x%08x, %5dKB, %8u, %s\n", idx, img_ptr, parts[idx].size / 1024, iis.imageNumber, str); idx += 1; str = str + strlen(iis.name) + 1; } if (!idx) { kfree(parts); parts = NULL; } *pparts = parts; return idx ? idx : ret; }
/** * ehci_hcd_omap_probe - initialize TI-based HCDs * * Allocates basic resources for this USB host controller, and * then invokes the start() method for the HCD associated with it * through the hotplug entry's driver_data. */ static int ehci_hcd_omap_probe(struct platform_device *pdev) { struct ehci_hcd_omap_platform_data *pdata = pdev->dev.platform_data; struct ehci_hcd_omap *omap; struct resource *res; struct usb_hcd *hcd; int irq = platform_get_irq(pdev, 0); int ret = -ENODEV; printk(KERN_DEBUG " ehci_hcd_omap_probe\n"); if (!pdata) { dev_dbg(&pdev->dev, "missing platform_data\n"); goto err_pdata; } if (usb_disabled()) { printk(KERN_DEBUG " usb_disabled\n"); goto err_disabled; } omap = kzalloc(sizeof(*omap), GFP_KERNEL); printk(KERN_DEBUG " kzalloc done\n"); if (!omap) { printk(KERN_DEBUG " problem with memory allocation\n"); ret = -ENOMEM; goto err_disabled; } hcd = usb_create_hcd(&ehci_omap_hc_driver, &pdev->dev, dev_name(&pdev->dev)); printk(KERN_DEBUG " usb_create hcd done\n"); if (!hcd) { printk(KERN_DEBUG " failed to create HCD\n"); dev_dbg(&pdev->dev, "failed to create hcd with err %d\n", ret); ret = -ENOMEM; goto err_create_hcd; } platform_set_drvdata(pdev, omap); omap->dev = &pdev->dev; omap->phy_reset = pdata->phy_reset; omap->reset_gpio_port[0] = pdata->reset_gpio_port[0]; omap->reset_gpio_port[1] = pdata->reset_gpio_port[1]; omap->reset_gpio_port[2] = pdata->reset_gpio_port[2]; omap->port_mode[0] = pdata->port_mode[0]; omap->port_mode[1] = pdata->port_mode[1]; omap->port_mode[2] = pdata->port_mode[2]; omap->ehci = hcd_to_ehci(hcd); omap->ehci->sbrn = 0x20; omap->suspended = 0; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); printk(KERN_DEBUG " platform get ressources 0 done\n"); hcd->rsrc_start = res->start; hcd->rsrc_len = resource_size(res); hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); if (!hcd->regs) { printk(KERN_DEBUG " EHCI ioremap failed\n"); dev_err(&pdev->dev, "EHCI ioremap failed\n"); ret = -ENOMEM; goto err_ioremap; } /* we know this is the memory we want, no need to ioremap again */ omap->ehci->caps = hcd->regs; omap->ehci_base = hcd->regs; res = platform_get_resource(pdev, IORESOURCE_MEM, 1); printk(KERN_DEBUG " platform get ressources 1 done\n"); omap->uhh_base = ioremap(res->start, resource_size(res)); if (!omap->uhh_base) { printk(KERN_DEBUG " UHH ioremap failed\n"); dev_err(&pdev->dev, "UHH ioremap failed\n"); ret = -ENOMEM; goto err_uhh_ioremap; } res = platform_get_resource(pdev, IORESOURCE_MEM, 2); printk(KERN_DEBUG " platform get ressources 2 done\n"); ret = omap_start_ehc(omap, hcd); if (ret) { dev_dbg(&pdev->dev, "failed to start ehci\n"); printk(KERN_DEBUG " failed to start ehci\n"); goto err_start; } omap->ehci->regs = hcd->regs + HC_LENGTH(readl(&omap->ehci->caps->hc_capbase)); dbg_hcs_params(omap->ehci, "reset"); dbg_hcc_params(omap->ehci, "reset"); /* cache this readonly data; minimize chip reads */ omap->ehci->hcs_params = readl(&omap->ehci->caps->hcs_params); /* SET 1 micro-frame Interrupt interval */ writel(readl(&omap->ehci->regs->command) | (1 << 16), &omap->ehci->regs->command); ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); if (ret) { dev_dbg(&pdev->dev, "failed to add hcd with err %d\n", ret); goto err_add_hcd; } EP10_HW_ID=ep_get_hardware_id(); if(EP10_HW_ID==BOARD_VERSION_UNKNOWN) { EP10_HW_ID = BOARD_ID_DVT1 ; } printk(KERN_DEBUG " add hcd done\n"); return 0; err_add_hcd: omap_stop_ehc(omap, hcd); err_start: //iounmap(omap->tll_base); err_tll_ioremap: iounmap(omap->uhh_base); err_uhh_ioremap: iounmap(hcd->regs); err_ioremap: usb_put_hcd(hcd); err_create_hcd: kfree(omap); err_disabled: err_pdata: return ret; }
/* ----------------------------- Entry point ------------------------------- */ static int __init init_modanalizer(void) { struct module *mod_ptr; unsigned int i,j; mutex_lock(&module_mutex); mod_ptr = find_module(module_name); mutex_unlock(&module_mutex); if (!mod_ptr) { printk(MODULE_PRINTK "Module doesn't exist\n"); return -EINVAL; } printk(MODULE_PRINTK "Found module: %s\n", mod_ptr->name); /* Count all text symbols */ ma_symbols_count = 0; for(i = 0; i < mod_ptr->num_symtab; ++i) { Elf64_Sym *sym = &mod_ptr->symtab[i]; if (sym->st_info == 't' || sym->st_info == 'T') ma_symbols_count++; } printk(MODULE_PRINTK "Getting text symbols (%u)...\n", ma_symbols_count); ma_symbols = kmalloc(sizeof(*ma_symbols) * ma_symbols_count, GFP_KERNEL); if (!ma_symbols) { printk(MODULE_PRINTK "Not enough memory to allocate symbols\n"); return -ENOMEM; } /* Clear all memory */ memset(ma_symbols, 0, sizeof(*ma_symbols) * ma_symbols_count); /* Get all symbols - TODO: Not sure if some lock is required there */ for (i = 0, j = 0; i < mod_ptr->num_symtab; ++i) { Elf64_Sym *sym; sym = &mod_ptr->symtab[i]; if (sym->st_info != 't' && sym->st_info != 'T') continue; ma_symbols[j].kp.addr = (kprobe_opcode_t*) (sym->st_value); ma_symbols[j].kp.pre_handler = ma_pre_handler; ma_symbols[j].name = mod_ptr->strtab + sym->st_name; ma_symbols[j].size = sym->st_size; printk(MODULE_PRINTK "%u: %s\n", j, ma_symbols[j].name); if (register_kprobe(&ma_symbols[j].kp) < 0) { printk(MODULE_PRINTK "Couldn't register kprobe for function: %s\n", ma_symbols[j].name); ma_symbols[j].kp.addr = NULL; } ++j; } if (!proc_create(MODULE_NAME_STR, 0644, NULL, &ma_file_ops)) { printk(MODULE_PRINTK "Couldn't create procfs file\n"); kfree(ma_symbols); return -ENOMEM; } return 0; }
/* * Read and decode extended CSD. */ static int mmc_read_ext_csd(struct mmc_card *card) { int err; u8 *ext_csd; BUG_ON(!card); if (card->csd.mmca_vsn < CSD_SPEC_VER_4) return 0; /* * As the ext_csd is so large and mostly unused, we don't store the * raw block in mmc_card. */ ext_csd = kmalloc(512, GFP_KERNEL); if (!ext_csd) { printk(KERN_ERR "%s: could not allocate a buffer to " "receive the ext_csd.\n", mmc_hostname(card->host)); return -ENOMEM; } err = mmc_send_ext_csd(card, ext_csd); if (err) { /* If the host or the card can't do the switch, * fail more gracefully. */ if ((err != -EINVAL) && (err != -ENOSYS) && (err != -EFAULT)) goto out; /* * High capacity cards should have this "magic" size * stored in their CSD. */ if (card->csd.capacity == (4096 * 512)) { printk(KERN_ERR "%s: unable to read EXT_CSD " "on a possible high capacity card. " "Card will be ignored.\n", mmc_hostname(card->host)); } else { printk(KERN_WARNING "%s: unable to read " "EXT_CSD, performance might " "suffer.\n", mmc_hostname(card->host)); err = 0; } goto out; } /* Version is coded in the CSD_STRUCTURE byte in the EXT_CSD register */ if (card->csd.structure == 3) { int ext_csd_struct = ext_csd[EXT_CSD_STRUCTURE]; if (ext_csd_struct > 2) { printk(KERN_ERR "%s: unrecognised EXT_CSD structure " "version %d\n", mmc_hostname(card->host), ext_csd_struct); err = -EINVAL; goto out; } } card->ext_csd.rev = ext_csd[EXT_CSD_REV]; if (card->ext_csd.rev > 5) { printk(KERN_ERR "%s: unrecognised EXT_CSD revision %d\n", mmc_hostname(card->host), card->ext_csd.rev); err = -EINVAL; goto out; } if (card->ext_csd.rev >= 2) { card->ext_csd.sectors = ext_csd[EXT_CSD_SEC_CNT + 0] << 0 | ext_csd[EXT_CSD_SEC_CNT + 1] << 8 | ext_csd[EXT_CSD_SEC_CNT + 2] << 16 | ext_csd[EXT_CSD_SEC_CNT + 3] << 24; #if !defined(CONFIG_INAND_VERSION_PATCH) if (card->ext_csd.sectors) mmc_card_set_blockaddr(card); #endif } switch (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_MASK) { case EXT_CSD_CARD_TYPE_52 | EXT_CSD_CARD_TYPE_26: card->ext_csd.hs_max_dtr = 52000000; break; case EXT_CSD_CARD_TYPE_26: card->ext_csd.hs_max_dtr = 26000000; break; default: /* MMC v4 spec says this cannot happen */ printk(KERN_WARNING "%s: card is mmc v4 but doesn't " "support any high-speed modes.\n", mmc_hostname(card->host)); } if (card->ext_csd.rev >= 3) { u8 sa_shift = ext_csd[EXT_CSD_S_A_TIMEOUT]; /* Sleep / awake timeout in 100ns units */ if (sa_shift > 0 && sa_shift <= 0x17) card->ext_csd.sa_timeout = 1 << ext_csd[EXT_CSD_S_A_TIMEOUT]; } out: kfree(ext_csd); return err; }
static int __devinit hydra_init(struct zorro_dev *z) { struct net_device *dev; unsigned long board = ZTWO_VADDR(z->resource.start); unsigned long ioaddr = board+HYDRA_NIC_BASE; const char name[] = "NE2000"; int start_page, stop_page; int j; int err; static u32 hydra_offsets[16] = { 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e, }; dev = alloc_ei_netdev(); if (!dev) return -ENOMEM; SET_MODULE_OWNER(dev); for(j = 0; j < ETHER_ADDR_LEN; j++) dev->dev_addr[j] = *((u8 *)(board + HYDRA_ADDRPROM + 2*j)); /* We must set the 8390 for word mode. */ z_writeb(0x4b, ioaddr + NE_EN0_DCFG); start_page = NESM_START_PG; stop_page = NESM_STOP_PG; dev->base_addr = ioaddr; dev->irq = IRQ_AMIGA_PORTS; /* Install the Interrupt handler */ if (request_irq(IRQ_AMIGA_PORTS, ei_interrupt, SA_SHIRQ, "Hydra Ethernet", dev)) { free_netdev(dev); return -EAGAIN; } ei_status.name = name; ei_status.tx_start_page = start_page; ei_status.stop_page = stop_page; ei_status.word16 = 1; ei_status.bigendian = 1; ei_status.rx_start_page = start_page + TX_PAGES; ei_status.reset_8390 = &hydra_reset_8390; ei_status.block_input = &hydra_block_input; ei_status.block_output = &hydra_block_output; ei_status.get_8390_hdr = &hydra_get_8390_hdr; ei_status.reg_offset = hydra_offsets; dev->open = &hydra_open; dev->stop = &hydra_close; #ifdef CONFIG_NET_POLL_CONTROLLER dev->poll_controller = ei_poll; #endif NS8390_init(dev, 0); err = register_netdev(dev); if (err) { free_irq(IRQ_AMIGA_PORTS, dev); free_netdev(dev); return err; } zorro_set_drvdata(z, dev); printk(KERN_INFO "%s: Hydra at 0x%08lx, address " "%02x:%02x:%02x:%02x:%02x:%02x (hydra.c " HYDRA_VERSION ")\n", dev->name, z->resource.start, dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); return 0; }
/* * Handle the detection and initialisation of a card. * * In the case of a resume, "oldcard" will contain the card * we're trying to reinitialise. */ static int mmc_init_card(struct mmc_host *host, u32 ocr, struct mmc_card *oldcard) { struct mmc_card *card; int err; u32 cid[4]; #if defined(CONFIG_INAND_VERSION_PATCH) u32 rocr[1]; #endif unsigned int max_dtr; BUG_ON(!host); WARN_ON(!host->claimed); /* * Since we're changing the OCR value, we seem to * need to tell some cards to go back to the idle * state. We wait 1ms to give cards time to * respond. */ mmc_go_idle(host); /* The extra bit indicates that we support high capacity */ #if defined(CONFIG_INAND_VERSION_PATCH) err = mmc_send_op_cond(host, ocr | (1 << 30), rocr); #else err = mmc_send_op_cond(host, ocr | (1 << 30), NULL); #endif if (err) goto err; /* * For SPI, enable CRC as appropriate. */ if (mmc_host_is_spi(host)) { err = mmc_spi_set_crc(host, use_spi_crc); if (err) goto err; } /* * Fetch CID from card. */ if (mmc_host_is_spi(host)) err = mmc_send_cid(host, cid); else err = mmc_all_send_cid(host, cid); if (err) goto err; if (oldcard) { if (memcmp(cid, oldcard->raw_cid, sizeof(cid)) != 0) { err = -ENOENT; goto err; } oldcard->err_count = 0; card = oldcard; } else { /* * Allocate card structure. */ card = mmc_alloc_card(host, &mmc_type); if (IS_ERR(card)) { err = PTR_ERR(card); goto err; } card->type = MMC_TYPE_MMC; card->rca = 1; memcpy(card->raw_cid, cid, sizeof(card->raw_cid)); host->card = card; } /* * For native busses: set card RCA and quit open drain mode. */ if (!mmc_host_is_spi(host)) { err = mmc_set_relative_addr(card); if (err) goto free_card; mmc_set_bus_mode(host, MMC_BUSMODE_PUSHPULL); } if (!oldcard) { /* * Fetch CSD from card. */ err = mmc_send_csd(card, card->raw_csd); if (err) goto free_card; err = mmc_decode_csd(card); if (err) goto free_card; err = mmc_decode_cid(card); if (err) goto free_card; } /* * Select card, as all following commands rely on that. */ if (!mmc_host_is_spi(host)) { err = mmc_select_card(card); if (err) goto free_card; } if (!oldcard) { /* * Fetch and process extended CSD. */ err = mmc_read_ext_csd(card); if (err) goto free_card; #if defined(CONFIG_INAND_VERSION_PATCH) if (rocr[0] & 0x40000000) mmc_card_set_blockaddr(card); #endif } /* * Activate high speed (if supported) */ if ((card->ext_csd.hs_max_dtr != 0) && (host->caps & MMC_CAP_MMC_HIGHSPEED)) { err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1); if (err && err != -EBADMSG) goto free_card; if (err) { printk(KERN_WARNING "%s: switch to highspeed failed\n", mmc_hostname(card->host)); err = 0; } else { mmc_card_set_highspeed(card); mmc_set_timing(card->host, MMC_TIMING_MMC_HS); } } /* * Compute bus speed. */ max_dtr = (unsigned int)-1; if (mmc_card_highspeed(card)) { if (max_dtr > card->ext_csd.hs_max_dtr) max_dtr = card->ext_csd.hs_max_dtr; } else if (max_dtr > card->csd.max_dtr) { max_dtr = card->csd.max_dtr; } mmc_set_clock(host, max_dtr); /* * Activate wide bus (if supported). */ if ((card->csd.mmca_vsn >= CSD_SPEC_VER_4) && (host->caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA))) { unsigned ext_csd_bit, bus_width; if (host->caps & MMC_CAP_8_BIT_DATA) { ext_csd_bit = EXT_CSD_BUS_WIDTH_8; bus_width = MMC_BUS_WIDTH_8; } else { ext_csd_bit = EXT_CSD_BUS_WIDTH_4; bus_width = MMC_BUS_WIDTH_4; } err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_BUS_WIDTH, ext_csd_bit); if (err && err != -EBADMSG) goto free_card; if (err) { printk(KERN_WARNING "%s: switch to bus width %d " "failed\n", mmc_hostname(card->host), 1 << bus_width); err = 0; } else { mmc_set_bus_width(card->host, bus_width); } } return 0; free_card: if (!oldcard) { mmc_remove_card(card); host->card = NULL; } err: return err; }
/* Received a packet and pass to upper layer */ static void dmfe_packet_receive(struct net_device *dev) { board_info_t *db = netdev_priv(dev); struct sk_buff *skb; u8 rxbyte; u16 i, GoodPacket, tmplen = 0, MDRAH, MDRAL; u32 tmpdata; rx_t rx; u16 * ptr = (u16*)℞ u8* rdptr; DMFE_DBUG(0, "dmfe_packet_receive()", 0); db->cont_rx_pkt_cnt=0; do { /*store the value of Memory Data Read address register*/ MDRAH=ior(db, DM9KS_MDRAH); MDRAL=ior(db, DM9KS_MDRAL); ior(db, DM9KS_MRCMDX); /* Dummy read */ rxbyte = inb(db->io_data); /* Got most updated data */ #ifdef CHECKSUM if (rxbyte&0x2) /* check RX byte */ { printk("dm9ks: abnormal!\n"); dmfe_reset(dev); break; }else { if (!(rxbyte&0x1)) break; } #else if (rxbyte==0) break; if (rxbyte>1) { printk("dm9ks: Rxbyte error!\n"); dmfe_reset(dev); break; } #endif /* A packet ready now & Get status/length */ GoodPacket = TRUE; outb(DM9KS_MRCMD, db->io_addr); /* Read packet status & length */ switch (db->io_mode) { case DM9KS_BYTE_MODE: *ptr = inb(db->io_data) + (inb(db->io_data) << 8); *(ptr+1) = inb(db->io_data) + (inb(db->io_data) << 8); break; case DM9KS_WORD_MODE: *ptr = inw(db->io_data); *(ptr+1) = inw(db->io_data); break; case DM9KS_DWORD_MODE: tmpdata = inl(db->io_data); *ptr = tmpdata; *(ptr+1) = tmpdata >> 16; break; default: break; } /* Packet status check */ if (rx.desc.status & 0xbf) { GoodPacket = FALSE; if (rx.desc.status & 0x01) { db->stats.rx_fifo_errors++; printk(KERN_INFO"<RX FIFO error>\n"); } if (rx.desc.status & 0x02) { db->stats.rx_crc_errors++; printk(KERN_INFO"<RX CRC error>\n"); } if (rx.desc.status & 0x80) { db->stats.rx_length_errors++; printk(KERN_INFO"<RX Length error>\n"); } if (rx.desc.status & 0x08) printk(KERN_INFO"<Physical Layer error>\n"); } if (!GoodPacket) { // drop this packet!!! switch (db->io_mode) { case DM9KS_BYTE_MODE: for (i=0; i<rx.desc.length; i++) inb(db->io_data); break; case DM9KS_WORD_MODE: tmplen = (rx.desc.length + 1) / 2; for (i = 0; i < tmplen; i++) inw(db->io_data); break; case DM9KS_DWORD_MODE: tmplen = (rx.desc.length + 3) / 4; for (i = 0; i < tmplen; i++) inl(db->io_data); break; } continue;/*next the packet*/ } skb = dev_alloc_skb(rx.desc.length+4); if (skb == NULL ) { printk(KERN_INFO "%s: Memory squeeze.\n", dev->name); /*re-load the value into Memory data read address register*/ iow(db,DM9KS_MDRAH,MDRAH); iow(db,DM9KS_MDRAL,MDRAL); return; } else { /* Move data from DM9000 */ skb->dev = dev; skb_reserve(skb, 2); rdptr = (u8*)skb_put(skb, rx.desc.length - 4); /* Read received packet from RX SARM */ switch (db->io_mode) { case DM9KS_BYTE_MODE: for (i=0; i<rx.desc.length; i++) rdptr[i]=inb(db->io_data); break; case DM9KS_WORD_MODE: tmplen = (rx.desc.length + 1) / 2; for (i = 0; i < tmplen; i++) ((u16 *)rdptr)[i] = inw(db->io_data); break; case DM9KS_DWORD_MODE: tmplen = (rx.desc.length + 3) / 4; for (i = 0; i < tmplen; i++) ((u32 *)rdptr)[i] = inl(db->io_data); break; } /* Pass to upper layer */ skb->protocol = eth_type_trans(skb,dev); #ifdef CHECKSUM if((rxbyte&0xe0)==0) /* receive packet no checksum fail */ skb->ip_summed = CHECKSUM_UNNECESSARY; #endif netif_rx(skb); dev->last_rx=jiffies; db->stats.rx_packets++; db->stats.rx_bytes += rx.desc.length; db->cont_rx_pkt_cnt++; #ifdef RDBG /* check RX FIFO pointer */ u16 MDRAH1, MDRAL1; u16 tmp_ptr; MDRAH1 = ior(db,DM9KS_MDRAH); MDRAL1 = ior(db,DM9KS_MDRAL); tmp_ptr = (MDRAH<<8)|MDRAL; switch (db->io_mode) { case DM9KS_BYTE_MODE: tmp_ptr += rx.desc.length+4; break; case DM9KS_WORD_MODE: tmp_ptr += ((rx.desc.length+1)/2)*2+4; break; case DM9KS_DWORD_MODE: tmp_ptr += ((rx.desc.length+3)/4)*4+4; break; } if (tmp_ptr >=0x4000) tmp_ptr = (tmp_ptr - 0x4000) + 0xc00; if (tmp_ptr != ((MDRAH1<<8)|MDRAL1)) printk("[dm9ks:RX FIFO ERROR\n"); #endif if (db->cont_rx_pkt_cnt>=CONT_RX_PKT_CNT) { dmfe_tx_done(0); break; } } }while((rxbyte & 0x01) == DM9KS_PKT_RDY); DMFE_DBUG(0, "[END]dmfe_packet_receive()", 0); }
/* * Starting point for MMC card init. */ int mmc_attach_mmc(struct mmc_host *host, u32 ocr) { int err; BUG_ON(!host); WARN_ON(!host->claimed); mmc_attach_bus_ops(host); /* * We need to get OCR a different way for SPI. */ if (mmc_host_is_spi(host)) { err = mmc_spi_read_ocr(host, 1, &ocr); if (err) goto err; } /* * Sanity check the voltages that the card claims to * support. */ if (ocr & 0x7F) { printk(KERN_WARNING "%s: card claims to support voltages " "below the defined range. These will be ignored.\n", mmc_hostname(host)); ocr &= ~0x7F; } host->ocr = mmc_select_voltage(host, ocr); /* * Can we support the voltage of the card? */ if (!host->ocr) { err = -EINVAL; goto err; } /* * Detect and init the card. */ err = mmc_init_card(host, host->ocr, NULL); if (err) goto err; mmc_release_host(host); err = mmc_add_card(host->card); if (err) goto remove_card; return 0; remove_card: mmc_remove_card(host->card); host->card = NULL; mmc_claim_host(host); err: mmc_detach_bus(host); mmc_release_host(host); printk(KERN_ERR "%s: error %d whilst initialising MMC card\n", mmc_hostname(host), err); return err; }
/* Initilize dm9000 board */ static void dmfe_init_dm9000(struct net_device *dev) { board_info_t *db = netdev_priv(dev); DMFE_DBUG(0, "dmfe_init_dm9000()", 0); spin_lock_init(&db->lock); iow(db, DM9KS_GPR, 0); /* GPR (reg_1Fh)bit GPIO0=0 pre-activate PHY */ mdelay(20); /* wait for PHY power-on ready */ /* do a software reset and wait 20us */ iow(db, DM9KS_NCR, 3); udelay(20); /* wait 20us at least for software reset ok */ iow(db, DM9KS_NCR, 3); /* NCR (reg_00h) bit[0] RST=1 & Loopback=1, reset on */ udelay(20); /* wait 20us at least for software reset ok */ /* I/O mode */ db->io_mode = ior(db, DM9KS_ISR) >> 6; /* ISR bit7:6 keeps I/O mode */ /* Set PHY */ db->op_mode = media_mode; set_PHY_mode(db); /* Program operating register */ iow(db, DM9KS_NCR, 0); iow(db, DM9KS_TCR, 0); /* TX Polling clear */ iow(db, DM9KS_BPTR, 0x3f); /* Less 3kb, 600us */ iow(db, DM9KS_SMCR, 0); /* Special Mode */ iow(db, DM9KS_NSR, 0x2c); /* clear TX status */ iow(db, DM9KS_ISR, 0x0f); /* Clear interrupt status */ iow(db, DM9KS_TCR2, 0x80); /* Set LED mode 1 */ if (db->chip_revision == 0x1A){ /* Data bus current driving/sinking capability */ iow(db, DM9KS_BUSCR, 0x01); /* default: 2mA */ } #ifdef FLOW_CONTROL iow(db, DM9KS_BPTR, 0x37); iow(db, DM9KS_FCTR, 0x38); iow(db, DM9KS_FCR, 0x29); #endif #ifdef DM8606 iow(db,0x34,1); #endif if (dev->features & NETIF_F_HW_CSUM){ printk(KERN_INFO "DM9KS:enable TX checksum\n"); iow(db, DM9KS_TCCR, 0x07); /* TX UDP/TCP/IP checksum enable */ } if (db->rx_csum){ printk(KERN_INFO "DM9KS:enable RX checksum\n"); iow(db, DM9KS_RCSR, 0x02); /* RX checksum enable */ } #ifdef ETRANS /*If TX loading is heavy, the driver can try to anbel "early transmit". The programmer can tune the "Early Transmit Threshold" to get the optimization. (DM9KS_ETXCSR.[1-0]) Side Effect: It will happen "Transmit under-run". When TX under-run always happens, the programmer can increase the value of "Early Transmit Threshold". */ iow(db, DM9KS_ETXCSR, 0x83); #endif /* Set address filter table */ dm9000_hash_table(dev); /* Activate DM9000/DM9010 */ iow(db, DM9KS_IMR, DM9KS_REGFF); /* Enable TX/RX interrupt mask */ iow(db, DM9KS_RXCR, DM9KS_REG05 | 1); /* RX enable */ /* Init Driver variable */ db->tx_pkt_cnt = 0; netif_carrier_on(dev); }
asmlinkage void __init start_kernel(void) { char * command_line; extern struct kernel_param __start___param[], __stop___param[]; smp_setup_processor_id(); /* * Need to run as early as possible, to initialize the * lockdep hash: */ lockdep_init(); debug_objects_early_init(); /* * Set up the the initial canary ASAP: */ boot_init_stack_canary(); cgroup_init_early(); local_irq_disable(); early_boot_irqs_off(); early_init_irq_lock_class(); /* * Interrupts are still disabled. Do necessary setups, then * enable them */ lock_kernel(); tick_init(); boot_cpu_init(); page_address_init(); printk(KERN_NOTICE "%s", linux_banner); setup_arch(&command_line); mm_init_owner(&init_mm, &init_task); setup_command_line(command_line); setup_nr_cpu_ids(); setup_per_cpu_areas(); smp_prepare_boot_cpu(); /* arch-specific boot-cpu hooks */ build_all_zonelists(NULL); page_alloc_init(); printk(KERN_NOTICE "Kernel command line: %s\n", boot_command_line); #ifdef CONFIG_BOARD_PW28 analyse_kernel_cmdline(0); printk(KERN_NOTICE "Kernel battchg_pause: %d\n", battchg_pause); #endif parse_early_param(); parse_args("Booting kernel", static_command_line, __start___param, __stop___param - __start___param, &unknown_bootoption); /* * These use large bootmem allocations and must precede * kmem_cache_init() */ pidhash_init(); vfs_caches_init_early(); sort_main_extable(); trap_init(); mm_init(); /* * Set up the scheduler prior starting any interrupts (such as the * timer interrupt). Full topology setup happens at smp_init() * time - but meanwhile we still have a functioning scheduler. */ sched_init(); /* * Disable preemption - early bootup scheduling is extremely * fragile until we cpu_idle() for the first time. */ preempt_disable(); if (!irqs_disabled()) { printk(KERN_WARNING "start_kernel(): bug: interrupts were " "enabled *very* early, fixing it\n"); local_irq_disable(); } rcu_init(); radix_tree_init(); /* init some links before init_ISA_irqs() */ early_irq_init(); init_IRQ(); prio_tree_init(); init_timers(); hrtimers_init(); softirq_init(); timekeeping_init(); time_init(); profile_init(); if (!irqs_disabled()) printk(KERN_CRIT "start_kernel(): bug: interrupts were " "enabled early\n"); early_boot_irqs_on(); local_irq_enable(); /* Interrupts are enabled now so all GFP allocations are safe. */ gfp_allowed_mask = __GFP_BITS_MASK; kmem_cache_init_late(); /* * HACK ALERT! This is early. We're enabling the console before * we've done PCI setups etc, and console_init() must be aware of * this. But we do want output early, in case something goes wrong. */ console_init(); if (panic_later) panic(panic_later, panic_param); lockdep_info(); /* * Need to run this when irqs are enabled, because it wants * to self-test [hard/soft]-irqs on/off lock inversion bugs * too: */ locking_selftest(); #ifdef CONFIG_BLK_DEV_INITRD if (initrd_start && !initrd_below_start_ok && page_to_pfn(virt_to_page((void *)initrd_start)) < min_low_pfn) { printk(KERN_CRIT "initrd overwritten (0x%08lx < 0x%08lx) - " "disabling it.\n", page_to_pfn(virt_to_page((void *)initrd_start)), min_low_pfn); initrd_start = 0; } #endif page_cgroup_init(); enable_debug_pagealloc(); kmemtrace_init(); kmemleak_init(); debug_objects_mem_init(); idr_init_cache(); setup_per_cpu_pageset(); numa_policy_init(); if (late_time_init) late_time_init(); sched_clock_init(); calibrate_delay(); pidmap_init(); anon_vma_init(); #ifdef CONFIG_X86 if (efi_enabled) efi_enter_virtual_mode(); #endif thread_info_cache_init(); cred_init(); fork_init(totalram_pages); proc_caches_init(); buffer_init(); key_init(); security_init(); dbg_late_init(); vfs_caches_init(totalram_pages); signals_init(); /* rootfs populating might need page-writeback */ page_writeback_init(); #ifdef CONFIG_PROC_FS proc_root_init(); #endif cgroup_init(); cpuset_init(); taskstats_init_early(); delayacct_init(); check_bugs(); acpi_early_init(); /* before LAPIC and SMP init */ sfi_init_late(); ftrace_init(); /* Do the rest non-__init'ed, we're now alive */ rest_init(); }
/**************************************************************************** * Module tidy up ****************************************************************************/ static void __exit rkd_exit(void) { printk("RKD:%s module: unloaded\n", acModuleName); }
static int __init kernel_init(void * unused) { /* * Wait until kthreadd is all set-up. */ wait_for_completion(&kthreadd_done); lock_kernel(); /* * init can allocate pages on any node */ set_mems_allowed(node_states[N_HIGH_MEMORY]); /* * init can run on any cpu. */ set_cpus_allowed_ptr(current, cpu_all_mask); /* * Tell the world that we're going to be the grim * reaper of innocent orphaned children. * * We don't want people to have to make incorrect * assumptions about where in the task array this * can be found. */ init_pid_ns.child_reaper = current; cad_pid = task_pid(current); smp_prepare_cpus(setup_max_cpus); do_pre_smp_initcalls(); start_boot_trace(); smp_init(); sched_init_smp(); do_basic_setup(); /* Open the /dev/console on the rootfs, this should never fail */ if (sys_open((const char __user *) "/dev/console", O_RDWR, 0) < 0) printk(KERN_WARNING "Warning: unable to open an initial console.\n"); (void) sys_dup(0); (void) sys_dup(0); /* * check if there is an early userspace init. If yes, let it do all * the work */ if (!ramdisk_execute_command) ramdisk_execute_command = "/init"; if (sys_access((const char __user *) ramdisk_execute_command, 0) != 0) { ramdisk_execute_command = NULL; prepare_namespace(); } /* * Ok, we have completed the initial bootup, and * we're essentially up and running. Get rid of the * initmem segments and start the user-mode stuff.. */ init_post(); return 0; }
// led ctrl. Maps the ledName to the corresponding ledInfoPtr and perform the led operation void boardLedCtrl(BOARD_LED_NAME ledName, BOARD_LED_STATE ledState) { unsigned long flags; PLED_CTRL pLed; spin_lock_irqsave(&brcm_ledlock, flags); // LED can be changed from ISR if( (int) ledName < kLedEnd ) { pLed = &gLedCtrl[ledName]; // If the state is kLedStateFail and there is not a failure LED defined // in the board parameters, change the state to kLedStateSlowBlinkContinues. if( ledState == kLedStateFail && pLed->ledRedGpio == -1 ) ledState = kLedStateSlowBlinkContinues; // Save current LED state pLed->ledState = ledState; if( pLed->ledHwFunc) { // Handle LEDs controlled by HW specific logic pLed->ledHwFunc (ledState); if (ledState == kLedStateFail) setLed (pLed, kLedOn, kLedRed); else setLed (pLed, kLedOff, kLedRed); } else { // Handle LEDs controlled by SW // Start from LED Off and turn it on later as needed setLed (pLed, kLedOff, kLedGreen); setLed (pLed, kLedOff, kLedRed); #if defined(CONFIG_BCM96328) || defined(CONFIG_BCM96362) // Disable HW control for WAN Data LED. // It will be enabled only if LED state is On if (ledName == kLedWanData) LED->ledHWDis |= GPIO_NUM_TO_MASK(pLed->ledGreenGpio); #endif switch (ledState) { case kLedStateOn: #if defined(CONFIG_BCM96328) || defined(CONFIG_BCM96362) // Enable SAR to control INET LED if (ledName == kLedWanData) LED->ledHWDis &= ~GPIO_NUM_TO_MASK(pLed->ledGreenGpio); #endif setLed (pLed, kLedOn, kLedGreen); break; case kLedStateOff: break; case kLedStateFail: setLed (pLed, kLedOn, kLedRed); break; case kLedStateSlowBlinkContinues: pLed->blinkCountDown = kSlowBlinkCount; ledTimerStart(); break; case kLedStateFastBlinkContinues: pLed->blinkCountDown = kFastBlinkCount; ledTimerStart(); break; case kLedStateUserWpsInProgress: /* 200ms on, 100ms off */ pLed->blinkCountDown = kFastBlinkCount; gLedRunningCounter = 0; ledTimerStart(); break; case kLedStateUserWpsError: /* 100ms on, 100ms off */ pLed->blinkCountDown = kFastBlinkCount; gLedRunningCounter = 0; ledTimerStart(); break; case kLedStateUserWpsSessionOverLap: /* 100ms on, 100ms off, 5 times, off for 500ms */ pLed->blinkCountDown = kFastBlinkCount; ledTimerStart(); break; default: printk("Invalid led state\n"); } } } spin_unlock_irqrestore(&brcm_ledlock, flags); }
static enum si_sm_result smic_event(struct si_sm_data *smic, long time) { unsigned char status; unsigned char flags; unsigned char data; if (smic->state == SMIC_HOSED) { init_smic_data(smic, smic->io); return SI_SM_HOSED; } if (smic->state != SMIC_IDLE) { if (smic_debug & SMIC_DEBUG_STATES) printk(KERN_DEBUG "smic_event - smic->smic_timeout = %ld," " time = %ld\n", smic->smic_timeout, time); if (time < SMIC_RETRY_TIMEOUT) { smic->smic_timeout -= time; if (smic->smic_timeout < 0) { start_error_recovery(smic, "smic timed out."); return SI_SM_CALL_WITH_DELAY; } } } flags = read_smic_flags(smic); if (flags & SMIC_FLAG_BSY) return SI_SM_CALL_WITH_DELAY; status = read_smic_status(smic); if (smic_debug & SMIC_DEBUG_STATES) printk(KERN_DEBUG "smic_event - state = %d, flags = 0x%02x," " status = 0x%02x\n", smic->state, flags, status); switch (smic->state) { case SMIC_IDLE: /* in IDLE we check for available messages */ if (flags & SMIC_SMS_DATA_AVAIL) return SI_SM_ATTN; return SI_SM_IDLE; case SMIC_START_OP: /* sanity check whether smic is really idle */ write_smic_control(smic, SMIC_CC_SMS_GET_STATUS); write_smic_flags(smic, flags | SMIC_FLAG_BSY); smic->state = SMIC_OP_OK; break; case SMIC_OP_OK: if (status != SMIC_SC_SMS_READY) { /* this should not happen */ start_error_recovery(smic, "state = SMIC_OP_OK," " status != SMIC_SC_SMS_READY"); return SI_SM_CALL_WITH_DELAY; } /* OK so far; smic is idle let us start ... */ write_smic_control(smic, SMIC_CC_SMS_WR_START); write_next_byte(smic); write_smic_flags(smic, flags | SMIC_FLAG_BSY); smic->state = SMIC_WRITE_START; break; case SMIC_WRITE_START: if (status != SMIC_SC_SMS_WR_START) { start_error_recovery(smic, "state = SMIC_WRITE_START, " "status != SMIC_SC_SMS_WR_START"); return SI_SM_CALL_WITH_DELAY; } /* * we must not issue WR_(NEXT|END) unless * TX_DATA_READY is set * */ if (flags & SMIC_TX_DATA_READY) { if (smic->write_count == 1) { /* last byte */ write_smic_control(smic, SMIC_CC_SMS_WR_END); smic->state = SMIC_WRITE_END; } else { write_smic_control(smic, SMIC_CC_SMS_WR_NEXT); smic->state = SMIC_WRITE_NEXT; } write_next_byte(smic); write_smic_flags(smic, flags | SMIC_FLAG_BSY); } else return SI_SM_CALL_WITH_DELAY; break; case SMIC_WRITE_NEXT: if (status != SMIC_SC_SMS_WR_NEXT) { start_error_recovery(smic, "state = SMIC_WRITE_NEXT, " "status != SMIC_SC_SMS_WR_NEXT"); return SI_SM_CALL_WITH_DELAY; } /* this is the same code as in SMIC_WRITE_START */ if (flags & SMIC_TX_DATA_READY) { if (smic->write_count == 1) { write_smic_control(smic, SMIC_CC_SMS_WR_END); smic->state = SMIC_WRITE_END; } else { write_smic_control(smic, SMIC_CC_SMS_WR_NEXT); smic->state = SMIC_WRITE_NEXT; } write_next_byte(smic); write_smic_flags(smic, flags | SMIC_FLAG_BSY); } else return SI_SM_CALL_WITH_DELAY; break; case SMIC_WRITE_END: if (status != SMIC_SC_SMS_WR_END) { start_error_recovery(smic, "state = SMIC_WRITE_END, " "status != SMIC_SC_SMS_WR_END"); return SI_SM_CALL_WITH_DELAY; } /* data register holds an error code */ data = read_smic_data(smic); if (data != 0) { if (smic_debug & SMIC_DEBUG_ENABLE) printk(KERN_DEBUG "SMIC_WRITE_END: data = %02x\n", data); start_error_recovery(smic, "state = SMIC_WRITE_END, " "data != SUCCESS"); return SI_SM_CALL_WITH_DELAY; } else smic->state = SMIC_WRITE2READ; break; case SMIC_WRITE2READ: /* * we must wait for RX_DATA_READY to be set before we * can continue */ if (flags & SMIC_RX_DATA_READY) { write_smic_control(smic, SMIC_CC_SMS_RD_START); write_smic_flags(smic, flags | SMIC_FLAG_BSY); smic->state = SMIC_READ_START; } else return SI_SM_CALL_WITH_DELAY; break; case SMIC_READ_START: if (status != SMIC_SC_SMS_RD_START) { start_error_recovery(smic, "state = SMIC_READ_START, " "status != SMIC_SC_SMS_RD_START"); return SI_SM_CALL_WITH_DELAY; } if (flags & SMIC_RX_DATA_READY) { read_next_byte(smic); write_smic_control(smic, SMIC_CC_SMS_RD_NEXT); write_smic_flags(smic, flags | SMIC_FLAG_BSY); smic->state = SMIC_READ_NEXT; } else return SI_SM_CALL_WITH_DELAY; break; case SMIC_READ_NEXT: switch (status) { /* * smic tells us that this is the last byte to be read * --> clean up */ case SMIC_SC_SMS_RD_END: read_next_byte(smic); write_smic_control(smic, SMIC_CC_SMS_RD_END); write_smic_flags(smic, flags | SMIC_FLAG_BSY); smic->state = SMIC_READ_END; break; case SMIC_SC_SMS_RD_NEXT: if (flags & SMIC_RX_DATA_READY) { read_next_byte(smic); write_smic_control(smic, SMIC_CC_SMS_RD_NEXT); write_smic_flags(smic, flags | SMIC_FLAG_BSY); smic->state = SMIC_READ_NEXT; } else return SI_SM_CALL_WITH_DELAY; break; default: start_error_recovery( smic, "state = SMIC_READ_NEXT, " "status != SMIC_SC_SMS_RD_(NEXT|END)"); return SI_SM_CALL_WITH_DELAY; } break; case SMIC_READ_END: if (status != SMIC_SC_SMS_READY) { start_error_recovery(smic, "state = SMIC_READ_END, " "status != SMIC_SC_SMS_READY"); return SI_SM_CALL_WITH_DELAY; } data = read_smic_data(smic); /* data register holds an error code */ if (data != 0) { if (smic_debug & SMIC_DEBUG_ENABLE) printk(KERN_DEBUG "SMIC_READ_END: data = %02x\n", data); start_error_recovery(smic, "state = SMIC_READ_END, " "data != SUCCESS"); return SI_SM_CALL_WITH_DELAY; } else { smic->state = SMIC_IDLE; return SI_SM_TRANSACTION_COMPLETE; } case SMIC_HOSED: init_smic_data(smic, smic->io); return SI_SM_HOSED; default: if (smic_debug & SMIC_DEBUG_ENABLE) { printk(KERN_DEBUG "smic->state = %d\n", smic->state); start_error_recovery(smic, "state = UNKNOWN"); return SI_SM_CALL_WITH_DELAY; } } smic->smic_timeout = SMIC_RETRY_TIMEOUT; return SI_SM_CALL_WITHOUT_DELAY; }