/* * This function should be called during kernel startup to initialize * the machine vector table. */ void __init init_IRQ(void) { int i; /* set up the vectors */ for (i = 72; i < 256; ++i) _ramvec[i] = (e_vector) bad_interrupt; _ramvec[32] = system_call; _ramvec[65] = (e_vector) inthandler1; _ramvec[66] = (e_vector) inthandler2; _ramvec[67] = (e_vector) inthandler3; _ramvec[68] = (e_vector) inthandler4; _ramvec[69] = (e_vector) inthandler5; _ramvec[70] = (e_vector) inthandler6; _ramvec[71] = (e_vector) inthandler7; IVR = 0x40; /* Set DragonBall IVR (interrupt base) to 64 */ /* turn off all interrupts */ IMR = ~0; for (i = 0; (i < NR_IRQS); i++) { set_irq_chip(i, &intc_irq_chip); set_irq_handler(i, handle_level_irq); } }
static int __init mxc_pseudo_init(void) { int i; /* disable the interrupt and clear the status */ pseudo_irq_pending = 0; pseudo_irq_enable = 0; pr_info("3-Stack Pseudo interrupt rev=0.1v\n"); for (i = MXC_PSEUDO_IO_BASE; i < (MXC_PSEUDO_IO_BASE + 16); i++) { set_irq_chip(i, &pseudo_irq_chip); set_irq_handler(i, handle_simple_irq); set_irq_flags(i, IRQF_VALID); } set_irq_flags(MXC_PSEUDO_PARENT, IRQF_NOAUTOEN); set_irq_handler(MXC_PSEUDO_PARENT, mxc_pseudo_irq_handler); /* Set and install PMIC IRQ handler */ gpio_request(0, NULL); gpio_direction_input(0); set_irq_type(gpio_to_irq(0), IRQF_TRIGGER_RISING); if (request_irq(gpio_to_irq(0), mcu_irq_handler, 0, "MCU_IRQ", 0)) { printk(KERN_ERR "mcu request irq failed\n"); return -1; } return 0; }
void set_irq_chip_and_handler_name(unsigned int irq, struct irq_chip *chip, irq_flow_handler_t handle, const char *name) { set_irq_chip(irq, chip); __set_irq_handler(irq, handle, 0, name); }
void __init ts4800_init_mux_irq(void) { int n; volatile unsigned long x; volatile unsigned long *iomuxregs = (volatile unsigned long *)(AIPS1_BASE_ADDR_VIRT + 0x000A8000); gpioregs = (volatile unsigned long *)(AIPS1_BASE_ADDR_VIRT + 0x00088000); FPGA_REG(FPGA_IRQ_MASK_OFFSET) = 0xFFFF; /* mask all */ /* * On the TS-4800, the FPGA interrupt is connected to EIM_D27 on * the MX515. This pin must be configured as a GPIO pin, by writing * 001b to the MUX_MODE bits of the IOMUXC_SW_MUX_CTL_PAD_EIM_D27 * register. Doing so makes this pin EIM_GPIO2_9. */ iomuxregs[0x88 / 4] = 1; gpioregs[0x18 / 4] = (1<<9); // clr status for irq 169 for(n=272; n < 280; n++) { set_irq_chip(n, &muxed_irq_chip); set_irq_handler(n, handle_simple_irq); set_irq_flags(n, IRQF_VALID); } /* Install mux handler on GPIO2_9, which is IRQ #169 */ set_irq_chained_handler(169, mux_irq_handler); }
int sapphire_init_gpio(void) { int i; if (!machine_is_sapphire()) return 0; DBG("%d,%d\r\n",SAPPHIRE_INT_START, SAPPHIRE_INT_END); DBG("NR_MSM_IRQS=%d, NR_GPIO_IRQS=%d\r\n", NR_MSM_IRQS, NR_GPIO_IRQS); for(i = SAPPHIRE_INT_START; i <= SAPPHIRE_INT_END; i++) { set_irq_chip(i, &sapphire_gpio_irq_chip); set_irq_handler(i, handle_edge_irq); set_irq_flags(i, IRQF_VALID); } register_gpio_chip(&sapphire_gpio_chip); register_gpio_chip(&sapphire_h2w_gpio_chip); /*setup CPLD INT connecting to SOC's gpio 17 */ set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); set_irq_chained_handler(MSM_GPIO_TO_INT(17), sapphire_gpio_irq_handler); set_irq_wake(MSM_GPIO_TO_INT(17), 1); if(sysdev_class_register(&sapphire_sysdev_class) == 0) sysdev_register(&sapphire_irq_device); return 0; }
void __init omap_init_irq(void) { unsigned long nr_irqs = 0; unsigned int nr_banks = 0; int i; for (i = 0; i < ARRAY_SIZE(irq_banks); i++) { struct omap_irq_bank *bank = irq_banks + i; if (cpu_is_omap24xx()) { bank->base_reg = IO_ADDRESS(OMAP24XX_IC_BASE); } if (cpu_is_omap34xx()) { bank->base_reg = VA_IC_BASE; } omap_irq_bank_init_one(bank); nr_irqs += bank->nr_irqs; nr_banks++; } printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n", nr_irqs, nr_banks, nr_banks > 1 ? "s" : ""); for (i = 0; i < nr_irqs; i++) { set_irq_chip(i, &omap_irq_chip); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } }
/* * This function initializes the AVIC hardware and disables all the * interrupts. It registers the interrupt enable and disable functions * to the kernel for each interrupt source. */ void __init mxc_init_irq(void) { int i; u32 reg; /* put the AVIC into the reset value with * all interrupts disabled */ __raw_writel(0, AVIC_INTCNTL); __raw_writel(0x1f, AVIC_NIMASK); /* disable all interrupts */ __raw_writel(0, AVIC_INTENABLEH); __raw_writel(0, AVIC_INTENABLEL); /* all IRQ no FIQ */ __raw_writel(0, AVIC_INTTYPEH); __raw_writel(0, AVIC_INTTYPEL); for (i = 0; i < MXC_MAX_INT_LINES; i++) { set_irq_chip(i, &mxc_avic_chip); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } /* Set WDOG2's interrupt the highest priority level (bit 28-31) */ reg = __raw_readl(AVIC_NIPRIORITY6); reg |= (0xF << 28); __raw_writel(reg, AVIC_NIPRIORITY6); /* init architectures chained interrupt handler */ mxc_register_gpios(); printk(KERN_INFO "MXC IRQ initialized\n"); }
void __init epxa10db_init_irq(void) { unsigned int i; request_resource(&iomem_resource, &irq_resource); /* * This bit sets up the interrupt controller using * the 6 PLD interrupts mode (the default) each * irqs is assigned a priority which is the same * as its interrupt number. This scheme is used because * its easy, but you may want to change it depending * on the contents of your PLD */ writel(3,INT_MODE(IO_ADDRESS(EXC_INT_CTRL00_BASE))); for (i = 0; i < NR_IRQS; i++){ writel(i+1, INT_PRIORITY_P0(IO_ADDRESS(EXC_INT_CTRL00_BASE)) + (4*i)); set_irq_chip(i,&epxa_irq_chip); set_irq_handler(i,do_level_IRQ); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } /* Disable all interrupts */ writel(-1,INT_MC(IO_ADDRESS(EXC_INT_CTRL00_BASE))); }
void __init mips_cpu_irq_init(void) { int irq_base = MIPS_CPU_IRQ_BASE; int i; /* Mask interrupts. */ clear_c0_status(ST0_IM); clear_c0_cause(CAUSEF_IP); /* * Only MT is using the software interrupts currently, so we just * leave them uninitialized for other processors. */ if (cpu_has_mipsmt) for (i = irq_base; i < irq_base + 2; i++) set_irq_chip(i, &mips_mt_cpu_irq_controller); #if defined(CONFIG_BMIPS4380) || defined(CONFIG_BMIPS5000) /* set up SW IRQs for SMP */ for (i = irq_base; i < irq_base + 8; i++) #else for (i = irq_base + 2; i < irq_base + 8; i++) #endif set_irq_chip_and_handler(i, &mips_cpu_irq_controller, handle_percpu_irq); }
void __init ixp23xx_init_irq(void) { int irq; /* Route everything to IRQ */ *IXP23XX_INTR_SEL1 = 0x0; *IXP23XX_INTR_SEL2 = 0x0; *IXP23XX_INTR_SEL3 = 0x0; *IXP23XX_INTR_SEL4 = 0x0; /* Mask all sources */ *IXP23XX_INTR_EN1 = 0x0; *IXP23XX_INTR_EN2 = 0x0; *IXP23XX_INTR_EN3 = 0x0; *IXP23XX_INTR_EN4 = 0x0; /* * Configure all IRQs for level-sensitive operation */ for (irq = 0; irq <= NUM_IXP23XX_RAW_IRQS; irq++) { ixp23xx_config_irq(irq, IXP23XX_IRQ_LEVEL); } for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { set_irq_chip(irq, &ixp23xx_pci_irq_chip); set_irq_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); }
void __init gic_dist_init(unsigned int gic_nr, void __iomem *base, unsigned int irq_start) { unsigned int max_irq; unsigned int i; if (gic_nr >= MAX_GIC_NR) BUG(); gic_data[gic_nr].dist_base = base; gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31; max_irq = _gic_dist_init(gic_nr); gic_data[gic_nr].max_irq = max_irq; /* * Setup the Linux IRQ subsystem. */ for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) { set_irq_chip(i, &gic_chip); set_irq_chip_data(i, &gic_data[gic_nr]); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } writel(1, base + GIC_DIST_CTRL); }
static __init int bast_irq_init(void) { unsigned int i; if (machine_is_bast()) { printk(KERN_INFO "BAST PC104 IRQ routing, Copyright 2005 Simtec Electronics\n"); /* zap all the IRQs */ __raw_writeb(0x0, BAST_VA_PC104_IRQMASK); set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux); /* register our IRQs */ for (i = 0; i < 4; i++) { unsigned int irqno = bast_pc104_irqs[i]; set_irq_chip(irqno, &bast_pc104_chip); set_irq_handler(irqno, handle_level_irq); set_irq_flags(irqno, IRQF_VALID); } } return 0; }
void __init s3c3410_init_irq(void) { int irq; for (irq = 0; irq < NR_IRQS; irq++) { set_irq_chip(irq, &s3c3410_chip); set_irq_handler(irq, do_level_IRQ); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); } /* mask and disable all further interrupts */ outl(0x00000000, S3C3410X_INTMSK); /* set all to IRQ mode, not FIQ */ outl(0x00000000, S3C3410X_INTMOD); /* Clear Intrerrupt pending register */ outl(0x00000000, S3C3410X_INTPND); /* * enable the gloabal interrupt flag, this should be * safe now, all sources are masked out and acknowledged */ outb(inb(S3C3410X_SYSCON) | S3C3410X_SYSCON_GIE, S3C3410X_SYSCON); }
static int __init msm_init_gpio(void) { int i, j = 0; for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) { if (i - FIRST_GPIO_IRQ > msm_gpio_chips[j].chip.end) { if (j < ARRAY_SIZE(msm_gpio_chips) - 1) j++; } set_irq_chip_data(i, &msm_gpio_chips[j]); set_irq_chip(i, &msm_gpio_irq_chip); set_irq_handler(i, handle_edge_irq); set_irq_flags(i, IRQF_VALID); } for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { writel(0, msm_gpio_chips[i].regs.int_en); register_gpio_chip(&msm_gpio_chips[i].chip); } set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); set_irq_wake(INT_GPIO_GROUP1, 1); set_irq_wake(INT_GPIO_GROUP2, 2); return 0; }
void __init gemini_init_irq(void) { unsigned int i, mode = 0, level = 0; disable_hlt(); request_resource(&iomem_resource, &irq_resource); for (i = 0; i < NR_IRQS; i++) { set_irq_chip(i, &gemini_irq_chip); if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) { set_irq_handler(i, handle_edge_irq); mode |= 1 << i; level |= 1 << i; } else { set_irq_handler(i, handle_level_irq); } set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } __raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); __raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); __raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); __raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); }
void __init ixp4xx_init_irq(void) { int i = 0; *IXP4XX_ICLR = 0x0; *IXP4XX_ICMR = 0x0; if (cpu_is_ixp46x() || cpu_is_ixp43x()) { *IXP4XX_ICLR2 = 0x00; *IXP4XX_ICMR2 = 0x00; } for(i = 0; i < NR_IRQS; i++) { set_irq_chip(i, &ixp4xx_irq_chip); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } }
void __init msm_init_irq(void) { unsigned n; /* select level interrupts */ writel(0, VIC_INT_TYPE0); writel(0, VIC_INT_TYPE1); /* select highlevel interrupts */ writel(0, VIC_INT_POLARITY0); writel(0, VIC_INT_POLARITY1); /* select IRQ for all INTs */ writel(0, VIC_INT_SELECT0); writel(0, VIC_INT_SELECT1); /* disable all INTs */ writel(0, VIC_INT_EN0); writel(0, VIC_INT_EN1); /* don't use 1136 vic */ writel(0, VIC_CONFIG); /* enable interrupt controller */ writel(1, VIC_INT_MASTEREN); for (n = 0; n < NR_MSM_IRQS; n++) { set_irq_chip(n, &msm_irq_chip); set_irq_handler(n, handle_level_irq); set_irq_flags(n, IRQF_VALID); } }
void __init kirkwood_init_irq(void) { int i; orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF)); orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF)); /* * Mask and clear GPIO IRQ interrupts. */ writel(0, GPIO_LEVEL_MASK(0)); writel(0, GPIO_EDGE_MASK(0)); writel(0, GPIO_EDGE_CAUSE(0)); writel(0, GPIO_LEVEL_MASK(32)); writel(0, GPIO_EDGE_MASK(32)); writel(0, GPIO_EDGE_CAUSE(32)); for (i = IRQ_KIRKWOOD_GPIO_START; i < NR_IRQS; i++) { set_irq_chip(i, &orion_gpio_irq_chip); set_irq_handler(i, handle_level_irq); irq_desc[i].status |= IRQ_LEVEL; set_irq_flags(i, IRQF_VALID); } set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler); }
static int pci_pic_host_map(struct irq_host *h, unsigned int virq, irq_hw_number_t hw) { get_irq_desc(virq)->status |= IRQ_LEVEL; set_irq_chip(virq, &m82xx_pci_ic); return 0; }
static void __init gic_basic_init(void) { unsigned int i, cpu; /* Setup defaults */ for (i = 0; i < GIC_NUM_INTRS; i++) { GIC_SET_POLARITY(i, GIC_POL_POS); GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL); GIC_SET_INTR_MASK(i, 0); } /* Setup specifics */ for (i = 0; i < _mapsize; i++) { cpu = _intrmap[i].cpunum; if (cpu == X) continue; setup_intr(_intrmap[i].intrnum, _intrmap[i].cpunum, _intrmap[i].pin, _intrmap[i].polarity, _intrmap[i].trigtype); /* Initialise per-cpu Interrupt software masks */ if (_intrmap[i].ipiflag) set_bit(_intrmap[i].intrnum, pcpu_masks[cpu].pcpu_mask); } vpe_local_setup(numvpes); for (i = _irqbase; i < (_irqbase + numintrs); i++) set_irq_chip(i, &gic_irq_controller); }
void __init versatile_init_irq(void) { unsigned int i; vic_init(VA_VIC_BASE, IRQ_VIC_START, ~0); set_irq_chained_handler(IRQ_VICSOURCE31, sic_handle_irq); /* Do second interrupt controller */ writel(~0, VA_SIC_BASE + SIC_IRQ_ENABLE_CLEAR); for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) { if ((PIC_MASK & (1 << (i - IRQ_SIC_START))) == 0) { set_irq_chip(i, &sic_chip); set_irq_handler(i, do_level_IRQ); set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } } /* * Interrupts on secondary controller from 0 to 8 are routed to * source 31 on PIC. * Interrupts from 21 to 31 are routed directly to the VIC on * the corresponding number on primary controller. This is controlled * by setting PIC_ENABLEx. */ writel(PIC_MASK, VA_SIC_BASE + SIC_INT_PIC_ENABLE); }
static int __init syncpt_init_irq(void) { void __iomem *sync_regs; unsigned int i; int irq; sync_regs = ioremap(TEGRA_HOST1X_BASE + HOST1X_SYNC_OFFSET, HOST1X_SYNC_SIZE); BUG_ON(!sync_regs); writel(0xffffffffUL, sync_regs + HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE); writel(0xffffffffUL, sync_regs + HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS); for (i = 0; i < INT_SYNCPT_THRESH_NR; i++) { irq = INT_SYNCPT_THRESH_BASE + i; set_irq_chip(irq, &syncpt_thresh_irq); set_irq_chip_data(irq, sync_regs); set_irq_handler(irq, handle_simple_irq); set_irq_flags(irq, IRQF_VALID); } if (set_irq_data(INT_HOST1X_MPCORE_SYNCPT, sync_regs)) BUG(); set_irq_chained_handler(INT_HOST1X_MPCORE_SYNCPT, syncpt_thresh_cascade); return 0; }
/* * We only do anything if we are the master NPU on the board. * The slave NPU only has the ethernet chip going directly to * the PCIB interrupt input. */ void __init ixdp2x01_init_irq(void) { int irq = 0; /* initialize chip specific interrupts */ ixp2000_init_irq(); if (machine_is_ixdp2401()) valid_irq_mask = IXDP2401_VALID_IRQ_MASK; else valid_irq_mask = IXDP2801_VALID_IRQ_MASK; /* Mask all interrupts from CPLD, disable simulation */ ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff); ixp2000_reg_write(IXDP2X01_INT_SIM_REG, 0); for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { if (irq & valid_irq_mask) { set_irq_chip(irq, &ixdp2x01_irq_chip); set_irq_handler(irq, do_level_IRQ); set_irq_flags(irq, IRQF_VALID); } else { set_irq_flags(irq, 0); } } /* Hook into PCI interrupts */ set_irq_chained_handler(IRQ_IXP2000_PCIB, &ixdp2x01_irq_handler); }
void __init gemini_init_irq(void) { unsigned int i, mode = 0, level = 0; /* * Disable arch_idle() by default since it is buggy * For more info see arch/arm/mach-gemini/include/mach/system.h */ disable_hlt(); request_resource(&iomem_resource, &irq_resource); for (i = 0; i < NR_IRQS; i++) { set_irq_chip(i, &gemini_irq_chip); if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) { set_irq_handler(i, handle_edge_irq); mode |= 1 << i; level |= 1 << i; } else { set_irq_handler(i, handle_level_irq); } set_irq_flags(i, IRQF_VALID | IRQF_PROBE); } /* Disable all interrupts */ __raw_writel(0, IRQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); __raw_writel(0, FIQ_MASK(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); /* Set interrupt mode */ __raw_writel(mode, IRQ_TMODE(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); __raw_writel(level, IRQ_TLEVEL(IO_ADDRESS(GEMINI_INTERRUPT_BASE))); }
/* call this from board-specific init_irq */ void __init at91_gpio_irq_setup(unsigned banks) { unsigned pioc, pin, id; if (banks > 4) banks = 4; for (pioc = 0, pin = PIN_BASE, id = AT91C_ID_PIOA; pioc < banks; pioc++, id++) { struct pio_controller __iomem *controller; unsigned i; controller = (void __force __iomem *) pio_virt[pioc]; __raw_writel(~0, &controller->idr); set_irq_data(id, (void *) pin); set_irq_chipdata(id, (void __force *) controller); for (i = 0; i < 32; i++, pin++) { set_irq_chip(pin, &gpio_irqchip); set_irq_handler(pin, do_simple_IRQ); set_irq_flags(pin, IRQF_VALID); } set_irq_chained_handler(id, gpio_irq_handler); /* enable the PIO peripheral clock */ AT91_SYS->PMC_PCER = 1 << id; } pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, banks); }
void __init pxa_init_irq(int irq_nr, set_wake_t fn) { int irq, i; pxa_internal_irq_nr = irq_nr; for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq += 32) { _ICMR(irq) = 0; /* disable all IRQs */ _ICLR(irq) = 0; /* all IRQs are IRQ, not FIQ */ } /* initialize interrupt priority */ if (cpu_is_pxa27x() || cpu_is_pxa3xx()) { for (i = 0; i < irq_nr; i++) IPR(i) = i | (1 << 31); } /* only unmasked interrupts kick us out of idle */ ICCR = 1; for (irq = PXA_IRQ(0); irq < PXA_IRQ(irq_nr); irq++) { set_irq_chip(irq, &pxa_internal_irq_chip); set_irq_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } pxa_internal_irq_chip.set_wake = fn; pxa_init_low_gpio_irq(fn); }
void set_irq_chip_and_handler(unsigned int irq, struct irq_chip *chip, irq_flow_handler_t handle) { set_irq_chip(irq, chip); __set_irq_handler(irq, handle, 0, NULL); }
static int __init _mxc_expio_init(void) { int i; initialized = 1; printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n"); /* * Configure INT line as GPIO input */ mxc_request_iomux(MX31_PIN_GPIO1_4, OUTPUTCONFIG_GPIO, INPUTCONFIG_GPIO); mxc_set_gpio_direction(MX31_PIN_GPIO1_4, 1); /* disable the interrupt and clear the status */ __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG); __raw_writew(0xFFFF, PBC_INTSTATUS_REG); for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); i++) { set_irq_chip(i, &expio_irq_chip); set_irq_handler(i, handle_level_irq); set_irq_flags(i, IRQF_VALID); } set_irq_type(EXPIO_PARENT_INT, IRQT_HIGH); set_irq_chained_handler(EXPIO_PARENT_INT, mxc_expio_irq_handler); return 0; }
void __init lh7a40x_init_board_irq (void) { int irq; for (irq = IRQ_KEV7A400_CPLD; irq < IRQ_KEV7A400_CPLD + NR_IRQ_BOARD; ++irq) { set_irq_chip (irq, &kev7a400_cpld_chip); set_irq_handler (irq, handle_edge_irq); set_irq_flags (irq, IRQF_VALID); } set_irq_chained_handler (IRQ_CPLD, kev7a400_cpld_handler); /* Clear all CPLD interrupts */ CPLD_CL_INT = 0xff; /* CPLD_INTR_MMC_CD | CPLD_INTR_ETH_INT; */ GPIO_GPIOINTEN = 0; /* Disable all GPIO interrupts */ barrier(); #if 0 GPIO_INTTYPE1 = (GPIO_INTR_PCC1_CD | GPIO_INTR_PCC1_CD); /* Edge trig. */ GPIO_INTTYPE2 = 0; /* Falling edge & low-level */ GPIO_GPIOFEOI = 0xff; /* Clear all GPIO interrupts */ GPIO_GPIOINTEN = 0xff; /* Enable all GPIO interrupts */ init_FIQ(); #endif }
int __init s5p_init_irq_eint(void) { int irq; for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++) set_irq_chip(irq, &s5p_irq_vic_eint); for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) { set_irq_chip(irq, &s5p_irq_eint); set_irq_handler(irq, handle_level_irq); set_irq_flags(irq, IRQF_VALID); } set_irq_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31); return 0; }