static void si_blit(struct pipe_context *ctx,
const struct pipe_blit_info *info)
{
struct si_context *sctx = (struct si_context*)ctx;
if (do_hardware_msaa_resolve(ctx, info)) {
return;
}
assert(util_blitter_is_blit_supported(sctx->blitter, info));
/* The driver doesn't decompress resources automatically while
* u_blitter is rendering. */
si_decompress_subresource(ctx, info->src.resource, info->mask,
info->src.level,
info->src.box.z,
info->src.box.z + info->src.box.depth - 1);
if (sctx->screen->b.debug_flags & DBG_FORCE_DMA &&
util_try_blit_via_copy_region(ctx, info))
return;
si_blitter_begin(ctx, SI_BLIT |
(info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
util_blitter_blit(sctx->blitter, info);
si_blitter_end(ctx);
}
static boolean si_generate_mipmap(struct pipe_context *ctx,
struct pipe_resource *tex,
enum pipe_format format,
unsigned base_level, unsigned last_level,
unsigned first_layer, unsigned last_layer)
{
struct si_context *sctx = (struct si_context*)ctx;
struct r600_texture *rtex = (struct r600_texture *)tex;
if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
return false;
/* The driver doesn't decompress resources automatically while
* u_blitter is rendering. */
si_decompress_subresource(ctx, tex, PIPE_MASK_RGBAZS,
base_level, first_layer, last_layer);
/* Clear dirty_level_mask for the levels that will be overwritten. */
assert(base_level < last_level);
rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
last_level - base_level);
si_blitter_begin(ctx, SI_BLIT | SI_DISABLE_RENDER_COND);
util_blitter_generate_mipmap(sctx->blitter, tex, format,
base_level, last_level,
first_layer, last_layer);
si_blitter_end(ctx);
return true;
}
static void si_pipe_clear_buffer(struct pipe_context *ctx,
struct pipe_resource *dst,
unsigned offset, unsigned size,
const void *clear_value_ptr,
int clear_value_size)
{
struct si_context *sctx = (struct si_context*)ctx;
uint32_t dword_value;
unsigned i;
assert(offset % clear_value_size == 0);
assert(size % clear_value_size == 0);
if (clear_value_size > 4) {
const uint32_t *u32 = clear_value_ptr;
bool clear_dword_duplicated = true;
/* See if we can lower large fills to dword fills. */
for (i = 1; i < clear_value_size / 4; i++)
if (u32[0] != u32[i]) {
clear_dword_duplicated = false;
break;
}
if (!clear_dword_duplicated) {
/* Use transform feedback for 64-bit, 96-bit, and
* 128-bit fills.
*/
union pipe_color_union clear_value;
memcpy(&clear_value, clear_value_ptr, clear_value_size);
si_blitter_begin(ctx, SI_DISABLE_RENDER_COND);
util_blitter_clear_buffer(sctx->blitter, dst, offset,
size, clear_value_size / 4,
&clear_value);
si_blitter_end(ctx);
return;
}
}
/* Expand the clear value to a dword. */
switch (clear_value_size) {
case 1:
dword_value = *(uint8_t*)clear_value_ptr;
dword_value |= (dword_value << 8) |
(dword_value << 16) |
(dword_value << 24);
break;
case 2:
dword_value = *(uint16_t*)clear_value_ptr;
dword_value |= dword_value << 16;
break;
default:
dword_value = *(uint32_t*)clear_value_ptr;
}
sctx->b.clear_buffer(ctx, dst, offset, size, dword_value,
R600_COHERENCY_SHADER);
}
static void si_blit_decompress_depth_in_place(struct si_context *sctx,
struct r600_texture *texture,
bool is_stencil_sampler,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer)
{
struct pipe_surface *zsurf, surf_tmpl = {{0}};
unsigned layer, max_layer, checked_last_layer, level;
unsigned *dirty_level_mask;
if (is_stencil_sampler) {
sctx->db_flush_stencil_inplace = true;
dirty_level_mask = &texture->stencil_dirty_level_mask;
} else {
sctx->db_flush_depth_inplace = true;
dirty_level_mask = &texture->dirty_level_mask;
}
si_mark_atom_dirty(sctx, &sctx->db_render_state);
surf_tmpl.format = texture->resource.b.b.format;
for (level = first_level; level <= last_level; level++) {
if (!(*dirty_level_mask & (1 << level)))
continue;
surf_tmpl.u.tex.level = level;
/* The smaller the mipmap level, the less layers there are
* as far as 3D textures are concerned. */
max_layer = util_max_layer(&texture->resource.b.b, level);
checked_last_layer = last_layer < max_layer ? last_layer : max_layer;
for (layer = first_layer; layer <= checked_last_layer; layer++) {
surf_tmpl.u.tex.first_layer = layer;
surf_tmpl.u.tex.last_layer = layer;
zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
sctx->custom_dsa_flush,
1.0f);
si_blitter_end(&sctx->b.b);
pipe_surface_reference(&zsurf, NULL);
}
/* The texture will always be dirty if some layers aren't flushed.
* I don't think this case occurs often though. */
if (first_layer == 0 && last_layer == max_layer) {
*dirty_level_mask &= ~(1 << level);
}
}
sctx->db_flush_depth_inplace = false;
sctx->db_flush_stencil_inplace = false;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
}
static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
const struct pipe_blit_info *info)
{
struct si_context *sctx = (struct si_context*)ctx;
struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
enum pipe_format format = int_to_norm_format(info->dst.format);
unsigned sample_mask = ~0;
/* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
* the format is R16G16. Use R16A16, which does work.
*/
if (format == PIPE_FORMAT_R16G16_UNORM)
format = PIPE_FORMAT_R16A16_UNORM;
if (format == PIPE_FORMAT_R16G16_SNORM)
format = PIPE_FORMAT_R16A16_SNORM;
if (info->src.resource->nr_samples > 1 &&
info->dst.resource->nr_samples <= 1 &&
util_max_layer(info->src.resource, 0) == 0 &&
util_max_layer(info->dst.resource, info->dst.level) == 0 &&
util_is_format_compatible(util_format_description(info->src.format),
util_format_description(info->dst.format)) &&
!util_format_is_pure_integer(format) &&
!util_format_is_depth_or_stencil(format) &&
!info->scissor_enable &&
(info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
dst_width == info->src.resource->width0 &&
dst_height == info->src.resource->height0 &&
info->dst.box.x == 0 &&
info->dst.box.y == 0 &&
info->dst.box.width == dst_width &&
info->dst.box.height == dst_height &&
info->dst.box.depth == 1 &&
info->src.box.x == 0 &&
info->src.box.y == 0 &&
info->src.box.width == dst_width &&
info->src.box.height == dst_height &&
info->src.box.depth == 1 &&
dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
!(dst->surface.flags & RADEON_SURF_SCANOUT) &&
(!dst->cmask.size || !dst->dirty_level_mask) && /* dst cannot be fast-cleared */
!dst->dcc_offset) {
si_blitter_begin(ctx, SI_COLOR_RESOLVE |
(info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
util_blitter_custom_resolve_color(sctx->blitter,
info->dst.resource, info->dst.level,
info->dst.box.z,
info->src.resource, info->src.box.z,
sample_mask, sctx->custom_blend_resolve,
format);
si_blitter_end(ctx);
return true;
}
return false;
}
static void si_blit_decompress_color(struct pipe_context *ctx,
struct r600_texture *rtex,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer,
bool need_dcc_decompress)
{
struct si_context *sctx = (struct si_context *)ctx;
void* custom_blend;
unsigned layer, checked_last_layer, max_layer;
unsigned level_mask =
u_bit_consecutive(first_level, last_level - first_level + 1);
if (!need_dcc_decompress)
level_mask &= rtex->dirty_level_mask;
if (!level_mask)
return;
if (rtex->dcc_offset && need_dcc_decompress) {
custom_blend = sctx->custom_blend_dcc_decompress;
} else if (rtex->fmask.size) {
custom_blend = sctx->custom_blend_decompress;
} else {
custom_blend = sctx->custom_blend_fastclear;
}
while (level_mask) {
unsigned level = u_bit_scan(&level_mask);
/* The smaller the mipmap level, the less layers there are
* as far as 3D textures are concerned. */
max_layer = util_max_layer(&rtex->resource.b.b, level);
checked_last_layer = MIN2(last_layer, max_layer);
for (layer = first_layer; layer <= checked_last_layer; layer++) {
struct pipe_surface *cbsurf, surf_tmpl;
surf_tmpl.format = rtex->resource.b.b.format;
surf_tmpl.u.tex.level = level;
surf_tmpl.u.tex.first_layer = layer;
surf_tmpl.u.tex.last_layer = layer;
cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
si_blitter_begin(ctx, SI_DECOMPRESS);
util_blitter_custom_color(sctx->blitter, cbsurf, custom_blend);
si_blitter_end(ctx);
pipe_surface_reference(&cbsurf, NULL);
}
/* The texture will always be dirty if some layers aren't flushed.
* I don't think this case occurs often though. */
if (first_layer == 0 && last_layer == max_layer) {
rtex->dirty_level_mask &= ~(1 << level);
}
}
}
static void si_clear_render_target(struct pipe_context *ctx,
struct pipe_surface *dst,
const union pipe_color_union *color,
unsigned dstx, unsigned dsty,
unsigned width, unsigned height)
{
struct si_context *sctx = (struct si_context *)ctx;
si_blitter_begin(ctx, SI_CLEAR_SURFACE);
util_blitter_clear_render_target(sctx->blitter, dst, color,
dstx, dsty, width, height);
si_blitter_end(ctx);
}
static void si_clear_depth_stencil(struct pipe_context *ctx,
struct pipe_surface *dst,
unsigned clear_flags,
double depth,
unsigned stencil,
unsigned dstx, unsigned dsty,
unsigned width, unsigned height)
{
struct si_context *sctx = (struct si_context *)ctx;
si_blitter_begin(ctx, SI_CLEAR_SURFACE);
util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
dstx, dsty, width, height);
si_blitter_end(ctx);
}
static void si_clear_depth_stencil(struct pipe_context *ctx,
struct pipe_surface *dst,
unsigned clear_flags,
double depth,
unsigned stencil,
unsigned dstx, unsigned dsty,
unsigned width, unsigned height,
bool render_condition_enabled)
{
struct si_context *sctx = (struct si_context *)ctx;
si_blitter_begin(sctx, SI_CLEAR_SURFACE |
(render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
util_blitter_clear_depth_stencil(sctx->blitter, dst, clear_flags, depth, stencil,
dstx, dsty, width, height);
si_blitter_end(sctx);
}
static void si_blit_decompress_color(struct pipe_context *ctx,
struct r600_texture *rtex,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer)
{
struct si_context *sctx = (struct si_context *)ctx;
unsigned layer, level, checked_last_layer, max_layer;
if (!rtex->dirty_level_mask)
return;
for (level = first_level; level <= last_level; level++) {
if (!(rtex->dirty_level_mask & (1 << level)))
continue;
/* The smaller the mipmap level, the less layers there are
* as far as 3D textures are concerned. */
max_layer = util_max_layer(&rtex->resource.b.b, level);
checked_last_layer = last_layer < max_layer ? last_layer : max_layer;
for (layer = first_layer; layer <= checked_last_layer; layer++) {
struct pipe_surface *cbsurf, surf_tmpl;
surf_tmpl.format = rtex->resource.b.b.format;
surf_tmpl.u.tex.level = level;
surf_tmpl.u.tex.first_layer = layer;
surf_tmpl.u.tex.last_layer = layer;
cbsurf = ctx->create_surface(ctx, &rtex->resource.b.b, &surf_tmpl);
si_blitter_begin(ctx, SI_DECOMPRESS);
util_blitter_custom_color(sctx->blitter, cbsurf,
rtex->fmask.size ? sctx->custom_blend_decompress :
sctx->custom_blend_fastclear);
si_blitter_end(ctx);
pipe_surface_reference(&cbsurf, NULL);
}
/* The texture will always be dirty if some layers aren't flushed.
* I don't think this case occurs often though. */
if (first_layer == 0 && last_layer == max_layer) {
rtex->dirty_level_mask &= ~(1 << level);
}
}
}
static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
const struct pipe_blit_info *info)
{
struct si_context *sctx = (struct si_context*)ctx;
struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
enum pipe_format format = int_to_norm_format(info->dst.format);
unsigned sample_mask = ~0;
if (info->src.resource->nr_samples > 1 &&
info->dst.resource->nr_samples <= 1 &&
util_max_layer(info->src.resource, 0) == 0 &&
util_max_layer(info->dst.resource, info->dst.level) == 0 &&
info->dst.format == info->src.format &&
!util_format_is_pure_integer(format) &&
!util_format_is_depth_or_stencil(format) &&
!info->scissor_enable &&
(info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
dst_width == info->src.resource->width0 &&
dst_height == info->src.resource->height0 &&
info->dst.box.x == 0 &&
info->dst.box.y == 0 &&
info->dst.box.width == dst_width &&
info->dst.box.height == dst_height &&
info->dst.box.depth == 1 &&
info->src.box.x == 0 &&
info->src.box.y == 0 &&
info->src.box.width == dst_width &&
info->src.box.height == dst_height &&
info->src.box.depth == 1 &&
dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
!(dst->surface.flags & RADEON_SURF_SCANOUT)) {
si_blitter_begin(ctx, SI_COLOR_RESOLVE);
util_blitter_custom_resolve_color(sctx->blitter,
info->dst.resource, info->dst.level,
info->dst.box.z,
info->src.resource, info->src.box.z,
sample_mask, sctx->custom_blend_resolve,
format);
si_blitter_end(ctx);
return true;
}
return false;
}
static void si_blit(struct pipe_context *ctx,
const struct pipe_blit_info *info)
{
struct si_context *sctx = (struct si_context*)ctx;
if (do_hardware_msaa_resolve(ctx, info)) {
return;
}
assert(util_blitter_is_blit_supported(sctx->blitter, info));
/* The driver doesn't decompress resources automatically while
* u_blitter is rendering. */
si_decompress_subresource(ctx, info->src.resource, info->src.level,
info->src.box.z,
info->src.box.z + info->src.box.depth - 1);
si_blitter_begin(ctx, SI_BLIT);
util_blitter_blit(sctx->blitter, info);
si_blitter_end(ctx);
}
static void si_clear_render_target(struct pipe_context *ctx,
struct pipe_surface *dst,
const union pipe_color_union *color,
unsigned dstx, unsigned dsty,
unsigned width, unsigned height,
bool render_condition_enabled)
{
struct si_context *sctx = (struct si_context *)ctx;
struct si_texture *sdst = (struct si_texture*)dst->texture;
if (dst->texture->nr_samples <= 1 && !sdst->dcc_offset) {
si_compute_clear_render_target(ctx, dst, color, dstx, dsty, width,
height, render_condition_enabled);
return;
}
si_blitter_begin(sctx, SI_CLEAR_SURFACE |
(render_condition_enabled ? 0 : SI_DISABLE_RENDER_COND));
util_blitter_clear_render_target(sctx->blitter, dst, color,
dstx, dsty, width, height);
si_blitter_end(sctx);
}
static void si_clear(struct pipe_context *ctx, unsigned buffers,
const union pipe_color_union *color,
double depth, unsigned stencil)
{
struct si_context *sctx = (struct si_context *)ctx;
struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
if (buffers & PIPE_CLEAR_COLOR) {
evergreen_do_fast_color_clear(&sctx->b, fb, &sctx->framebuffer.atom,
&buffers, color);
}
if (buffers & PIPE_CLEAR_COLOR) {
int i;
/* These buffers cannot use fast clear, make sure to disable expansion. */
for (i = 0; i < fb->nr_cbufs; i++) {
struct r600_texture *tex;
/* If not clearing this buffer, skip. */
if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
continue;
if (!fb->cbufs[i])
continue;
tex = (struct r600_texture *)fb->cbufs[i]->texture;
if (tex->fmask.size == 0)
tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
}
}
si_blitter_begin(ctx, SI_CLEAR);
util_blitter_clear(sctx->blitter, fb->width, fb->height,
util_framebuffer_get_num_layers(fb),
buffers, color, depth, stencil);
si_blitter_end(ctx);
}
/* Helper function for si_blit_decompress_zs_in_place.
*/
static void
si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
struct r600_texture *texture,
unsigned planes, unsigned level_mask,
unsigned first_layer, unsigned last_layer)
{
struct pipe_surface *zsurf, surf_tmpl = {{0}};
unsigned layer, max_layer, checked_last_layer;
unsigned fully_decompressed_mask = 0;
if (!level_mask)
return;
if (planes & PIPE_MASK_S)
sctx->db_flush_stencil_inplace = true;
if (planes & PIPE_MASK_Z)
sctx->db_flush_depth_inplace = true;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
surf_tmpl.format = texture->resource.b.b.format;
while (level_mask) {
unsigned level = u_bit_scan(&level_mask);
surf_tmpl.u.tex.level = level;
/* The smaller the mipmap level, the less layers there are
* as far as 3D textures are concerned. */
max_layer = util_max_layer(&texture->resource.b.b, level);
checked_last_layer = MIN2(last_layer, max_layer);
for (layer = first_layer; layer <= checked_last_layer; layer++) {
surf_tmpl.u.tex.first_layer = layer;
surf_tmpl.u.tex.last_layer = layer;
zsurf = sctx->b.b.create_surface(&sctx->b.b, &texture->resource.b.b, &surf_tmpl);
si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
util_blitter_custom_depth_stencil(sctx->blitter, zsurf, NULL, ~0,
sctx->custom_dsa_flush,
1.0f);
si_blitter_end(&sctx->b.b);
pipe_surface_reference(&zsurf, NULL);
}
/* The texture will always be dirty if some layers aren't flushed.
* I don't think this case occurs often though. */
if (first_layer == 0 && last_layer == max_layer) {
fully_decompressed_mask |= 1u << level;
}
}
if (planes & PIPE_MASK_Z)
texture->dirty_level_mask &= ~fully_decompressed_mask;
if (planes & PIPE_MASK_S)
texture->stencil_dirty_level_mask &= ~fully_decompressed_mask;
sctx->db_flush_depth_inplace = false;
sctx->db_flush_stencil_inplace = false;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
}
static unsigned
si_blit_dbcb_copy(struct si_context *sctx,
struct r600_texture *src,
struct r600_texture *dst,
unsigned planes, unsigned level_mask,
unsigned first_layer, unsigned last_layer,
unsigned first_sample, unsigned last_sample)
{
struct pipe_surface surf_tmpl = {{0}};
unsigned layer, sample, checked_last_layer, max_layer;
unsigned fully_copied_levels = 0;
if (planes & PIPE_MASK_Z)
sctx->dbcb_depth_copy_enabled = true;
if (planes & PIPE_MASK_S)
sctx->dbcb_stencil_copy_enabled = true;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
while (level_mask) {
unsigned level = u_bit_scan(&level_mask);
/* The smaller the mipmap level, the less layers there are
* as far as 3D textures are concerned. */
max_layer = util_max_layer(&src->resource.b.b, level);
checked_last_layer = MIN2(last_layer, max_layer);
surf_tmpl.u.tex.level = level;
for (layer = first_layer; layer <= checked_last_layer; layer++) {
struct pipe_surface *zsurf, *cbsurf;
surf_tmpl.format = src->resource.b.b.format;
surf_tmpl.u.tex.first_layer = layer;
surf_tmpl.u.tex.last_layer = layer;
zsurf = sctx->b.b.create_surface(&sctx->b.b, &src->resource.b.b, &surf_tmpl);
surf_tmpl.format = dst->resource.b.b.format;
cbsurf = sctx->b.b.create_surface(&sctx->b.b, &dst->resource.b.b, &surf_tmpl);
for (sample = first_sample; sample <= last_sample; sample++) {
if (sample != sctx->dbcb_copy_sample) {
sctx->dbcb_copy_sample = sample;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
}
si_blitter_begin(&sctx->b.b, SI_DECOMPRESS);
util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
sctx->custom_dsa_flush, 1.0f);
si_blitter_end(&sctx->b.b);
}
pipe_surface_reference(&zsurf, NULL);
pipe_surface_reference(&cbsurf, NULL);
}
if (first_layer == 0 && last_layer >= max_layer &&
first_sample == 0 && last_sample >= u_max_sample(&src->resource.b.b))
fully_copied_levels |= 1u << level;
}
sctx->dbcb_depth_copy_enabled = false;
sctx->dbcb_stencil_copy_enabled = false;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
return fully_copied_levels;
}
void si_resource_copy_region(struct pipe_context *ctx,
struct pipe_resource *dst,
unsigned dst_level,
unsigned dstx, unsigned dsty, unsigned dstz,
struct pipe_resource *src,
unsigned src_level,
const struct pipe_box *src_box)
{
struct si_context *sctx = (struct si_context *)ctx;
struct pipe_surface *dst_view, dst_templ;
struct pipe_sampler_view src_templ, *src_view;
unsigned dst_width, dst_height, src_width0, src_height0;
unsigned src_force_level = 0;
struct pipe_box sbox, dstbox;
/* Handle buffers first. */
if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
return;
}
assert(u_max_sample(dst) == u_max_sample(src));
/* The driver doesn't decompress resources automatically while
* u_blitter is rendering. */
si_decompress_subresource(ctx, src, PIPE_MASK_RGBAZS, src_level,
src_box->z, src_box->z + src_box->depth - 1);
dst_width = u_minify(dst->width0, dst_level);
dst_height = u_minify(dst->height0, dst_level);
src_width0 = src->width0;
src_height0 = src->height0;
util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
util_blitter_default_src_texture(&src_templ, src, src_level);
if (util_format_is_compressed(src->format) ||
util_format_is_compressed(dst->format)) {
unsigned blocksize = util_format_get_blocksize(src->format);
if (blocksize == 8)
src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
else
src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT; /* 128-bit block */
dst_templ.format = src_templ.format;
dst_width = util_format_get_nblocksx(dst->format, dst_width);
dst_height = util_format_get_nblocksy(dst->format, dst_height);
src_width0 = util_format_get_nblocksx(src->format, src_width0);
src_height0 = util_format_get_nblocksy(src->format, src_height0);
dstx = util_format_get_nblocksx(dst->format, dstx);
dsty = util_format_get_nblocksy(dst->format, dsty);
sbox.x = util_format_get_nblocksx(src->format, src_box->x);
sbox.y = util_format_get_nblocksy(src->format, src_box->y);
sbox.z = src_box->z;
sbox.width = util_format_get_nblocksx(src->format, src_box->width);
sbox.height = util_format_get_nblocksy(src->format, src_box->height);
sbox.depth = src_box->depth;
src_box = &sbox;
src_force_level = src_level;
} else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src) ||
/* also *8_SNORM has precision issues, use UNORM instead */
util_format_is_snorm8(src->format)) {
if (util_format_is_subsampled_422(src->format)) {
src_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
dst_templ.format = PIPE_FORMAT_R8G8B8A8_UINT;
dst_width = util_format_get_nblocksx(dst->format, dst_width);
src_width0 = util_format_get_nblocksx(src->format, src_width0);
dstx = util_format_get_nblocksx(dst->format, dstx);
sbox = *src_box;
sbox.x = util_format_get_nblocksx(src->format, src_box->x);
sbox.width = util_format_get_nblocksx(src->format, src_box->width);
src_box = &sbox;
} else {
unsigned blocksize = util_format_get_blocksize(src->format);
switch (blocksize) {
case 1:
dst_templ.format = PIPE_FORMAT_R8_UNORM;
src_templ.format = PIPE_FORMAT_R8_UNORM;
break;
case 2:
dst_templ.format = PIPE_FORMAT_R8G8_UNORM;
src_templ.format = PIPE_FORMAT_R8G8_UNORM;
break;
case 4:
dst_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
src_templ.format = PIPE_FORMAT_R8G8B8A8_UNORM;
break;
case 8:
dst_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT;
break;
case 16:
dst_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
src_templ.format = PIPE_FORMAT_R32G32B32A32_UINT;
break;
default:
fprintf(stderr, "Unhandled format %s with blocksize %u\n",
util_format_short_name(src->format), blocksize);
assert(0);
}
}
}
/* Initialize the surface. */
dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
dst_width, dst_height);
/* Initialize the sampler view. */
src_view = si_create_sampler_view_custom(ctx, src, &src_templ,
src_width0, src_height0,
src_force_level);
u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
abs(src_box->depth), &dstbox);
/* Copy. */
si_blitter_begin(ctx, SI_COPY);
util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
src_view, src_box, src_width0, src_height0,
PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL,
FALSE);
si_blitter_end(ctx);
pipe_surface_reference(&dst_view, NULL);
pipe_sampler_view_reference(&src_view, NULL);
}
static void si_clear(struct pipe_context *ctx, unsigned buffers,
const union pipe_color_union *color,
double depth, unsigned stencil)
{
struct si_context *sctx = (struct si_context *)ctx;
struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
struct pipe_surface *zsbuf = fb->zsbuf;
struct r600_texture *zstex =
zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
if (buffers & PIPE_CLEAR_COLOR) {
evergreen_do_fast_color_clear(&sctx->b, fb,
&sctx->framebuffer.atom, &buffers,
&sctx->framebuffer.dirty_cbufs,
color);
if (!buffers)
return; /* all buffers have been fast cleared */
}
if (buffers & PIPE_CLEAR_COLOR) {
int i;
/* These buffers cannot use fast clear, make sure to disable expansion. */
for (i = 0; i < fb->nr_cbufs; i++) {
struct r600_texture *tex;
/* If not clearing this buffer, skip. */
if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
continue;
if (!fb->cbufs[i])
continue;
tex = (struct r600_texture *)fb->cbufs[i]->texture;
if (tex->fmask.size == 0)
tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
}
}
if (zstex && zstex->htile_buffer &&
zsbuf->u.tex.level == 0 &&
zsbuf->u.tex.first_layer == 0 &&
zsbuf->u.tex.last_layer == util_max_layer(&zstex->resource.b.b, 0)) {
if (buffers & PIPE_CLEAR_DEPTH) {
/* Need to disable EXPCLEAR temporarily if clearing
* to a new value. */
if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
sctx->db_depth_disable_expclear = true;
}
zstex->depth_clear_value = depth;
sctx->framebuffer.dirty_zsbuf = true;
si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_DEPTH_CLEAR */
sctx->db_depth_clear = true;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
}
if (buffers & PIPE_CLEAR_STENCIL) {
stencil &= 0xff;
/* Need to disable EXPCLEAR temporarily if clearing
* to a new value. */
if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
sctx->db_stencil_disable_expclear = true;
}
zstex->stencil_clear_value = stencil;
sctx->framebuffer.dirty_zsbuf = true;
si_mark_atom_dirty(sctx, &sctx->framebuffer.atom); /* updates DB_STENCIL_CLEAR */
sctx->db_stencil_clear = true;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
}
}
si_blitter_begin(ctx, SI_CLEAR);
util_blitter_clear(sctx->blitter, fb->width, fb->height,
util_framebuffer_get_num_layers(fb),
buffers, color, depth, stencil);
si_blitter_end(ctx);
if (sctx->db_depth_clear) {
sctx->db_depth_clear = false;
sctx->db_depth_disable_expclear = false;
zstex->depth_cleared = true;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
}
if (sctx->db_stencil_clear) {
sctx->db_stencil_clear = false;
sctx->db_stencil_disable_expclear = false;
zstex->stencil_cleared = true;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
}
}
static void si_resource_copy_region(struct pipe_context *ctx,
struct pipe_resource *dst,
unsigned dst_level,
unsigned dstx, unsigned dsty, unsigned dstz,
struct pipe_resource *src,
unsigned src_level,
const struct pipe_box *src_box)
{
struct si_context *sctx = (struct si_context *)ctx;
struct r600_texture *rdst = (struct r600_texture*)dst;
struct pipe_surface *dst_view, dst_templ;
struct pipe_sampler_view src_templ, *src_view;
struct texture_orig_info orig_info[2];
struct pipe_box sbox, dstbox;
boolean restore_orig[2];
/* Fallback for buffers. */
if (dst->target == PIPE_BUFFER && src->target == PIPE_BUFFER) {
si_copy_buffer(sctx, dst, src, dstx, src_box->x, src_box->width);
return;
}
memset(orig_info, 0, sizeof(orig_info));
/* The driver doesn't decompress resources automatically while
* u_blitter is rendering. */
si_decompress_subresource(ctx, src, src_level,
src_box->z, src_box->z + src_box->depth - 1);
restore_orig[0] = restore_orig[1] = FALSE;
if (util_format_is_compressed(src->format) &&
util_format_is_compressed(dst->format)) {
si_compressed_to_blittable(src, src_level, &orig_info[0]);
restore_orig[0] = TRUE;
sbox.x = util_format_get_nblocksx(orig_info[0].format, src_box->x);
sbox.y = util_format_get_nblocksy(orig_info[0].format, src_box->y);
sbox.z = src_box->z;
sbox.width = util_format_get_nblocksx(orig_info[0].format, src_box->width);
sbox.height = util_format_get_nblocksy(orig_info[0].format, src_box->height);
sbox.depth = src_box->depth;
src_box = &sbox;
si_compressed_to_blittable(dst, dst_level, &orig_info[1]);
restore_orig[1] = TRUE;
/* translate the dst box as well */
dstx = util_format_get_nblocksx(orig_info[1].format, dstx);
dsty = util_format_get_nblocksy(orig_info[1].format, dsty);
} else if (!util_blitter_is_copy_supported(sctx->blitter, dst, src)) {
if (util_format_is_subsampled_422(src->format)) {
/* XXX untested */
si_change_format(src, src_level, &orig_info[0],
PIPE_FORMAT_R8G8B8A8_UINT);
si_change_format(dst, dst_level, &orig_info[1],
PIPE_FORMAT_R8G8B8A8_UINT);
sbox = *src_box;
sbox.x = util_format_get_nblocksx(orig_info[0].format, src_box->x);
sbox.width = util_format_get_nblocksx(orig_info[0].format, src_box->width);
src_box = &sbox;
dstx = util_format_get_nblocksx(orig_info[1].format, dstx);
restore_orig[0] = TRUE;
restore_orig[1] = TRUE;
} else {
unsigned blocksize = util_format_get_blocksize(src->format);
switch (blocksize) {
case 1:
si_change_format(src, src_level, &orig_info[0],
PIPE_FORMAT_R8_UNORM);
si_change_format(dst, dst_level, &orig_info[1],
PIPE_FORMAT_R8_UNORM);
break;
case 2:
si_change_format(src, src_level, &orig_info[0],
PIPE_FORMAT_R8G8_UNORM);
si_change_format(dst, dst_level, &orig_info[1],
PIPE_FORMAT_R8G8_UNORM);
break;
case 4:
si_change_format(src, src_level, &orig_info[0],
PIPE_FORMAT_R8G8B8A8_UNORM);
si_change_format(dst, dst_level, &orig_info[1],
PIPE_FORMAT_R8G8B8A8_UNORM);
break;
case 8:
si_change_format(src, src_level, &orig_info[0],
PIPE_FORMAT_R16G16B16A16_UINT);
si_change_format(dst, dst_level, &orig_info[1],
PIPE_FORMAT_R16G16B16A16_UINT);
break;
case 16:
si_change_format(src, src_level, &orig_info[0],
PIPE_FORMAT_R32G32B32A32_UINT);
si_change_format(dst, dst_level, &orig_info[1],
PIPE_FORMAT_R32G32B32A32_UINT);
break;
default:
fprintf(stderr, "Unhandled format %s with blocksize %u\n",
util_format_short_name(src->format), blocksize);
assert(0);
}
restore_orig[0] = TRUE;
restore_orig[1] = TRUE;
}
}
/* Initialize the surface. */
util_blitter_default_dst_texture(&dst_templ, dst, dst_level, dstz);
dst_view = r600_create_surface_custom(ctx, dst, &dst_templ,
rdst->surface.level[dst_level].npix_x,
rdst->surface.level[dst_level].npix_y);
/* Initialize the sampler view. */
util_blitter_default_src_texture(&src_templ, src, src_level);
src_view = ctx->create_sampler_view(ctx, src, &src_templ);
u_box_3d(dstx, dsty, dstz, abs(src_box->width), abs(src_box->height),
abs(src_box->depth), &dstbox);
/* Copy. */
si_blitter_begin(ctx, SI_COPY);
util_blitter_blit_generic(sctx->blitter, dst_view, &dstbox,
src_view, src_box, src->width0, src->height0,
PIPE_MASK_RGBAZS, PIPE_TEX_FILTER_NEAREST, NULL);
si_blitter_end(ctx);
pipe_surface_reference(&dst_view, NULL);
pipe_sampler_view_reference(&src_view, NULL);
if (restore_orig[0])
si_reset_blittable_to_orig(src, src_level, &orig_info[0]);
if (restore_orig[1])
si_reset_blittable_to_orig(dst, dst_level, &orig_info[1]);
}
static void si_blit_decompress_depth(struct pipe_context *ctx,
struct r600_texture *texture,
struct r600_texture *staging,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer,
unsigned first_sample, unsigned last_sample)
{
struct si_context *sctx = (struct si_context *)ctx;
unsigned layer, level, sample, checked_last_layer, max_layer;
float depth = 1.0f;
const struct util_format_description *desc;
assert(staging != NULL && "use si_blit_decompress_zs_in_place instead");
desc = util_format_description(staging->resource.b.b.format);
if (util_format_has_depth(desc))
sctx->dbcb_depth_copy_enabled = true;
if (util_format_has_stencil(desc))
sctx->dbcb_stencil_copy_enabled = true;
assert(sctx->dbcb_depth_copy_enabled || sctx->dbcb_stencil_copy_enabled);
for (level = first_level; level <= last_level; level++) {
/* The smaller the mipmap level, the less layers there are
* as far as 3D textures are concerned. */
max_layer = util_max_layer(&texture->resource.b.b, level);
checked_last_layer = MIN2(last_layer, max_layer);
for (layer = first_layer; layer <= checked_last_layer; layer++) {
for (sample = first_sample; sample <= last_sample; sample++) {
struct pipe_surface *zsurf, *cbsurf, surf_tmpl;
sctx->dbcb_copy_sample = sample;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
surf_tmpl.format = texture->resource.b.b.format;
surf_tmpl.u.tex.level = level;
surf_tmpl.u.tex.first_layer = layer;
surf_tmpl.u.tex.last_layer = layer;
zsurf = ctx->create_surface(ctx, &texture->resource.b.b, &surf_tmpl);
surf_tmpl.format = staging->resource.b.b.format;
cbsurf = ctx->create_surface(ctx,
(struct pipe_resource*)staging, &surf_tmpl);
si_blitter_begin(ctx, SI_DECOMPRESS);
util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
sctx->custom_dsa_flush, depth);
si_blitter_end(ctx);
pipe_surface_reference(&zsurf, NULL);
pipe_surface_reference(&cbsurf, NULL);
}
}
}
sctx->dbcb_depth_copy_enabled = false;
sctx->dbcb_stencil_copy_enabled = false;
si_mark_atom_dirty(sctx, &sctx->db_render_state);
}
static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
const struct pipe_blit_info *info)
{
struct si_context *sctx = (struct si_context*)ctx;
struct r600_texture *src = (struct r600_texture*)info->src.resource;
struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
enum pipe_format format = info->src.format;
unsigned sample_mask = ~0;
struct pipe_resource *tmp, templ;
struct pipe_blit_info blit;
/* Check basic requirements for hw resolve. */
if (!(info->src.resource->nr_samples > 1 &&
info->dst.resource->nr_samples <= 1 &&
!util_format_is_pure_integer(format) &&
!util_format_is_depth_or_stencil(format) &&
util_max_layer(info->src.resource, 0) == 0))
return false;
/* Hardware MSAA resolve doesn't work if SPI format = NORM16_ABGR and
* the format is R16G16. Use R16A16, which does work.
*/
if (format == PIPE_FORMAT_R16G16_UNORM)
format = PIPE_FORMAT_R16A16_UNORM;
if (format == PIPE_FORMAT_R16G16_SNORM)
format = PIPE_FORMAT_R16A16_SNORM;
/* Check the remaining requirements for hw resolve. */
if (util_max_layer(info->dst.resource, info->dst.level) == 0 &&
!info->scissor_enable &&
(info->mask & PIPE_MASK_RGBA) == PIPE_MASK_RGBA &&
util_is_format_compatible(util_format_description(info->src.format),
util_format_description(info->dst.format)) &&
dst_width == info->src.resource->width0 &&
dst_height == info->src.resource->height0 &&
info->dst.box.x == 0 &&
info->dst.box.y == 0 &&
info->dst.box.width == dst_width &&
info->dst.box.height == dst_height &&
info->dst.box.depth == 1 &&
info->src.box.x == 0 &&
info->src.box.y == 0 &&
info->src.box.width == dst_width &&
info->src.box.height == dst_height &&
info->src.box.depth == 1 &&
dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
(!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */
/* Check the last constraint. */
if (src->surface.micro_tile_mode != dst->surface.micro_tile_mode) {
/* The next fast clear will switch to this mode to
* get direct hw resolve next time if the mode is
* different now.
*/
src->last_msaa_resolve_target_micro_mode =
dst->surface.micro_tile_mode;
goto resolve_to_temp;
}
/* Resolving into a surface with DCC is unsupported. Since
* it's being overwritten anyway, clear it to uncompressed.
* This is still the fastest codepath even with this clear.
*/
if (dst->dcc_offset &&
dst->surface.level[info->dst.level].dcc_enabled) {
vi_dcc_clear_level(&sctx->b, dst, info->dst.level,
0xFFFFFFFF);
dst->dirty_level_mask &= ~(1 << info->dst.level);
}
/* Resolve directly from src to dst. */
si_blitter_begin(ctx, SI_COLOR_RESOLVE |
(info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
util_blitter_custom_resolve_color(sctx->blitter,
info->dst.resource, info->dst.level,
info->dst.box.z,
info->src.resource, info->src.box.z,
sample_mask, sctx->custom_blend_resolve,
format);
si_blitter_end(ctx);
return true;
}
resolve_to_temp:
/* Shader-based resolve is VERY SLOW. Instead, resolve into
* a temporary texture and blit.
*/
memset(&templ, 0, sizeof(templ));
templ.target = PIPE_TEXTURE_2D;
templ.format = info->src.resource->format;
templ.width0 = info->src.resource->width0;
templ.height0 = info->src.resource->height0;
templ.depth0 = 1;
templ.array_size = 1;
templ.usage = PIPE_USAGE_DEFAULT;
templ.flags = R600_RESOURCE_FLAG_FORCE_TILING |
R600_RESOURCE_FLAG_DISABLE_DCC;
/* The src and dst microtile modes must be the same. */
if (src->surface.micro_tile_mode == V_009910_ADDR_SURF_DISPLAY_MICRO_TILING)
templ.bind = PIPE_BIND_SCANOUT;
else
templ.bind = 0;
tmp = ctx->screen->resource_create(ctx->screen, &templ);
if (!tmp)
return false;
assert(src->surface.micro_tile_mode ==
((struct r600_texture*)tmp)->surface.micro_tile_mode);
/* resolve */
si_blitter_begin(ctx, SI_COLOR_RESOLVE |
(info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
util_blitter_custom_resolve_color(sctx->blitter, tmp, 0, 0,
info->src.resource, info->src.box.z,
sample_mask, sctx->custom_blend_resolve,
format);
si_blitter_end(ctx);
/* blit */
blit = *info;
blit.src.resource = tmp;
blit.src.box.z = 0;
si_blitter_begin(ctx, SI_BLIT |
(info->render_condition_enable ? 0 : SI_DISABLE_RENDER_COND));
util_blitter_blit(sctx->blitter, &blit);
si_blitter_end(ctx);
pipe_resource_reference(&tmp, NULL);
return true;
}
static void si_blit_decompress_depth(struct pipe_context *ctx,
struct r600_texture *texture,
struct r600_texture *staging,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer,
unsigned first_sample, unsigned last_sample)
{
struct si_context *sctx = (struct si_context *)ctx;
unsigned layer, level, sample, checked_last_layer, max_layer, max_sample;
float depth = 1.0f;
const struct util_format_description *desc;
void **custom_dsa;
struct r600_texture *flushed_depth_texture = staging ?
staging : texture->flushed_depth_texture;
if (!staging && !texture->dirty_level_mask)
return;
max_sample = u_max_sample(&texture->resource.b.b);
desc = util_format_description(flushed_depth_texture->resource.b.b.format);
switch (util_format_has_depth(desc) | util_format_has_stencil(desc) << 1) {
default:
assert(!"No depth or stencil to uncompress");
return;
case 3:
custom_dsa = sctx->custom_dsa_flush_depth_stencil;
break;
case 2:
custom_dsa = sctx->custom_dsa_flush_stencil;
break;
case 1:
custom_dsa = sctx->custom_dsa_flush_depth;
break;
}
for (level = first_level; level <= last_level; level++) {
if (!staging && !(texture->dirty_level_mask & (1 << level)))
continue;
/* The smaller the mipmap level, the less layers there are
* as far as 3D textures are concerned. */
max_layer = util_max_layer(&texture->resource.b.b, level);
checked_last_layer = last_layer < max_layer ? last_layer : max_layer;
for (layer = first_layer; layer <= checked_last_layer; layer++) {
for (sample = first_sample; sample <= last_sample; sample++) {
struct pipe_surface *zsurf, *cbsurf, surf_tmpl;
surf_tmpl.format = texture->resource.b.b.format;
surf_tmpl.u.tex.level = level;
surf_tmpl.u.tex.first_layer = layer;
surf_tmpl.u.tex.last_layer = layer;
zsurf = ctx->create_surface(ctx, &texture->resource.b.b, &surf_tmpl);
surf_tmpl.format = flushed_depth_texture->resource.b.b.format;
cbsurf = ctx->create_surface(ctx,
(struct pipe_resource*)flushed_depth_texture, &surf_tmpl);
si_blitter_begin(ctx, SI_DECOMPRESS);
util_blitter_custom_depth_stencil(sctx->blitter, zsurf, cbsurf, 1 << sample,
custom_dsa[sample], depth);
si_blitter_end(ctx);
pipe_surface_reference(&zsurf, NULL);
pipe_surface_reference(&cbsurf, NULL);
}
}
/* The texture will always be dirty if some layers aren't flushed.
* I don't think this case can occur though. */
if (!staging &&
first_layer == 0 && last_layer == max_layer &&
first_sample == 0 && last_sample == max_sample) {
texture->dirty_level_mask &= ~(1 << level);
}
}
}
static void si_clear(struct pipe_context *ctx, unsigned buffers,
const union pipe_color_union *color,
double depth, unsigned stencil)
{
struct si_context *sctx = (struct si_context *)ctx;
struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
struct pipe_surface *zsbuf = fb->zsbuf;
struct si_texture *zstex =
zsbuf ? (struct si_texture*)zsbuf->texture : NULL;
if (buffers & PIPE_CLEAR_COLOR) {
si_do_fast_color_clear(sctx, &buffers, color);
if (!buffers)
return; /* all buffers have been fast cleared */
/* These buffers cannot use fast clear, make sure to disable expansion. */
for (unsigned i = 0; i < fb->nr_cbufs; i++) {
struct si_texture *tex;
/* If not clearing this buffer, skip. */
if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
continue;
tex = (struct si_texture *)fb->cbufs[i]->texture;
if (tex->surface.fmask_size == 0)
tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
}
}
if (zstex &&
si_htile_enabled(zstex, zsbuf->u.tex.level) &&
zsbuf->u.tex.first_layer == 0 &&
zsbuf->u.tex.last_layer == util_max_layer(&zstex->buffer.b.b, 0)) {
/* TC-compatible HTILE only supports depth clears to 0 or 1. */
if (buffers & PIPE_CLEAR_DEPTH &&
(!zstex->tc_compatible_htile ||
depth == 0 || depth == 1)) {
/* Need to disable EXPCLEAR temporarily if clearing
* to a new value. */
if (!zstex->depth_cleared || zstex->depth_clear_value != depth) {
sctx->db_depth_disable_expclear = true;
}
if (zstex->depth_clear_value != (float)depth) {
/* Update DB_DEPTH_CLEAR. */
zstex->depth_clear_value = depth;
sctx->framebuffer.dirty_zsbuf = true;
si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
}
sctx->db_depth_clear = true;
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
}
/* TC-compatible HTILE only supports stencil clears to 0. */
if (buffers & PIPE_CLEAR_STENCIL &&
(!zstex->tc_compatible_htile || stencil == 0)) {
stencil &= 0xff;
/* Need to disable EXPCLEAR temporarily if clearing
* to a new value. */
if (!zstex->stencil_cleared || zstex->stencil_clear_value != stencil) {
sctx->db_stencil_disable_expclear = true;
}
if (zstex->stencil_clear_value != (uint8_t)stencil) {
/* Update DB_STENCIL_CLEAR. */
zstex->stencil_clear_value = stencil;
sctx->framebuffer.dirty_zsbuf = true;
si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
}
sctx->db_stencil_clear = true;
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
}
/* TODO: Find out what's wrong here. Fast depth clear leads to
* corruption in ARK: Survival Evolved, but that may just be
* a coincidence and the root cause is elsewhere.
*
* The corruption can be fixed by putting the DB flush before
* or after the depth clear. (surprisingly)
*
* https://bugs.freedesktop.org/show_bug.cgi?id=102955 (apitrace)
*
* This hack decreases back-to-back ClearDepth performance.
*/
if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
sctx->screen->options.clear_db_cache_before_clear)
sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
}
si_blitter_begin(sctx, SI_CLEAR);
util_blitter_clear(sctx->blitter, fb->width, fb->height,
util_framebuffer_get_num_layers(fb),
buffers, color, depth, stencil);
si_blitter_end(sctx);
if (sctx->db_depth_clear) {
sctx->db_depth_clear = false;
sctx->db_depth_disable_expclear = false;
zstex->depth_cleared = true;
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
}
if (sctx->db_stencil_clear) {
sctx->db_stencil_clear = false;
sctx->db_stencil_disable_expclear = false;
zstex->stencil_cleared = true;
si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
}
}