void s_init(void)
{
	/*
	 * The ROM will only have set up sufficient pinmux to allow for the
	 * first 4KiB NOR to be read, we must finish doing what we know of
	 * the NOR mux in this space in order to continue.
	 */
#ifdef CONFIG_NOR_BOOT
	enable_norboot_pin_mux();
#endif
	watchdog_disable();
	set_uart_mux_conf();
	setup_clocks_for_console();
	uart_soft_reset();
#if defined(CONFIG_NOR_BOOT) || defined(CONFIG_QSPI_BOOT)
	/* TODO: This does not work, gd is not available yet */
	gd->baudrate = CONFIG_BAUDRATE;
	serial_init();
	gd->have_console = 1;
#endif
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
	/* Enable RTC32K clock */
	rtc32k_enable();
#endif
}
int main(void) {
  int32_t i;
  uint8_t pos=0;
  uint8_t dir=1;
  watchdog_disable();
  minimus32_init();
  clock_prescale_none();

  sw_dither_init(&dither, 50); //Full brightness was too bright 50% is better
  sw_rc_servo_init(&servo, 25);
  timer0_fast_timer_init(TIMER0_8, 80); //setup 25 ints per ms

  sei(); //ints on

  while (1){
    sw_dither_set(&dither, pos);
    sw_rc_servo_set_pos(&servo, pos);
    pos+=dir;
    if (pos==25) dir=255;
    if (pos==0) dir = 1;
    
    for (i=0; i<6000; i++){
    }
  }

}
Beispiel #3
0
Datei: main.c Projekt: Mpic/avr
int main(void)
{
    int blink = 0;

    setup();

    for (;;) {
	/* enable transistor */
	PORTB |= _BV(PB4);
	_delay_us(500);
	blink = ACSR & _BV(ACO); 
	PORTB &= ~(_BV(PB4));
	/* disable transistor */

	if (blink) {
	    PORTB |= _BV(PB2);
	    _delay_ms(DELAY);
	    PORTB &= ~(_BV(PB2));
	    watchdog_enable(WD_2_SECONDS);
	} else {
	    watchdog_enable(WD_8_SECONDS);
	}

	powerdown();
	watchdog_disable();
    }

    return 0;
}
static int watchdog_close(struct inode *inode,struct file *file)
{
	watchdog_disable();
	printk("watchdog: disable watchdog\n");

	return 0;
}
Beispiel #5
0
void machine_restart(unsigned int delay_millisecs)
{
    int timeout = 10;

    watchdog_disable();
    console_start_sync();
    spin_debug_disable();

    local_irq_enable();
    smp_call_function(halt_this_cpu, NULL, 0);
    local_irq_disable();

    mdelay(delay_millisecs);

    /* Wait at most another 10ms for all other CPUs to go offline. */
    while ( (num_online_cpus() > 1) && (timeout-- > 0) )
        mdelay(1);

    /* This is mainly for PSCI-0.2, which does not return if success. */
    call_psci_system_reset();

    /* Alternative reset procedure */
    while ( 1 )
    {
        platform_reset();
        mdelay(100);
    }
}
Beispiel #6
0
void early_system_init(void)
{
	/*
	 * The ROM will only have set up sufficient pinmux to allow for the
	 * first 4KiB NOR to be read, we must finish doing what we know of
	 * the NOR mux in this space in order to continue.
	 */
#ifdef CONFIG_NOR_BOOT
	enable_norboot_pin_mux();
#endif
	watchdog_disable();
	set_uart_mux_conf();
	setup_early_clocks();
	uart_soft_reset();
#ifdef CONFIG_SPL_BUILD
	/*
	 * Save the boot parameters passed from romcode.
	 * We cannot delay the saving further than this,
	 * to prevent overwrites.
	 */
	save_omap_boot_params();
#endif
#ifdef CONFIG_DEBUG_UART_OMAP
	debug_uart_init();
#endif
#ifdef CONFIG_TI_I2C_BOARD_DETECT
	do_board_detect();
#endif
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
	/* Enable RTC32K clock */
	rtc32k_enable();
#endif
}
Beispiel #7
0
static void kexec_common_shutdown(void)
{
    watchdog_disable();
    console_start_sync();
    spin_debug_disable();
    one_cpu_only();
    acpi_table_parse(ACPI_SIG_DMAR, acpi_dmar_reinstate);
}
Beispiel #8
0
void machine_halt(void)
{
    watchdog_disable();
    console_start_sync();
    local_irq_enable();
    smp_call_function(__machine_halt, NULL, 0);
    __machine_halt(NULL);
}
Beispiel #9
0
static int watchdog_release(struct inode *inode, struct file *filp)
{
	watchdog_disable();

	open_state = WATCHDOG_DRIVER_CLOSE;
	wd_expire = 0;
	printk(KERN_INFO PFX "watchog timer disabled, margin: %ds.\n", wdt_margin);

	return 0;
}
Beispiel #10
0
/*
 * Writing the config is done to the next unwritten slot in the
 * flash.  If all slots have been written, erase whole block and
 * start from the first slot.
 * We calculate the config CRC just before writing.
 */
void write_config(void)
{
#if 0
	config.crc = calc_block_crc(sizeof(config) - sizeof(unsigned),
								(void *)&config);
	/* This might take a long time, so take the risk. */
	watchdog_disable();
	eeprom_write_block(&config, (void *)EE_CONFIG_ADDRESS, sizeof(config));
	watchdog_enable();
#endif
}
Beispiel #11
0
static retval_t cmd_watchdog_disable(const subsystem_t *self, frame_t *iframe, frame_t *oframe) {
	uint32_t key;

	if (RV_SUCCESS != frame_get_u32(iframe, &key)) return RV_ILLEGAL;
    FUTURE_HOOK_3(pm_cmd_watchdog_disable, &key, iframe, oframe);

    if (0xCACACECA != key) return RV_ILLEGAL;

    watchdog_disable();
    return RV_SUCCESS;
}
Beispiel #12
0
void
Default_Reset_Handler(void)
{
        /* XXX this is permanent - move to application code? */
        watchdog_disable();

#ifdef EXTERNAL_XTAL
        OSC_CR = OSC_CR_SC16P_MASK;
        MCG.c2.raw = ((struct MCG_C2_t){
                        .range0 = MCG_RANGE_VERYHIGH,
                                .erefs0 = MCG_EREF_OSC
                                }).raw;
Beispiel #13
0
void setup(void)
{
   unsigned char i;

   watchdog_disable();
   
   XBR0 = 0x01;                 // Enable RX/TX
   XBR1 = 0x40;                 // Enable crossbar
   P0MDOUT = 0x90;              // P0.4: TX, P0.7: RS485 enable Push/Pull
   P0SKIP  = 0x0C;              // Skip P0.2&3 for Xtal
   P0MDIN  = 0xF3;              // P0.2&3 as analog input for Xtal
   P2MDOUT = 0x02;              // P2.1 for external watchdog

   OSCXCN = 0;
   OSCICN |= 0x03;              // Configure internal oscillator for
                                // its maximum frequency

   CLKMUL = 0x00;               // Select internal oscillator as
                                // input to clock multiplier

   CLKMUL |= 0x80;              // Enable clock multiplier
   for (i=0 ; i<100 ; i++);     // Delay for >5us
   CLKMUL |= 0xC0;              // Initialize the clock multiplier

   while(!(CLKMUL & 0x20));     // Wait for multiplier to lock

   CLKSEL |= USB_4X_CLOCK;      // Select USB clock
   CLKSEL |= SYS_INT_OSC;       // Select system clock

   VDM0CN = 0x80;               // VDD monitor enable
   while ((VDM0CN & 0x40)==0);  // wait for VDD monitor to stabilize

   /* start system clock */
   sysclock_init();

   /* init memory */
   RS485_ENABLE = 0;

   /* initialize UART0 */
   uart_init(0, BD_115200);
   PS0 = 1;                     // serial interrupt high priority

   /* Blink LEDs */
   led_blink(0, 3, 150);
   led_blink(1, 3, 150);

   /* invert first LED */
   led_mode(0, 1);

   /* dummy to prevent linker error */
   delay_us(1);
}
Beispiel #14
0
static void maybe_reboot(void)
{
    if ( opt_noreboot )
    {
        printk("'noreboot' set - not rebooting.\n");
        machine_halt();
    }
    else
    {
        printk("rebooting machine in 5 seconds.\n");
        watchdog_disable();
        machine_restart(5000);
    }
}
Beispiel #15
0
int main(void) {
  watchdog_disable();
  clock_prescale_none();
  timer1_clock_init();

  lcd_44780_power_up_delay();
  lcd_44780_init();

  lcd_44780_print("Hello world");

  while (1) {
    print_time();  
  }
  return 0;
}
Beispiel #16
0
static int watchdog_open(struct inode *inode, struct file *filp)
{
	if (open_state == WATCHDOG_DRIVER_OPEN)
		return -EBUSY;

	wd_expire = 0;

	watchdog_disable();
	watchdog_set_timeout(wdt_margin);
	watchdog_enable();

	printk(KERN_INFO PFX "watchog timer enabled, margin: %ds.\n", wdt_margin);
	open_state = WATCHDOG_DRIVER_OPEN;

	return nonseekable_open(inode, filp);
}
Beispiel #17
0
void s_init(void)
{
	/*
	 * The ROM will only have set up sufficient pinmux to allow for the
	 * first 4KiB NOR to be read, we must finish doing what we know of
	 * the NOR mux in this space in order to continue.
	 */
#ifdef CONFIG_NOR_BOOT
	enable_norboot_pin_mux();
#endif
	watchdog_disable();
	set_uart_mux_conf();
	setup_clocks_for_console();
	uart_soft_reset();
#if defined(CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC)
	/* Enable RTC32K clock */
	rtc32k_enable();
#endif
}
Beispiel #18
0
void machine_halt(void)
{
    int timeout = 10;

    watchdog_disable();
    console_start_sync();
    local_irq_enable();
    smp_call_function(halt_this_cpu, NULL, 0);
    local_irq_disable();

    /* Wait at most another 10ms for all other CPUs to go offline. */
    while ( (num_online_cpus() > 1) && (timeout-- > 0) )
        mdelay(1);

    /* This is mainly for PSCI-0.2, which does not return if success. */
    call_psci_system_off();

    /* Alternative halt procedure */
    platform_poweroff();
    halt_this_cpu(NULL);
}
Beispiel #19
0
void s_init(void)
{
	/*
	 * The ROM will only have set up sufficient pinmux to allow for the
	 * first 4KiB NOR to be read, we must finish doing what we know of
	 * the NOR mux in this space in order to continue.
	 */
#ifdef CONFIG_NOR_BOOT
	enable_norboot_pin_mux();
#endif
	/*
	 * Save the boot parameters passed from romcode.
	 * We cannot delay the saving further than this,
	 * to prevent overwrites.
	 */
#ifdef CONFIG_SPL_BUILD
	save_omap_boot_params();
#endif
	watchdog_disable();
	timer_init();
	set_uart_mux_conf();
	setup_clocks_for_console();
	uart_soft_reset();

#ifdef CONFIG_NOR_BOOT
	gd->baudrate = CONFIG_BAUDRATE;
	serial_init();
	gd->have_console = 1;
#elif defined(CONFIG_SPL_BUILD)
	gd = &gdata;
	preloader_console_init();
#endif

	prcm_init();
	set_mux_conf_regs();
	/* Enable RTC32K clock */
	rtc32k_enable();
	sdram_init();
}
Beispiel #20
0
void domain_shutdown(struct domain *d, u8 reason)
{
    struct vcpu *v;

    if ( d->domain_id == 0 )
    {
        extern void machine_restart(char *);
        extern void machine_halt(void);

        debugger_trap_immediate();

        if ( reason == SHUTDOWN_poweroff ) 
        {
            printk("Domain 0 halted: halting machine.\n");
            machine_halt();
        }
        else if ( reason == SHUTDOWN_crash )
        {
            printk("Domain 0 crashed: rebooting machine in 5 seconds.\n");
            watchdog_disable();
            //mdelay(5000);
            machine_restart(0);
        }
        else
        {
            printk("Domain 0 shutdown: rebooting machine.\n");
            machine_restart(0);
        }
    }

    /* Mark the domain as shutting down. */
    d->shutdown_code = reason;

    /* Put every vcpu to sleep, but don't wait (avoids inter-vcpu deadlock). */
    for_each_vcpu ( d, v )
    {
        atomic_inc(&v->pausecnt);
        vcpu_sleep_nosync(v);
    }
Beispiel #21
0
int main(void) { 
  uint16_t i,j;
  uint8_t s;

  timer1_callback blink_call_back;
  timer1_callback backlight_call_back;

  watchdog_disable();
  minimus32_init();
  clock_prescale_none();
  spi_config_io_for_master_mode();
  DDRB |= 0b11110000; //IO setup for the reset,cs, cmd and led pin

  pcd8544_init(&pcdIO, 45);

  //Setup a blink pattern indicating a working MCU
  timer1_clock_init();
  timer1_clock_register_callback(0, 100, 1, &blink, 0, &blink_call_back);

  //Enable the pulsed output that controls the backlight
  sw_dither_init(&backlight, 1023);
  timer1_clock_register_callback(0, 1, 1, &handleBackLight, 0, &backlight_call_back);

  for (i=0; i<1024; i++){
    for(j=0; j<2000; j++){}
    sw_dither_set(&backlight, i);
  } 

  //Show grey scale hack
  while (1) {
    while (state_==GREY_HACK_STATE){
      greyScaleHack(s);
      s++;
      if (s>2) s=0;
      for(j=0; j<7500; j++){}
    }
  }
  return 0;
}
/*
 *	Process a watchdog timeout interrupt. For a normal clean watchdog
 *	we just do a process dump. For old broken 5307 we need to verify
 *	if this was a real watchdog event or not...
 */
void watchdog_timeout(int irq, void *dummy, struct pt_regs *fp)
{
#ifdef CONFIG_OLDMASK
	/*
	 *	Debuging code for software watchdog. If we get in here
	 *	and timer interrupt counts don't match we know that a
	 *	bad external bus cycle must have locked the CPU.
	 */
	if ((swt_doit++ > TIMEDELAY) &&
	    ((swt_lastjiffies + swt_reference) > jiffies)) {
		if (swt_inwatchdog) {
			cli();
			watchdog_disable();
			mcf_setimr(mcf_getimr() | MCFSIM_IMR_SWD);
			printk("%s(%d): Double WATCHDOG PANIC!!\n",
				__FILE__, __LINE__);
			for (;;)
				;
		}

		swt_inwatchdog++;
		swt_doit = TIMEDELAY - 8;	/* 8 seconds grace */
		printk("WATCHDOG: expired last=%d(%d) jiffies=%d!\n",
			swt_lastjiffies, swt_reference, jiffies);
		dump(fp);
		force_sig(SIGSEGV, current);
		swt_inwatchdog  = 0;
	}
	swt_lastjiffies = jiffies;
#else

	printk("WATCHDOG: expired!\n");
	dump(fp);

#endif /* CONFIG_OLDMASK */
}
void main(void) {
#else
int main(void) {
#endif
    
    uint32_t blcc;
    
    // Prevent optimizing of bootloader revision in progmem
    volatile uint16_t tmp2 = ATmega3290p_bl_rev;
    
    // Disable watchdog
    watchdog_disable();
    
    
    // Configuring LCD with Extern clock (TOSC, 32.768kHz)
    //                      32786 Hz          32786 Hz
    //  frame_rate = ------------------ = ------------- = 32 Hz
    //               8 * .prescl * .div     8 * 16 * 8
    //
    lcd_config_t lcd_config = LCD_DEFAULT_CONFIG;
    
    // Initialization
    if (true != avr_init()) {               // Generic MCU initialization
        error_handler();
    } else if (df_init() != 0) {            // Data flash initialization
        error_handler();
    } else if (lcd_init(lcd_config) != 0) { // Display
        error_handler();
    } else if (led_init() != 0) {           // Led
        error_handler();
    }
    
   
    /* start timer 2*/
    ASSR |= (1<<AS2);    // Asynchronous operation
    TCCR2A &= ~((1<<CS22)|(1<<CS21)|(1<<CS20));
    TCCR2A |= (1<<CS20);
    
    
    // Check shorting of "Factory default pins"
    uint8_t prr = PRR;
	PRR &= ~(1 << PRADC);
	DIDR1 &= ~((1 << AIN1D)|(1 << AIN0D));
	PRR = prr;
    
    BOOT_DDR |= (1 << BOOT_TX);  // Tx output
    BOOT_PORT &= ~(1 << BOOT_TX);  // Tx low
    
    BOOT_DDR &= ~(1 << BOOT_RX); // Rx input
    BOOT_PORT |= (1 << BOOT_RX); // Rx pullup on
    
    if ((BOOT_PIN & (1 << BOOT_RX)) != (1 << BOOT_RX)) { // Rx pin low?
        /* Check that RX goes high when TX is pulled high. */
        BOOT_PORT |= (1 << BOOT_TX);                            // Set Tx high
        
        nop();
        nop();
        nop();
        nop();
        
        if ((BOOT_PIN & (1 << BOOT_RX)) == (1 << BOOT_RX)) {    // Rx high?
            intvecs_to_boot(); // move interrutp vectors to boot section, and start boot loader
            sei();
            
            // Check supply voltage
            if (supply_voltage_read() < 2600) {
                lcd_puts("LOW BAT");
                error_handler();
            }
            
            BLCC_WRITE(BLCC_NORMAL_APP_START); // write communication channel in case abnormal exit of boot loader (power off etc.)
            
            lcd_symbol_set(LCD_SYMBOL_RAVEN);
            lcd_puts("WRITING");
            led_status_set(LED_FAST_BLINK);
            do_fw_upgrade(M3290P_FLASH_FD_IMG_ADR);

            // Signal ATmega3290p application program that FW upgrade is complete
            // This makes the application program continue upgrade ATmega1284p after booting
            BLCC_WRITE(BLCC_LOAD_FACTORY_DEFAULT);
            
            app_start();    // start application program
        }
    }
    
    // Read bootloader communication channel in EEPROM and take proper action
    BLCC_READ(blcc);
    if (blcc == BLCC_FW_UPGRADE_START_REQUEST_FROM_APP) {
        intvecs_to_boot(); // move interrutp vectors to boot section, and start boot loader
        sei();
        
        // Check supply voltage
        if (supply_voltage_read() < 2600) {
            lcd_puts("LOW BAT");
            error_handler();
        }
        
        BLCC_WRITE(BLCC_NORMAL_APP_START); // write communication channel in case abnormal exit of boot loader (power off etc.)
        
        lcd_symbol_set(LCD_SYMBOL_RAVEN);
        lcd_puts("WRITING");
        led_status_set(LED_FAST_BLINK);
        do_fw_upgrade(M3290P_FLASH_USR_IMG_ADR);
        
        // Signal ATmega3290p application program that FW upgrade is complete
        BLCC_WRITE(BLCC_FW_UPGRADE_COMPLETE);
        reboot();
    } else if (blcc == BLCC_FW_UPGRADE_COMPLETE) {
        BLCC_WRITE(BLCC_FW_UPGRADE_COMPLETE);
        sei();
        app_start();    // start application program
    } else if (blcc == BLCC_RESTART_REQUEST_FROM_APP) {
        /* Start application program*/
        BLCC_WRITE(BLCC_NORMAL_APP_START);
        sei();
        app_start();
    } else {
        /*else, start application program*/
        BLCC_WRITE(BLCC_NORMAL_APP_START);
        sei();
        app_start();
    }
}
Beispiel #24
0
static void sl351x_wdt_shutdown(struct platform_device *dev)
{
	watchdog_disable();
}
Beispiel #25
0
void setup(void)
{
   unsigned char adr, flags, d;
   unsigned short i;
   unsigned char *p;

   _flkey = 0;
   
   /* first disable watchdog */
   watchdog_disable();

   /* avoid any blocking of RS485 bus */
   RS485_ENABLE = RS485_ENABLE_OFF;

   /* Port and oscillator configuration */

#if defined(CPU_C8051F120)

   SFRPAGE   = CONFIG_PAGE;
  
   XBR0 = 0x04;                 // Enable XBar, UART0 & UART1
   XBR1 = 0x00;
   XBR2 = 0x44;

  #ifdef CLK_25MHZ
   /* Select internal quartz oscillator */
   SFRPAGE   = LEGACY_PAGE;
   FLSCL     = 0x00;            // set flash read time for <25 MHz

   SFRPAGE   = CONFIG_PAGE;
   OSCICN    = 0x83;            // divide by 1
   CLKSEL    = 0x00;            // select internal oscillator
  #else          // 98 MHz
   /* Select internal quartz oscillator */
   SFRPAGE   = LEGACY_PAGE;
   FLSCL     = 0xB0;            // set flash read time for 100 MHz

   SFRPAGE   = CONFIG_PAGE;
   OSCICN    = 0x83;            // divide by 1
   CLKSEL    = 0x00;            // select internal oscillator

   PLL0CN    |= 0x01;
   PLL0DIV   = 0x01;
   PLL0FLT   = 0x01;
   PLL0MUL   = 0x04;
   for (i = 0 ; i < 15; i++);   // Wait 5us for initialization
   PLL0CN    |= 0x02;
   for (i = 0 ; i<50000 && ((PLL0CN & 0x10) == 0) ; i++);

   CLKSEL    = 0x02;            // select PLL as sysclk src
  #endif

#elif defined(CPU_C8051F020)

   XBR0 = 0x04;                 // Enable UART0 & UART1
   XBR1 = 0x00;
   XBR2 = 0x44;

   /* Select external quartz oscillator */
   OSCXCN = 0x67;               // Crystal mode, Power Factor 22E6
   OSCICN = 0x08;               // CLKSL=1 (external)

#elif defined(CPU_C8051F310) || defined(CPU_C8051F320)

   XBR0 = 0x01;                 // Enable RX/TX
   XBR1 = 0x40;                 // Enable crossbar

   /* Select internal quartz oscillator */
   OSCICN = 0x83;               // IOSCEN=1, SYSCLK=24.5 MHz
   CLKSEL = 0x00;               // derive SYSCLK from internal source

#else

   XBR0 = 0x04;                 // Enable RX/TX
   XBR1 = 0x00;
   XBR2 = 0x40;                 // Enable crossbar

   PRT0CF = 0x01;               // P0.0: TX = Push Pull
   PRT1CF = 0x00;               // P1
   PRT2CF = 0x00;               // P2  Open drain for 5V LCD
   PRT3CF = 0x20;               // P3.5: RS485 enable = Push Pull

   /* Select external quartz oscillator */
   OSCXCN = 0x67;               // Crystal mode, Power Factor 22E6
   OSCICN = 0x08;               // CLKSL=1 (external)

#endif
        
#ifdef CFG_HAVE_LCD
   lcd_setup();
#endif

#ifdef CFG_HAVE_EMIF
   /* initialize external memory interface */
   d = emif_init();

   /* do memory test on cold start */
   SFRPAGE = LEGACY_PAGE;
   if (d > 0 && (RSTSRC & 0x02) > 0)
      emif_test(d);
#endif

   /* start system clock */
   sysclock_init();

   /* enable watchdog with default timeout */
   watchdog_enable(0);

   /* enable missing clock detector */
   RSTSRC |= 0x04;

   /* default LED mode */
   for (i=0 ; i<N_LED ; i++)
      led_mode(i, 1);
   
   /* initialize all memory */
   CSR = 0;
   addressed = 0;
   flash_param = 0;
   flash_program = 0;
   flash_allowed = 0;
   wrong_cpu = 0;
   _flkey = 0;

#ifdef CFG_HAVE_RTC
   rtc_set = 0;
#endif

   i_in = i_out = n_out = 0;
   _cur_sub_addr = 0;
   for (i=0 ; i<sizeof(in_buf) ; i++)
      in_buf[i] = 0;
   for (i=0 ; i<sizeof(out_buf) ; i++)
      out_buf[i] = 0;

   /* check if we got reset by watchdog */
#if defined(CPU_C8051F120)
   SFRPAGE   = LEGACY_PAGE;
#endif
   WD_RESET = ((RSTSRC & 0x02) == 0 && (RSTSRC & 0x08) > 0);

   /* initialize UART(s) */
   uart_init(0, BD_115200);

#ifdef CFG_UART1_MSCB
   uart_init(1, BD_115200);
#endif

#ifdef CFG_DYN_VARIABLES
   setup_variables();
#endif

   /* count variables */
   for (n_variables = _var_size = 0;; n_variables++) {
      _var_size += variables[n_variables].width;
      if (variables[n_variables].width == 0)
         break;
   }

   /* check if variables are in xdata and xdata is present */
   if (n_variables > 0) {
      p = variables[0].ud;
      d = *p;
      *p = 0x55;
      if (*p != 0x55)
         wrong_cpu = 1;
      *p = 0xAA;
      if (*p != 0xAA)
         wrong_cpu = 1;
      *p = d;
   }

   /* retrieve EEPROM data */
#ifdef CPU_C8051F120
   SFRPAGE = LEGACY_PAGE;
#endif
   if ((RSTSRC & 0x02) > 0)
      flags = eeprom_retrieve(1); // vars on cold start
   else
      flags = eeprom_retrieve(0);

   if ((flags & (1 << 0)) == 0) {
      configured_addr = 0;
   
      /* set initial values */
      sys_info.node_addr = 0xFFFF;
      sys_info.group_addr = 0xFFFF;
      memset(sys_info.node_name, 0, sizeof(sys_info.node_name));
      strncpy(sys_info.node_name, node_name, sizeof(sys_info.node_name));
   } else
      configured_addr = 1;

   /* store SVN revision */
   sys_info.svn_revision = (svn_rev_main[6]-'0')*1000+
                           (svn_rev_main[7]-'0')*100+
                           (svn_rev_main[8]-'0')*10+
                           (svn_rev_main[9]-'0');

   if ((flags & (1 << 1)) == 0) {

      /* init variables */
      for (i = 0; variables[i].width; i++)
         if (!(variables[i].flags & MSCBF_DATALESS)) {
            /* do it for each sub-address */
            for (adr = 0 ; adr < _n_sub_addr ; adr++) {
               memset((char*)variables[i].ud + _var_size*adr, 0, variables[i].width);
            }
         }

      /* call user initialization routine with initialization */
      user_init(1);

      /* write current variables to flash later in main routine */
      configured_vars = 0;
   } else {
      /* call user initialization routine without initialization */
      user_init(0);
      configured_vars = 1;
   }

   /* Blink LEDs */
   for (i=0 ; i<N_LED ; i++)
      led_blink(i, 3, 150);

}
Beispiel #26
0
/* trap handler: main entry point */
int 
__trap_to_gdb(struct cpu_user_regs *regs, unsigned long cookie)
{
    int rc = 0;
    unsigned long flags;

    if ( gdb_ctx->serhnd < 0 )
    {
        printk("Debugging connection not set up.\n");
        return -EBUSY;
    }

    /* We rely on our caller to ensure we're only on one processor
     * at a time... We should probably panic here, but given that
     * we're a debugger we should probably be a little tolerant of
     * things going wrong. */
    /* We don't want to use a spin lock here, because we're doing
       two distinct things:

       1 -- we don't want to run on more than one processor at a time,
            and
       2 -- we want to do something sensible if we re-enter ourselves.

       Spin locks are good for 1, but useless for 2. */
    if ( !atomic_dec_and_test(&gdb_ctx->running) )
    {
        printk("WARNING WARNING WARNING: Avoiding recursive gdb.\n");
        atomic_inc(&gdb_ctx->running);
        return -EBUSY;
    }

    if ( !gdb_ctx->connected )
    {
        printk("GDB connection activated.\n");
        gdb_arch_print_state(regs);
        gdb_ctx->connected = 1;
    }

    gdb_smp_pause();

    local_irq_save(flags);

    watchdog_disable();
    console_start_sync();

    /* Shouldn't really do this, but otherwise we stop for no
       obvious reason, which is Bad */
    printk("Waiting for GDB to attach...\n");

    gdb_arch_enter(regs);
    gdb_ctx->signum = gdb_arch_signal_num(regs, cookie);

    /* If gdb is already attached, tell it we've stopped again. */
    if ( gdb_ctx->currently_attached )
    {
        gdb_start_packet(gdb_ctx);
        gdb_cmd_signum(gdb_ctx);
    }

    do {
        if ( receive_command(gdb_ctx) < 0 )
        {
            dbg_printk("Error in GDB session...\n");
            rc = -EIO;
            break;
        }
    } while ( process_command(regs, gdb_ctx) == 0 );

    gdb_smp_resume();

    gdb_arch_exit(regs);
    console_end_sync();
    watchdog_enable();
    atomic_inc(&gdb_ctx->running);

    local_irq_restore(flags);

    return rc;
}
Beispiel #27
0
static int sl351x_wdt_suspend(struct platform_device *dev, pm_message_t state)
{
	watchdog_disable();
}
Beispiel #28
0
static void watchdog_cleanup(unsigned int cpu, bool online)
{
	watchdog_disable(cpu);
}
Beispiel #29
0
/* do some early init */
void s_init(void)
{
	watchdog_disable();
}
Beispiel #30
0
// Hook to customize watchdog init. Defaults to disable, implement to override.
static void watchdog_hook_default(void) { watchdog_disable(); } // Why do you have to go and make things so complicated?