static void reversed_bs_w_2(void *t, bus_space_handle_t h, bus_size_t o, uint16_t v) { writew(h + (o &~ 3) + (2 - (o & 3)), v); }
static void c_can_plat_write_reg_aligned_to_32bit(const struct c_can_priv *priv, enum reg index, u16 val) { writew(val, priv->base + 2 * priv->regs[index]); }
static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg, int last) { struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap); u16 val, tcr_val; int ret, wait_result; int xfer_len = 0; if (!(pmsg->flags & I2C_M_NOSTART)) { ret = wmt_i2c_wait_bus_not_busy(i2c_dev); if (ret < 0) return ret; } if (pmsg->len == 0) { /* * We still need to run through the while (..) once, so * start at -1 and break out early from the loop */ xfer_len = -1; writew(0, i2c_dev->base + REG_CDR); } else { writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR); } if (!(pmsg->flags & I2C_M_NOSTART)) { val = readw(i2c_dev->base + REG_CR); val &= ~CR_TX_END; writew(val, i2c_dev->base + REG_CR); val = readw(i2c_dev->base + REG_CR); val |= CR_CPU_RDY; writew(val, i2c_dev->base + REG_CR); } reinit_completion(&i2c_dev->complete); if (i2c_dev->mode == I2C_MODE_STANDARD) tcr_val = TCR_STANDARD_MODE; else tcr_val = TCR_FAST_MODE; tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK)); writew(tcr_val, i2c_dev->base + REG_TCR); if (pmsg->flags & I2C_M_NOSTART) { val = readw(i2c_dev->base + REG_CR); val |= CR_CPU_RDY; writew(val, i2c_dev->base + REG_CR); } while (xfer_len < pmsg->len) { wait_result = wait_for_completion_timeout(&i2c_dev->complete, 500 * HZ / 1000); if (wait_result == 0) return -ETIMEDOUT; ret = wmt_check_status(i2c_dev); if (ret) return ret; xfer_len++; val = readw(i2c_dev->base + REG_CSR); if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) { dev_dbg(i2c_dev->dev, "write RCV NACK error\n"); return -EIO; } if (pmsg->len == 0) { val = CR_TX_END | CR_CPU_RDY | CR_ENABLE; writew(val, i2c_dev->base + REG_CR); break; } if (xfer_len == pmsg->len) { if (last != 1) writew(CR_ENABLE, i2c_dev->base + REG_CR); } else { writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base + REG_CDR); writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR); } } return 0; }
DLLEXPORT void hal_writew(u16 val, volatile void *addr) { writew(val, addr); }
static void ide_itdm320_outw (u16 val, unsigned long port) { writew(val, port); }
/* ======================================================================== Routine Description: Write 16-bit to a register. Arguments: pAd - WLAN control block pointer Offset - Register offset Value - 32-bit value Return Value: None Note: ======================================================================== */ VOID RTMP_PCI_Writew( IN ULONG Value, IN VOID *pAddr) { writew(Value, pAddr); }
/* Load adapter from the memory image of the CYCX firmware module. * o verify firmware integrity and compatibility * o start adapter up */ static int load_cyc2x(struct cycx_hw *hw, struct cycx_firmware *cfm, u32 len) { int i, j; struct cycx_fw_header *img_hdr; u8 *reset_image, *data_image, *code_image; void __iomem *pt_cycld = hw->dpmbase + 0x400; u16 cksum; /* Announce */ // printk(KERN_INFO "%s: firmware signature=\"%s\"\n", modname, ; /* Verify firmware signature */ if (strcmp(cfm->signature, CFM_SIGNATURE)) { // printk(KERN_ERR "%s:load_cyc2x: not Cyclom-2X firmware!\n", ; return -EINVAL; } ; /* Verify firmware module format version */ if (cfm->version != CFM_VERSION) { // printk(KERN_ERR "%s:%s: firmware format %u rejected! " // "Expecting %u.\n", ; return -EINVAL; } /* Verify firmware module length and checksum */ cksum = checksum((u8*)&cfm->info, sizeof(struct cycx_fw_info) + cfm->info.codesize); /* FIXME cfm->info.codesize is off by 2 if (((len - sizeof(struct cycx_firmware) - 1) != cfm->info.codesize) || */ if (cksum != cfm->checksum) { // printk(KERN_ERR "%s:%s: firmware corrupted!\n", ; // printk(KERN_ERR " cdsize = 0x%x (expected 0x%lx)\n", // len - (int)sizeof(struct cycx_firmware) - 1, ; // printk(KERN_ERR " chksum = 0x%x (expected 0x%x)\n", ; return -EINVAL; } /* If everything is ok, set reset, data and code pointers */ img_hdr = (struct cycx_fw_header *)&cfm->image; #ifdef FIRMWARE_DEBUG ; ; ; ; #endif reset_image = ((u8 *)img_hdr) + sizeof(struct cycx_fw_header); data_image = reset_image + img_hdr->reset_size; code_image = data_image + img_hdr->data_size; /*---- Start load ----*/ /* Announce */ // printk(KERN_INFO "%s: loading firmware %s (ID=%u)...\n", modname, // cfm->descr[0] ? cfm->descr : "unknown firmware", ; for (i = 0 ; i < 5 ; i++) { /* Reset Cyclom hardware */ if (!reset_cyc2x(hw->dpmbase)) { // printk(KERN_ERR "%s: dpm problem or board not found\n", ; return -EINVAL; } /* Load reset.bin */ cycx_reset_boot(hw->dpmbase, reset_image, img_hdr->reset_size); /* reset is waiting for boot */ writew(GEN_POWER_ON, pt_cycld); msleep_interruptible(1 * 1000); for (j = 0 ; j < 3 ; j++) if (!readw(pt_cycld)) goto reset_loaded; else msleep_interruptible(1 * 1000); } ; return -EINVAL; reset_loaded: /* Load data.bin */ if (cycx_data_boot(hw->dpmbase, data_image, img_hdr->data_size)) { ; return -EINVAL; } /* Load code.bin */ if (cycx_code_boot(hw->dpmbase, code_image, img_hdr->code_size)) { ; return -EINVAL; } /* Prepare boot-time configuration data */ cycx_bootcfg(hw); /* kick-off CPU */ cycx_start(hw->dpmbase); /* Arthur Ganzert's tip: wait a while after the firmware loading... seg abr 26 17:17:12 EST 1999 - acme */ msleep_interruptible(7 * 1000); ; /* enable interrupts */ cycx_inten(hw); return 0; }
static inline void sh_sdhi_writew(struct sh_sdhi_host *host, int reg, u16 val) { writew(val, host->addr + (reg << host->bus_shift)); }
/* * omap_cpu needs to transfer data to ASTORIA EP buffer */ static void cy_service_e_p_dma_write_request( cy_as_omap_dev_kernel *dev_p, uint8_t ep) { uint16_t addr; uint16_t v = 0, i = 0; uint32_t size; uint16_t *dptr; register void *write_addr ; register uint16_t a,b,c,d ; cy_as_hal_device_tag tag = (cy_as_hal_device_tag)dev_p ; /* * note: size here its the size of the dma transfer could be * anything > 0 && < P_PORT packet size */ size = end_points[ep].dma_xfer_sz ; dptr = end_points[ep].data_p ; write_addr = (void *) (dev_p->m_vma_addr_base + CYAS_DEV_CALC_EP_ADDR(ep)) ; /* * perform the soft DMA transfer, soft in this case */ if (size){ /* * Now, write the data to the device */ for(i = size/8 ; i > 0 ; i--) { a = *dptr++ ; b = *dptr++ ; c = *dptr++ ; d = *dptr++ ; writew (a, write_addr) ; writew (b, write_addr) ; writew (c, write_addr) ; writew (d, write_addr) ; } switch ((size & 7)/2) { case 3: writew (*dptr, write_addr) ; dptr++ ; case 2: writew (*dptr, write_addr) ; dptr++ ; case 1: writew (*dptr, write_addr) ; dptr++ ; break ; } if (size & 1) { uint16_t v = *((uint8_t *)dptr) ; writew (v, write_addr); } } end_points[ep].seg_xfer_cnt += size; end_points[ep].req_xfer_cnt += size; /* * pre-advance data pointer * (if it's outside sg list it will be reset anyway) */ end_points[ep].data_p += size; /* * now clear DMAVAL bit to indicate we are done * transferring data and that the data can now be * sent via USB to the USB host, sent to storage, * or used internally. */ addr = CY_AS_MEM_P0_EP2_DMA_REG + ep - 2 ; cy_as_hal_write_register(tag, addr, size) ; /* * finally, tell the USB subsystem that the * data is gone and we can accept the * next request if one exists. */ if (prep_for_next_xfer(tag, ep)) { /* * There is more data to go. Re-init the WestBridge DMA side */ v = end_points[ep].dma_xfer_sz | CY_AS_MEM_P0_E_pn_DMA_REG_DMAVAL ; cy_as_hal_write_register(tag, addr, v) ; } else { end_points[ep].pending = cy_false ; end_points[ep].type = cy_as_hal_none ; end_points[ep].buffer_valid = cy_false ; /* * notify the API that we are done with rq on this EP */ if (callback) { /* * this callback will wake up the process that might be * sleeping on the EP which data is being transferred */ callback(tag, ep, end_points[ep].req_xfer_cnt, CY_AS_ERROR_SUCCESS); } } }
/* * Miscellaneous platform dependent initializations */ int board_early_init_f(void) { u16 pio_out_cfg = 0x0000; /* Configure General Purpose Bus timing */ writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt); writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw); writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff); writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw); writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff); writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw); writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff); /* Configure Programmable Input/Output Pins */ writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0); writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16); writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16); writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0); writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs); writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel); /* * Turn off top board * Set StrataFlash chips to 16-bit width * Set StrataFlash chips to normal (non reset/power down) mode */ pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR; pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH; pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE; pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE; writew(pio_out_cfg, &sc520_mmcr->pioset15_0); /* Turn off auxiliary power output */ writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0); /* Clear FPGA program mode */ writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16); enet_setup_pars(); /* Disable Watchdog */ writew(0x3333, &sc520_mmcr->wdtmrctl); writew(0xcccc, &sc520_mmcr->wdtmrctl); writew(0x0000, &sc520_mmcr->wdtmrctl); /* Chip Select Configuration */ writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl); writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl); writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl); writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl); writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl); writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl); writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl); writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb); /* enable posted-writes */ writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl); return 0; }
/* * imx_keypad_check_for_events is the timer handler. */ static void imx_keypad_check_for_events(unsigned long data) { struct imx_keypad *keypad = (struct imx_keypad *) data; unsigned short matrix_volatile_state[MAX_MATRIX_KEY_COLS]; unsigned short reg_val; bool state_changed, is_zero_matrix; int i; memset(matrix_volatile_state, 0, sizeof(matrix_volatile_state)); imx_keypad_scan_matrix(keypad, matrix_volatile_state); state_changed = false; for (i = 0; i < MAX_MATRIX_KEY_COLS; i++) { if ((keypad->cols_en_mask & (1 << i)) == 0) continue; if (keypad->matrix_unstable_state[i] ^ matrix_volatile_state[i]) { state_changed = true; break; } } /* * If the matrix state is changed from the previous scan * (Re)Begin the debouncing process, saving the new state in * keypad->matrix_unstable_state. * else * Increase the count of number of scans with a stable state. */ if (state_changed) { memcpy(keypad->matrix_unstable_state, matrix_volatile_state, sizeof(matrix_volatile_state)); keypad->stable_count = 0; } else keypad->stable_count++; /* * If the matrix is not as stable as we want reschedule scan * in the near future. */ if (keypad->stable_count < IMX_KEYPAD_SCANS_FOR_STABILITY) { mod_timer(&keypad->check_matrix_timer, jiffies + msecs_to_jiffies(10)); return; } /* * If the matrix state is stable, fire the events and save the new * stable state. Note, if the matrix is kept stable for longer * (keypad->stable_count > IMX_KEYPAD_SCANS_FOR_STABILITY) all * events have already been generated. */ if (keypad->stable_count == IMX_KEYPAD_SCANS_FOR_STABILITY) { imx_keypad_fire_events(keypad, matrix_volatile_state); memcpy(keypad->matrix_stable_state, matrix_volatile_state, sizeof(matrix_volatile_state)); } is_zero_matrix = true; for (i = 0; i < MAX_MATRIX_KEY_COLS; i++) { if (matrix_volatile_state[i] != 0) { is_zero_matrix = false; break; } } if (is_zero_matrix) { /* * All keys have been released. Enable only the KDI * interrupt for future key presses (clear the KDI * status bit and its sync chain before that). */ reg_val = readw(keypad->mmio_base + KPSR); reg_val |= KBD_STAT_KPKD | KBD_STAT_KDSC; writew(reg_val, keypad->mmio_base + KPSR); reg_val = readw(keypad->mmio_base + KPSR); reg_val |= KBD_STAT_KDIE; reg_val &= ~KBD_STAT_KRIE; writew(reg_val, keypad->mmio_base + KPSR); } else { /* * Some keys are still pressed. Schedule a rescan in * attempt to detect multiple key presses and enable * the KRI interrupt to react quickly to key release * event. */ mod_timer(&keypad->check_matrix_timer, jiffies + msecs_to_jiffies(60)); reg_val = readw(keypad->mmio_base + KPSR); reg_val |= KBD_STAT_KPKR | KBD_STAT_KRSS; writew(reg_val, keypad->mmio_base + KPSR); reg_val = readw(keypad->mmio_base + KPSR); reg_val |= KBD_STAT_KRIE; reg_val &= ~KBD_STAT_KDIE; writew(reg_val, keypad->mmio_base + KPSR); } }
static int __init coh901327_probe(struct platform_device *pdev) { int ret; u16 val; struct resource *res; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENOENT; parent = &pdev->dev; physize = resource_size(res); phybase = res->start; if (request_mem_region(phybase, physize, DRV_NAME) == NULL) { ret = -EBUSY; goto out; } virtbase = ioremap(phybase, physize); if (!virtbase) { ret = -ENOMEM; goto out_no_remap; } clk = clk_get(&pdev->dev, NULL); if (IS_ERR(clk)) { ret = PTR_ERR(clk); dev_err(&pdev->dev, "could not get clock\n"); goto out_no_clk; } ret = clk_enable(clk); if (ret) { dev_err(&pdev->dev, "could not enable clock\n"); goto out_no_clk_enable; } val = readw(virtbase + U300_WDOG_SR); switch (val) { case U300_WDOG_SR_STATUS_TIMED_OUT: dev_info(&pdev->dev, "watchdog timed out since last chip reset!\n"); coh901327_wdt.bootstatus |= WDIOF_CARDRESET; break; case U300_WDOG_SR_STATUS_NORMAL: dev_info(&pdev->dev, "in normal status, no timeouts have occurred.\n"); break; default: dev_info(&pdev->dev, "contains an illegal status code (%08x)\n", val); break; } val = readw(virtbase + U300_WDOG_D2R); switch (val) { case U300_WDOG_D2R_DISABLE_STATUS_DISABLED: dev_info(&pdev->dev, "currently disabled.\n"); break; case U300_WDOG_D2R_DISABLE_STATUS_ENABLED: dev_info(&pdev->dev, "currently enabled! (disabling it now)\n"); coh901327_disable(); break; default: dev_err(&pdev->dev, "contains an illegal enable/disable code (%08x)\n", val); break; } writew(U300_WDOG_SR_RESET_STATUS_RESET, virtbase + U300_WDOG_SR); irq = platform_get_irq(pdev, 0); if (request_irq(irq, coh901327_interrupt, 0, DRV_NAME " Bark", pdev)) { ret = -EIO; goto out_no_irq; } clk_disable(clk); if (margin < 1 || margin > 327) margin = 60; coh901327_wdt.timeout = margin; ret = watchdog_register_device(&coh901327_wdt); if (ret == 0) dev_info(&pdev->dev, "initialized. timer margin=%d sec\n", margin); else goto out_no_wdog; return 0; out_no_wdog: free_irq(irq, pdev); out_no_irq: clk_disable(clk); out_no_clk_enable: clk_put(clk); out_no_clk: iounmap(virtbase); out_no_remap: release_mem_region(phybase, SZ_4K); out: return ret; }
static void pl011_set_termios(struct uart_port *port, struct termios *termios, struct termios *old) { unsigned int lcr_h, old_cr; unsigned long flags; unsigned int baud, quot; /* * Ask the core to calculate the divisor for us. */ baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16); quot = port->uartclk * 4 / baud; switch (termios->c_cflag & CSIZE) { case CS5: lcr_h = UART01x_LCRH_WLEN_5; break; case CS6: lcr_h = UART01x_LCRH_WLEN_6; break; case CS7: lcr_h = UART01x_LCRH_WLEN_7; break; default: // CS8 lcr_h = UART01x_LCRH_WLEN_8; break; } if (termios->c_cflag & CSTOPB) lcr_h |= UART01x_LCRH_STP2; if (termios->c_cflag & PARENB) { lcr_h |= UART01x_LCRH_PEN; if (!(termios->c_cflag & PARODD)) lcr_h |= UART01x_LCRH_EPS; } if (port->fifosize > 1) lcr_h |= UART01x_LCRH_FEN; spin_lock_irqsave(&port->lock, flags); /* * Update the per-port timeout. */ uart_update_timeout(port, termios->c_cflag, baud); port->read_status_mask = UART01x_RSR_OE; if (termios->c_iflag & INPCK) port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; if (termios->c_iflag & (BRKINT | PARMRK)) port->read_status_mask |= UART01x_RSR_BE; /* * Characters to ignore */ port->ignore_status_mask = 0; if (termios->c_iflag & IGNPAR) port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; if (termios->c_iflag & IGNBRK) { port->ignore_status_mask |= UART01x_RSR_BE; /* * If we're ignoring parity and break indicators, * ignore overruns too (for real raw support). */ if (termios->c_iflag & IGNPAR) port->ignore_status_mask |= UART01x_RSR_OE; } /* * Ignore all characters if CREAD is not set. */ if ((termios->c_cflag & CREAD) == 0) port->ignore_status_mask |= UART_DUMMY_RSR_RX; if (UART_ENABLE_MS(port, termios->c_cflag)) pl011_enable_ms(port); /* first, disable everything */ old_cr = readw(port->membase + UART011_CR); writew(0, port->membase + UART011_CR); /* Set baud rate */ writew(quot & 0x3f, port->membase + UART011_FBRD); writew(quot >> 6, port->membase + UART011_IBRD); /* * ----------v----------v----------v----------v----- * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L * ----------^----------^----------^----------^----- */ writew(lcr_h, port->membase + UART011_LCRH); writew(old_cr, port->membase + UART011_CR); spin_unlock_irqrestore(&port->lock, flags); }
void fastcall iowrite16(u16 val, void __iomem *addr) { writew(val, addr); }
static inline void ad1889_writew(struct snd_ad1889 *chip, unsigned reg, u16 val) { writew(val, chip->iobase + reg); }
static void armflash_write16(struct map_info *map, __u16 d, unsigned long adr) { writew(d, adr + map->map_priv_2); }
/* ** config.rio has taken a dislike to one of the gross maps entries. ** if the entry is suitably inactive, then we can gob on it and remove ** it from the table. */ int RIODeleteRta(struct rio_info *p, struct Map *MapP) { int host, entry, port, link; int SysPort; struct Host *HostP; struct Map *HostMapP; struct Port *PortP; int work_done = 0; unsigned long lock_flags, sem_flags; rio_dprintk(RIO_DEBUG_TABLE, "Delete entry on host %x, rta %x\n", MapP->HostUniqueNum, MapP->RtaUniqueNum); for (host = 0; host < p->RIONumHosts; host++) { HostP = &p->RIOHosts[host]; rio_spin_lock_irqsave(&HostP->HostLock, lock_flags); if ((HostP->Flags & RUN_STATE) != RC_RUNNING) { rio_spin_unlock_irqrestore(&HostP->HostLock, lock_flags); continue; } for (entry = 0; entry < MAX_RUP; entry++) { if (MapP->RtaUniqueNum == HostP->Mapping[entry].RtaUniqueNum) { HostMapP = &HostP->Mapping[entry]; rio_dprintk(RIO_DEBUG_TABLE, "Found entry offset %d on host %s\n", entry, HostP->Name); /* ** Check all four links of the unit are disconnected */ for (link = 0; link < LINKS_PER_UNIT; link++) { if (HostMapP->Topology[link].Unit != ROUTE_DISCONNECT) { rio_dprintk(RIO_DEBUG_TABLE, "Entry is in use and cannot be deleted!\n"); p->RIOError.Error = UNIT_IS_IN_USE; rio_spin_unlock_irqrestore(&HostP->HostLock, lock_flags); return -EBUSY; } } /* ** Slot has been allocated, BUT not booted/routed/ ** connected/selected or anything else-ed */ SysPort = HostMapP->SysPort; if (SysPort != NO_PORT) { for (port = SysPort; port < SysPort + PORTS_PER_RTA; port++) { PortP = p->RIOPortp[port]; rio_dprintk(RIO_DEBUG_TABLE, "Unmap port\n"); rio_spin_lock_irqsave(&PortP->portSem, sem_flags); PortP->Mapped = 0; if (PortP->State & (RIO_MOPEN | RIO_LOPEN)) { rio_dprintk(RIO_DEBUG_TABLE, "Gob on port\n"); PortP->TxBufferIn = PortP->TxBufferOut = 0; /* What should I do wakeup( &PortP->TxBufferIn ); wakeup( &PortP->TxBufferOut); */ PortP->InUse = NOT_INUSE; /* What should I do wakeup( &PortP->InUse ); signal(PortP->TtyP->t_pgrp,SIGKILL); ttyflush(PortP->TtyP,(FREAD|FWRITE)); */ PortP->State |= RIO_CLOSING | RIO_DELETED; } /* ** For the second slot of a 16 port RTA, the ** driver needs to reset the changes made to ** the phb to port mappings in RIORouteRup. */ if (PortP->SecondBlock) { u16 dest_unit = HostMapP->ID; u16 dest_port = port - SysPort; u16 __iomem *TxPktP; struct PKT __iomem *Pkt; for (TxPktP = PortP->TxStart; TxPktP <= PortP->TxEnd; TxPktP++) { /* ** *TxPktP is the pointer to the ** transmit packet on the host card. ** This needs to be translated into ** a 32 bit pointer so it can be ** accessed from the driver. */ Pkt = (struct PKT __iomem *) RIO_PTR(HostP->Caddr, readw(&*TxPktP)); rio_dprintk(RIO_DEBUG_TABLE, "Tx packet (%x) destination: Old %x:%x New %x:%x\n", readw(TxPktP), readb(&Pkt->dest_unit), readb(&Pkt->dest_port), dest_unit, dest_port); writew(dest_unit, &Pkt->dest_unit); writew(dest_port, &Pkt->dest_port); } rio_dprintk(RIO_DEBUG_TABLE, "Port %d phb destination: Old %x:%x New %x:%x\n", port, readb(&PortP->PhbP->destination) & 0xff, (readb(&PortP->PhbP->destination) >> 8) & 0xff, dest_unit, dest_port); writew(dest_unit + (dest_port << 8), &PortP->PhbP->destination); } rio_spin_unlock_irqrestore(&PortP->portSem, sem_flags); } } rio_dprintk(RIO_DEBUG_TABLE, "Entry nulled.\n"); memset(HostMapP, 0, sizeof(struct Map)); work_done++; } }
static int RIOScrub(int op, u8 __iomem *ram, int size) { int off; unsigned char oldbyte; unsigned char newbyte; unsigned char invbyte; unsigned short oldword; unsigned short newword; unsigned short invword; unsigned short swapword; if (op) { oldbyte = val[op-1]; oldword = oldbyte | (oldbyte<<8); } else oldbyte = oldword = 0; /* Tell the compiler we've initilalized them. */ newbyte = val[op]; newword = newbyte | (newbyte<<8); invbyte = ~newbyte; invword = invbyte | (invbyte<<8); /* ** Check that the RAM contains the value that should have been left there ** by the previous test (not applicable for pass zero) */ if (op) { for (off=0; off<size; off++) { if (readb(ram + off) != oldbyte) { rio_dprintk (RIO_DEBUG_INIT, "RIO-init: Byte Pre Check 1: BYTE at offset 0x%x should have been=%x, was=%x\n", off, oldbyte, readb(ram + off)); return RIO_FAIL; } } for (off=0; off<size; off+=2) { if (readw(ram + off) != oldword) { rio_dprintk (RIO_DEBUG_INIT, "RIO-init: Word Pre Check: WORD at offset 0x%x should have been=%x, was=%x\n",off,oldword, readw(ram + off)); rio_dprintk (RIO_DEBUG_INIT, "RIO-init: Word Pre Check: BYTE at offset 0x%x is %x BYTE at offset 0x%x is %x\n", off, readb(ram + off), off+1, readb(ram+off+1)); return RIO_FAIL; } } } /* ** Now write the INVERSE of the test data into every location, using ** BYTE write operations, first checking before each byte is written ** that the location contains the old value still, and checking after ** the write that the location contains the data specified - this is ** the BYTE read/write test. */ for (off=0; off<size; off++) { if (op && (readb(ram + off) != oldbyte)) { rio_dprintk (RIO_DEBUG_INIT, "RIO-init: Byte Pre Check 2: BYTE at offset 0x%x should have been=%x, was=%x\n", off, oldbyte, readb(ram + off)); return RIO_FAIL; } writeb(invbyte, ram + off); if (readb(ram + off) != invbyte) { rio_dprintk (RIO_DEBUG_INIT, "RIO-init: Byte Inv Check: BYTE at offset 0x%x should have been=%x, was=%x\n", off, invbyte, readb(ram + off)); return RIO_FAIL; } } /* ** now, use WORD operations to write the test value into every location, ** check as before that the location contains the previous test value ** before overwriting, and that it contains the data value written ** afterwards. ** This is the WORD operation test. */ for (off=0; off<size; off+=2) { if (readw(ram + off) != invword) { rio_dprintk (RIO_DEBUG_INIT, "RIO-init: Word Inv Check: WORD at offset 0x%x should have been=%x, was=%x\n", off, invword, readw(ram + off)); rio_dprintk (RIO_DEBUG_INIT, "RIO-init: Word Inv Check: BYTE at offset 0x%x is %x BYTE at offset 0x%x is %x\n", off, readb(ram + off), off+1, readb(ram+off+1)); return RIO_FAIL; } writew(newword, ram + off); if ( readw(ram + off) != newword ) { rio_dprintk (RIO_DEBUG_INIT, "RIO-init: Post Word Check 1: WORD at offset 0x%x should have been=%x, was=%x\n", off, newword, readw(ram + off)); rio_dprintk (RIO_DEBUG_INIT, "RIO-init: Post Word Check 1: BYTE at offset 0x%x is %x BYTE at offset 0x%x is %x\n", off, readb(ram + off), off+1, readb(ram + off + 1)); return RIO_FAIL; } } /* ** now run through the block of memory again, first in byte mode ** then in word mode, and check that all the locations contain the ** required test data. */ for (off=0; off<size; off++) { if (readb(ram + off) != newbyte) { rio_dprintk (RIO_DEBUG_INIT, "RIO-init: Post Byte Check: BYTE at offset 0x%x should have been=%x, was=%x\n", off, newbyte, readb(ram + off)); return RIO_FAIL; } } for (off=0; off<size; off+=2) { if (readw(ram + off) != newword ) { rio_dprintk (RIO_DEBUG_INIT, "RIO-init: Post Word Check 2: WORD at offset 0x%x should have been=%x, was=%x\n", off, newword, readw(ram + off)); rio_dprintk (RIO_DEBUG_INIT, "RIO-init: Post Word Check 2: BYTE at offset 0x%x is %x BYTE at offset 0x%x is %x\n", off, readb(ram + off), off+1, readb(ram + off + 1)); return RIO_FAIL; } } /* ** time to check out byte swapping errors */ swapword = invbyte | (newbyte << 8); for (off=0; off<size; off+=2) { writeb(invbyte, &ram[off]); writeb(newbyte, &ram[off+1]); } for ( off=0; off<size; off+=2 ) { if (readw(ram + off) != swapword) { rio_dprintk (RIO_DEBUG_INIT, "RIO-init: SwapWord Check 1: WORD at offset 0x%x should have been=%x, was=%x\n", off, swapword, readw(ram + off)); rio_dprintk (RIO_DEBUG_INIT, "RIO-init: SwapWord Check 1: BYTE at offset 0x%x is %x BYTE at offset 0x%x is %x\n", off, readb(ram + off), off+1, readb(ram + off + 1)); return RIO_FAIL; } writew(~swapword, ram + off); } for (off=0; off<size; off+=2) { if (readb(ram + off) != newbyte) { rio_dprintk (RIO_DEBUG_INIT, "RIO-init: SwapWord Check 2: BYTE at offset 0x%x should have been=%x, was=%x\n", off, newbyte, readb(ram + off)); return RIO_FAIL; } if (readb(ram + off + 1) != invbyte) { rio_dprintk (RIO_DEBUG_INIT, "RIO-init: SwapWord Check 2: BYTE at offset 0x%x should have been=%x, was=%x\n", off+1, invbyte, readb(ram + off + 1)); return RIO_FAIL; } writew(newword, ram + off); } return 0; }
void cycx_intr(struct cycx_hw *hw) { writew(0, hw->dpmbase + GEN_CYCX_INTR); }
/* * Handle uplink data, this is currently for the modem port * Return 1 - ok * Return 0 - toggle field are out of sync */ static int handle_data_ul(struct nozomi *dc, enum port_type port, u16 read_iir) { u8 *toggle = &(dc->port[port].toggle_ul); if (*toggle == 0 && read_iir & MDM_UL1) { dc->last_ier &= ~MDM_UL; writew(dc->last_ier, dc->reg_ier); if (send_data(port, dc)) { writew(MDM_UL1, dc->reg_fcr); dc->last_ier = dc->last_ier | MDM_UL; writew(dc->last_ier, dc->reg_ier); *toggle = !*toggle; } if (read_iir & MDM_UL2) { dc->last_ier &= ~MDM_UL; writew(dc->last_ier, dc->reg_ier); if (send_data(port, dc)) { writew(MDM_UL2, dc->reg_fcr); dc->last_ier = dc->last_ier | MDM_UL; writew(dc->last_ier, dc->reg_ier); *toggle = !*toggle; } } } else if (*toggle == 1 && read_iir & MDM_UL2) { dc->last_ier &= ~MDM_UL; writew(dc->last_ier, dc->reg_ier); if (send_data(port, dc)) { writew(MDM_UL2, dc->reg_fcr); dc->last_ier = dc->last_ier | MDM_UL; writew(dc->last_ier, dc->reg_ier); *toggle = !*toggle; } if (read_iir & MDM_UL1) { dc->last_ier &= ~MDM_UL; writew(dc->last_ier, dc->reg_ier); if (send_data(port, dc)) { writew(MDM_UL1, dc->reg_fcr); dc->last_ier = dc->last_ier | MDM_UL; writew(dc->last_ier, dc->reg_ier); *toggle = !*toggle; } } } else { writew(read_iir & MDM_UL, dc->reg_fcr); dev_err(&dc->pdev->dev, "port out of sync!\n"); return 0; } return 1; }
static inline void serial_out(struct uart_omap_port *up, int offset, int value) { offset <<= up->port.regshift; writew(value, up->port.membase + offset); }
static irqreturn_t interrupt_handler(int irq, void *dev_id) { struct nozomi *dc = dev_id; unsigned int a; u16 read_iir; if (!dc) return IRQ_NONE; spin_lock(&dc->spin_mutex); read_iir = readw(dc->reg_iir); /* Card removed */ if (read_iir == (u16)-1) goto none; /* * Just handle interrupt enabled in IER * (by masking with dc->last_ier) */ read_iir &= dc->last_ier; if (read_iir == 0) goto none; DBG4("%s irq:0x%04X, prev:0x%04X", interrupt2str(read_iir), read_iir, dc->last_ier); if (read_iir & RESET) { if (unlikely(!nozomi_read_config_table(dc))) { dc->last_ier = 0x0; writew(dc->last_ier, dc->reg_ier); dev_err(&dc->pdev->dev, "Could not read status from " "card, we should disable interface\n"); } else { writew(RESET, dc->reg_fcr); } /* No more useful info if this was the reset interrupt. */ goto exit_handler; } if (read_iir & CTRL_UL) { DBG1("CTRL_UL"); dc->last_ier &= ~CTRL_UL; writew(dc->last_ier, dc->reg_ier); if (send_flow_control(dc)) { writew(CTRL_UL, dc->reg_fcr); dc->last_ier = dc->last_ier | CTRL_UL; writew(dc->last_ier, dc->reg_ier); } } if (read_iir & CTRL_DL) { receive_flow_control(dc); writew(CTRL_DL, dc->reg_fcr); } if (read_iir & MDM_DL) { if (!handle_data_dl(dc, PORT_MDM, &(dc->port[PORT_MDM].toggle_dl), read_iir, MDM_DL1, MDM_DL2)) { dev_err(&dc->pdev->dev, "MDM_DL out of sync!\n"); goto exit_handler; } } if (read_iir & MDM_UL) { if (!handle_data_ul(dc, PORT_MDM, read_iir)) { dev_err(&dc->pdev->dev, "MDM_UL out of sync!\n"); goto exit_handler; } } if (read_iir & DIAG_DL) { if (!handle_data_dl(dc, PORT_DIAG, &(dc->port[PORT_DIAG].toggle_dl), read_iir, DIAG_DL1, DIAG_DL2)) { dev_err(&dc->pdev->dev, "DIAG_DL out of sync!\n"); goto exit_handler; } } if (read_iir & DIAG_UL) { dc->last_ier &= ~DIAG_UL; writew(dc->last_ier, dc->reg_ier); if (send_data(PORT_DIAG, dc)) { writew(DIAG_UL, dc->reg_fcr); dc->last_ier = dc->last_ier | DIAG_UL; writew(dc->last_ier, dc->reg_ier); } } if (read_iir & APP1_DL) { if (receive_data(PORT_APP1, dc)) writew(APP1_DL, dc->reg_fcr); } if (read_iir & APP1_UL) { dc->last_ier &= ~APP1_UL; writew(dc->last_ier, dc->reg_ier); if (send_data(PORT_APP1, dc)) { writew(APP1_UL, dc->reg_fcr); dc->last_ier = dc->last_ier | APP1_UL; writew(dc->last_ier, dc->reg_ier); } } if (read_iir & APP2_DL) { if (receive_data(PORT_APP2, dc)) writew(APP2_DL, dc->reg_fcr); } if (read_iir & APP2_UL) { dc->last_ier &= ~APP2_UL; writew(dc->last_ier, dc->reg_ier); if (send_data(PORT_APP2, dc)) { writew(APP2_UL, dc->reg_fcr); dc->last_ier = dc->last_ier | APP2_UL; writew(dc->last_ier, dc->reg_ier); } } exit_handler: spin_unlock(&dc->spin_mutex); for (a = 0; a < NOZOMI_MAX_PORTS; a++) if (test_and_clear_bit(a, &dc->flip)) tty_flip_buffer_push(&dc->port[a].port); return IRQ_HANDLED; none: spin_unlock(&dc->spin_mutex); return IRQ_NONE; }
int dram_init(void) { static const struct ddr3_jedec_timings timings = { .tinit = 5, .trst_pwron = 80000, .cke_inactive = 200000, .wrlat = 5, .caslat_lin = 12, .trc = 21, .trrd = 4, .tccd = 4, .tbst_int_interval = 0, .tfaw = 20, .trp = 6, .twtr = 4, .tras_min = 15, .tmrd = 4, .trtp = 4, .tras_max = 28080, .tmod = 12, .tckesr = 4, .tcke = 3, .trcd_int = 6, .tras_lockout = 0, .tdal = 12, .bstlen = 3, .tdll = 512, .trp_ab = 6, .tref = 3120, .trfc = 44, .tref_int = 0, .tpdex = 3, .txpdll = 10, .txsnr = 48, .txsr = 468, .cksrx = 5, .cksre = 5, .freq_chg_en = 0, .zqcl = 256, .zqinit = 512, .zqcs = 64, .ref_per_zq = 64, .zqcs_rotate = 0, .aprebit = 10, .cmd_age_cnt = 64, .age_cnt = 64, .q_fullness = 7, .odt_rd_mapcs0 = 0, .odt_wr_mapcs0 = 1, .wlmrd = 40, .wldqsen = 25, }; ddrmc_setup_iomux(NULL, 0); ddrmc_ctrl_init_ddr3(&timings, vf610twr_cr_settings, NULL, 1, 3); gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } static void setup_iomux_uart(void) { static const iomux_v3_cfg_t uart1_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } static void setup_iomux_enet(void) { static const iomux_v3_cfg_t enet0_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); } static void setup_iomux_i2c(void) { static const iomux_v3_cfg_t i2c0_pads[] = { VF610_PAD_PTB14__I2C0_SCL, VF610_PAD_PTB15__I2C0_SDA, }; imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); } #ifdef CONFIG_NAND_VF610_NFC static void setup_iomux_nfc(void) { static const iomux_v3_cfg_t nfc_pads[] = { VF610_PAD_PTD31__NF_IO15, VF610_PAD_PTD30__NF_IO14, VF610_PAD_PTD29__NF_IO13, VF610_PAD_PTD28__NF_IO12, VF610_PAD_PTD27__NF_IO11, VF610_PAD_PTD26__NF_IO10, VF610_PAD_PTD25__NF_IO9, VF610_PAD_PTD24__NF_IO8, VF610_PAD_PTD23__NF_IO7, VF610_PAD_PTD22__NF_IO6, VF610_PAD_PTD21__NF_IO5, VF610_PAD_PTD20__NF_IO4, VF610_PAD_PTD19__NF_IO3, VF610_PAD_PTD18__NF_IO2, VF610_PAD_PTD17__NF_IO1, VF610_PAD_PTD16__NF_IO0, VF610_PAD_PTB24__NF_WE_B, VF610_PAD_PTB25__NF_CE0_B, VF610_PAD_PTB27__NF_RE_B, VF610_PAD_PTC26__NF_RB_B, VF610_PAD_PTC27__NF_ALE, VF610_PAD_PTC28__NF_CLE }; imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); } #endif static void setup_iomux_qspi(void) { static const iomux_v3_cfg_t qspi0_pads[] = { VF610_PAD_PTD0__QSPI0_A_QSCK, VF610_PAD_PTD1__QSPI0_A_CS0, VF610_PAD_PTD2__QSPI0_A_DATA3, VF610_PAD_PTD3__QSPI0_A_DATA2, VF610_PAD_PTD4__QSPI0_A_DATA1, VF610_PAD_PTD5__QSPI0_A_DATA0, VF610_PAD_PTD7__QSPI0_B_QSCK, VF610_PAD_PTD8__QSPI0_B_CS0, VF610_PAD_PTD9__QSPI0_B_DATA3, VF610_PAD_PTD10__QSPI0_B_DATA2, VF610_PAD_PTD11__QSPI0_B_DATA1, VF610_PAD_PTD12__QSPI0_B_DATA0, }; imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); } #ifdef CONFIG_FSL_ESDHC struct fsl_esdhc_cfg esdhc_cfg[1] = { {ESDHC1_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) { /* eSDHC1 is always present */ return 1; } int board_mmc_init(bd_t *bis) { static const iomux_v3_cfg_t esdhc1_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), }; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); imx_iomux_v3_setup_multiple_pads( esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); } #endif static void clock_init(void) { struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, CCM_CCGR0_UART1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | CCM_CCGR2_QSPI0_CTRL_MASK); clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, CCM_CCGR7_SDHC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, CCM_CCGR10_NFC_CTRL_MASK); clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | CCM_CACRR_ARM_CLK_DIV(0)); clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) | CCM_CSCMR1_NFC_CLK_SEL(0)); clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, CCM_CSCDR1_RMII_CLK_EN); clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | CCM_CSCDR2_NFC_EN); clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) | CCM_CSCDR3_NFC_PRE_DIV(5)); clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, CCM_CSCMR2_RMII_CLK_SEL(0)); } static void mscm_init(void) { struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; int i; for (i = 0; i < MSCM_IRSPRC_NUM; i++) writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); } int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) phydev->drv->config(phydev); return 0; } int board_early_init_f(void) { clock_init(); mscm_init(); setup_iomux_uart(); setup_iomux_enet(); setup_iomux_i2c(); setup_iomux_qspi(); #ifdef CONFIG_NAND_VF610_NFC setup_iomux_nfc(); #endif return 0; }
/* Allocate memory for one device */ static int nozomi_card_init(struct pci_dev *pdev, const struct pci_device_id *ent) { resource_size_t start; int ret; struct nozomi *dc = NULL; int ndev_idx; int i; dev_dbg(&pdev->dev, "Init, new card found\n"); for (ndev_idx = 0; ndev_idx < ARRAY_SIZE(ndevs); ndev_idx++) if (!ndevs[ndev_idx]) break; if (ndev_idx >= ARRAY_SIZE(ndevs)) { dev_err(&pdev->dev, "no free tty range for this card left\n"); ret = -EIO; goto err; } dc = kzalloc(sizeof(struct nozomi), GFP_KERNEL); if (unlikely(!dc)) { dev_err(&pdev->dev, "Could not allocate memory\n"); ret = -ENOMEM; goto err_free; } dc->pdev = pdev; ret = pci_enable_device(dc->pdev); if (ret) { dev_err(&pdev->dev, "Failed to enable PCI Device\n"); goto err_free; } ret = pci_request_regions(dc->pdev, NOZOMI_NAME); if (ret) { dev_err(&pdev->dev, "I/O address 0x%04x already in use\n", (int) /* nozomi_private.io_addr */ 0); goto err_disable_device; } start = pci_resource_start(dc->pdev, 0); if (start == 0) { dev_err(&pdev->dev, "No I/O address for card detected\n"); ret = -ENODEV; goto err_rel_regs; } /* Find out what card type it is */ nozomi_get_card_type(dc); dc->base_addr = ioremap_nocache(start, dc->card_type); if (!dc->base_addr) { dev_err(&pdev->dev, "Unable to map card MMIO\n"); ret = -ENODEV; goto err_rel_regs; } dc->send_buf = kmalloc(SEND_BUF_MAX, GFP_KERNEL); if (!dc->send_buf) { dev_err(&pdev->dev, "Could not allocate send buffer?\n"); ret = -ENOMEM; goto err_free_sbuf; } for (i = PORT_MDM; i < MAX_PORT; i++) { if (kfifo_alloc(&dc->port[i].fifo_ul, FIFO_BUFFER_SIZE_UL, GFP_KERNEL)) { dev_err(&pdev->dev, "Could not allocate kfifo buffer\n"); ret = -ENOMEM; goto err_free_kfifo; } } spin_lock_init(&dc->spin_mutex); nozomi_setup_private_data(dc); /* Disable all interrupts */ dc->last_ier = 0; writew(dc->last_ier, dc->reg_ier); ret = request_irq(pdev->irq, &interrupt_handler, IRQF_SHARED, NOZOMI_NAME, dc); if (unlikely(ret)) { dev_err(&pdev->dev, "can't request irq %d\n", pdev->irq); goto err_free_kfifo; } DBG1("base_addr: %p", dc->base_addr); make_sysfs_files(dc); dc->index_start = ndev_idx * MAX_PORT; ndevs[ndev_idx] = dc; pci_set_drvdata(pdev, dc); /* Enable RESET interrupt */ dc->last_ier = RESET; iowrite16(dc->last_ier, dc->reg_ier); dc->state = NOZOMI_STATE_ENABLED; for (i = 0; i < MAX_PORT; i++) { struct device *tty_dev; struct port *port = &dc->port[i]; port->dc = dc; tty_port_init(&port->port); port->port.ops = &noz_tty_port_ops; tty_dev = tty_port_register_device(&port->port, ntty_driver, dc->index_start + i, &pdev->dev); if (IS_ERR(tty_dev)) { ret = PTR_ERR(tty_dev); dev_err(&pdev->dev, "Could not allocate tty?\n"); tty_port_destroy(&port->port); goto err_free_tty; } } return 0; err_free_tty: for (i = 0; i < MAX_PORT; ++i) { tty_unregister_device(ntty_driver, dc->index_start + i); tty_port_destroy(&dc->port[i].port); } err_free_kfifo: for (i = 0; i < MAX_PORT; i++) kfifo_free(&dc->port[i].fifo_ul); err_free_sbuf: kfree(dc->send_buf); iounmap(dc->base_addr); err_rel_regs: pci_release_regions(pdev); err_disable_device: pci_disable_device(pdev); err_free: kfree(dc); err: return ret; }
static inline void write_reg(struct omap2_onenand *c, unsigned short value, int reg) { writew(value, c->onenand.base + reg); }
/* * Read configuration table from card under intalization phase * Returns 1 if ok, else 0 */ static int nozomi_read_config_table(struct nozomi *dc) { read_mem32((u32 *) &dc->config_table, dc->base_addr + 0, sizeof(struct config_table)); if (dc->config_table.signature != NOZOMI_CONFIG_MAGIC) { dev_err(&dc->pdev->dev, "ConfigTable Bad! 0x%08X != 0x%08X\n", dc->config_table.signature, NOZOMI_CONFIG_MAGIC); return 0; } if ((dc->config_table.version == 0) || (dc->config_table.toggle.enabled == TOGGLE_VALID)) { int i; DBG1("Second phase, configuring card"); nozomi_setup_memory(dc); dc->port[PORT_MDM].toggle_ul = dc->config_table.toggle.mdm_ul; dc->port[PORT_MDM].toggle_dl = dc->config_table.toggle.mdm_dl; dc->port[PORT_DIAG].toggle_dl = dc->config_table.toggle.diag_dl; DBG1("toggle ports: MDM UL:%d MDM DL:%d, DIAG DL:%d", dc->port[PORT_MDM].toggle_ul, dc->port[PORT_MDM].toggle_dl, dc->port[PORT_DIAG].toggle_dl); dump_table(dc); for (i = PORT_MDM; i < MAX_PORT; i++) { memset(&dc->port[i].ctrl_dl, 0, sizeof(struct ctrl_dl)); memset(&dc->port[i].ctrl_ul, 0, sizeof(struct ctrl_ul)); } /* Enable control channel */ dc->last_ier = dc->last_ier | CTRL_DL; writew(dc->last_ier, dc->reg_ier); dc->state = NOZOMI_STATE_ALLOCATED; dev_info(&dc->pdev->dev, "Initialization OK!\n"); return 1; } if ((dc->config_table.version > 0) && (dc->config_table.toggle.enabled != TOGGLE_VALID)) { u32 offset = 0; DBG1("First phase: pushing upload buffers, clearing download"); dev_info(&dc->pdev->dev, "Version of card: %d\n", dc->config_table.version); /* Here we should disable all I/O over F32. */ nozomi_setup_memory(dc); /* * We should send ALL channel pair tokens back along * with reset token */ /* push upload modem buffers */ write_mem32(dc->port[PORT_MDM].ul_addr[CH_A], (u32 *) &offset, 4); write_mem32(dc->port[PORT_MDM].ul_addr[CH_B], (u32 *) &offset, 4); writew(MDM_UL | DIAG_DL | MDM_DL, dc->reg_fcr); DBG1("First phase done"); } return 1; }
void osl_writew(uint16 v, volatile uint16 *r) { writew(v, r); }
void iowrite16(u16 val, void __iomem *addr) { writew(val, addr); }
static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg, int last) { struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap); u16 val, tcr_val; int ret, wait_result; u32 xfer_len = 0; if (!(pmsg->flags & I2C_M_NOSTART)) { ret = wmt_i2c_wait_bus_not_busy(i2c_dev); if (ret < 0) return ret; } val = readw(i2c_dev->base + REG_CR); val &= ~CR_TX_END; writew(val, i2c_dev->base + REG_CR); val = readw(i2c_dev->base + REG_CR); val &= ~CR_TX_NEXT_NO_ACK; writew(val, i2c_dev->base + REG_CR); if (!(pmsg->flags & I2C_M_NOSTART)) { val = readw(i2c_dev->base + REG_CR); val |= CR_CPU_RDY; writew(val, i2c_dev->base + REG_CR); } if (pmsg->len == 1) { val = readw(i2c_dev->base + REG_CR); val |= CR_TX_NEXT_NO_ACK; writew(val, i2c_dev->base + REG_CR); } reinit_completion(&i2c_dev->complete); if (i2c_dev->mode == I2C_MODE_STANDARD) tcr_val = TCR_STANDARD_MODE; else tcr_val = TCR_FAST_MODE; tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK); writew(tcr_val, i2c_dev->base + REG_TCR); if (pmsg->flags & I2C_M_NOSTART) { val = readw(i2c_dev->base + REG_CR); val |= CR_CPU_RDY; writew(val, i2c_dev->base + REG_CR); } while (xfer_len < pmsg->len) { wait_result = wait_for_completion_timeout(&i2c_dev->complete, 500 * HZ / 1000); if (!wait_result) return -ETIMEDOUT; ret = wmt_check_status(i2c_dev); if (ret) return ret; pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8; xfer_len++; if (xfer_len == pmsg->len - 1) { val = readw(i2c_dev->base + REG_CR); val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY); writew(val, i2c_dev->base + REG_CR); } else { val = readw(i2c_dev->base + REG_CR); val |= CR_CPU_RDY; writew(val, i2c_dev->base + REG_CR); } } return 0; }
static int omap2_onenand_set_async_mode(int cs, void __iomem *onenand_base) { struct gpmc_timings t; u32 reg; int err; const int t_cer = 15; const int t_avdp = 12; const int t_aavdh = 7; const int t_ce = 76; const int t_aa = 76; const int t_oe = 20; const int t_cez = 20; const int t_ds = 30; const int t_wpl = 40; const int t_wph = 30; reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE; writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); memset(&t, 0, sizeof(t)); t.sync_clk = 0; t.cs_on = 0; t.adv_on = 0; t.adv_rd_off = gpmc_round_ns_to_ticks(max_t(int, t_avdp, t_cer)); t.oe_on = t.adv_rd_off + gpmc_round_ns_to_ticks(t_aavdh); t.access = t.adv_on + gpmc_round_ns_to_ticks(t_aa); t.access = max_t(int, t.access, t.cs_on + gpmc_round_ns_to_ticks(t_ce)); t.access = max_t(int, t.access, t.oe_on + gpmc_round_ns_to_ticks(t_oe)); t.oe_off = t.access + gpmc_round_ns_to_ticks(1); t.cs_rd_off = t.oe_off; t.rd_cycle = t.cs_rd_off + gpmc_round_ns_to_ticks(t_cez); t.adv_wr_off = t.adv_rd_off; t.we_on = t.oe_on; if (cpu_is_omap34xx()) { t.wr_data_mux_bus = t.we_on; t.wr_access = t.we_on + gpmc_round_ns_to_ticks(t_ds); } t.we_off = t.we_on + gpmc_round_ns_to_ticks(t_wpl); t.cs_wr_off = t.we_off + gpmc_round_ns_to_ticks(t_wph); t.wr_cycle = t.cs_wr_off + gpmc_round_ns_to_ticks(t_cez); gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, GPMC_CONFIG1_DEVICESIZE_16 | GPMC_CONFIG1_MUXADDDATA); err = gpmc_cs_set_timings(cs, &t); if (err) return err; reg = readw(onenand_base + ONENAND_REG_SYS_CFG1); reg &= ~ONENAND_SYS_CFG1_SYNC_READ & ~ONENAND_SYS_CFG1_SYNC_WRITE; writew(reg, onenand_base + ONENAND_REG_SYS_CFG1); return 0; }