/// runOnMachineFunction - We need to override this function so we can avoid
/// the call to EmitFunctionHeader(), which the MCPureStreamer can't handle.
bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
  const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
  if (STM.dumpCode()) {
    MF.dump();
  }
  SetupMachineFunction(MF);
  if (STM.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
    EmitProgramInfo(MF);
  }
  OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
  EmitFunctionBody();
  return false;
}
Beispiel #2
0
int XTCFrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) 
const {
    const MachineFrameInfo *MFI = MF.getFrameInfo();
  
    const XTCFunctionInfo *XTCFI = MF.getInfo<XTCFunctionInfo>();
    if (XTCFI->hasReplacement(FI))
        FI = XTCFI->getReplacement(FI);
#if 0
      DEBUG(dbgs()<<"Get Frame index offset\n");
      DEBUG(dbgs()<<"Fixed: "<<MFI->getNumFixedObjects()<<"\n");
      DEBUG(dbgs()<<"This: "<<FI<<"\n");
      DEBUG(dbgs()<<"Num: "<<MFI->getNumObjects()<<"\n");
      MF.dump();
#endif
      return TargetFrameLowering::getFrameIndexOffset(MF,FI);
}
Beispiel #3
0
/// We need to override this function so we can avoid
/// the call to EmitFunctionHeader(), which the MCPureStreamer can't handle.
bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
  const AMDGPUSubtarget &STM = TM.getSubtarget<AMDGPUSubtarget>();
  if (STM.dumpCode()) {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
    MF.dump();
#endif
  }
  SetupMachineFunction(MF);
  if (OutStreamer.hasRawTextSupport()) {
    OutStreamer.EmitRawText("@" + MF.getName() + ":");
  }
  OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
  if (STM.device()->getGeneration() > AMDGPUDeviceInfo::HD6XXX) {
    EmitProgramInfo(MF);
  }
  EmitFunctionBody();
  return false;
}
Beispiel #4
0
bool PPCBranchCoalescing::runOnMachineFunction(MachineFunction &MF) {

  if (skipFunction(MF.getFunction()) || MF.empty())
    return false;

  bool didSomething = false;

  DEBUG(dbgs() << "******** Branch Coalescing ********\n");
  initialize(MF);

  DEBUG(dbgs() << "Function: "; MF.dump(); dbgs() << "\n");

  CoalescingCandidateInfo Cand1, Cand2;
  // Walk over blocks and find candidates to merge
  // Continue trying to merge with the first candidate found, as long as merging
  // is successfull.
  for (MachineBasicBlock &MBB : MF) {
    bool MergedCandidates = false;
    do {
      MergedCandidates = false;
      Cand1.clear();
      Cand2.clear();

      Cand1.BranchBlock = &MBB;

      // If unable to coalesce the branch, then continue to next block
      if (!canCoalesceBranch(Cand1))
        break;

      Cand2.BranchBlock = Cand1.BranchTargetBlock;
      if (!canCoalesceBranch(Cand2))
        break;

      // Sanity check
      // The branch-taken block of the second candidate should post-dominate the
      // first candidate
      assert(MPDT->dominates(Cand2.BranchTargetBlock, Cand1.BranchBlock) &&
             "Branch-taken block should post-dominate first candidate");

      if (!identicalOperands(Cand1.Cond, Cand2.Cond)) {
        DEBUG(dbgs() << "Blocks " << Cand1.BranchBlock->getNumber() << " and "
                     << Cand2.BranchBlock->getNumber()
                     << " have different branches\n");
        break;
      }
      if (!canMerge(Cand2, Cand1)) {
        DEBUG(dbgs() << "Cannot merge blocks " << Cand1.BranchBlock->getNumber()
                     << " and " << Cand2.BranchBlock->getNumber() << "\n");
        NumBlocksNotCoalesced++;
        continue;
      }
      DEBUG(dbgs() << "Merging blocks " << Cand1.BranchBlock->getNumber()
                   << " and " << Cand1.BranchTargetBlock->getNumber() << "\n");
      MergedCandidates = mergeCandidates(Cand2, Cand1);
      if (MergedCandidates)
        didSomething = true;

      DEBUG(dbgs() << "Function after merging: "; MF.dump(); dbgs() << "\n");
    } while (MergedCandidates);
  }

#ifndef NDEBUG
  // Verify MF is still valid after branch coalescing
  if (didSomething)
    MF.verify(nullptr, "Error in code produced by branch coalescing");
#endif // NDEBUG

  DEBUG(dbgs() << "Finished Branch Coalescing\n");
  return didSomething;
}
Beispiel #5
0
bool BitLevelInfo::runOnMachineFunction(MachineFunction &MF) {
  MRI = &MF.getRegInfo();

  VFInfo *VFI = MF.getInfo<VFInfo>();
  // No need to run the pass if bitwidth information not available anymore.
  if (!VFI->isBitWidthAnnotated())
    return false;

  // Annotate the bit width information to target flag.
  for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
       BI != BE; ++BI)
    for (MachineBasicBlock::iterator I = BI->begin(), E =  BI->end();
         I != E; ++I) {
      MachineInstr &Instr = *I;
      bool isShifts = false;
      switch (Instr.getOpcode()) {
      default: break;
      case VTM::IMPLICIT_DEF:
        continue;
      case VTM::VOpRet: {
        // Setup the bit width for predicate operand.
        MachineOperand &Op = Instr.getOperand(0);
        VInstrInfo::setBitWidth(Op, 1);
        continue;
      }
      case VTM::VOpToState:
      case VTM::VOpToStateb: {
        // Setup the bit width for predicate operand.
        MachineOperand &Op = Instr.getOperand(0);
        if (Op.isImm()) {
          assert(Op.getImm() && "Unexpected 'never' in unconditional branch!");
          Op.ChangeToRegister(0, false);
          VInstrInfo::setBitWidth(Op, 1);
        }

        MachineOperand &Pred = Instr.getOperand(2);
        if (Pred.isImm()) {
          assert(Pred.getImm() && "Unexpected 'never' in unconditional branch!");
          Pred.ChangeToRegister(0, false);
          VInstrInfo::setBitWidth(Op, 1);
        }
        continue;
      }
      case VTM::COPY:     case VTM::PHI:
        continue;
      case VTM::VOpSRA: case VTM::VOpSRA_c:
      case VTM::VOpSRL: case VTM::VOpSRL_c:
      case VTM::VOpSHL: case VTM::VOpSHL_c:
        isShifts = true;
        break;
      }

      BitWidthAnnotator Annotator(Instr);

      if (isShifts) {
        // Fix the RHS operand width.
        Annotator.setBitWidth(Log2_32_Ceil(Annotator.getBitWidth(1)), 2);
        Annotator.updateBitWidth();
      }

      for (unsigned i = 0, e = Instr.getNumOperands() - 2; i < e; ++i) {
        MachineOperand &MO = Instr.getOperand(i);
        if (!MO.isReg() && !MO.isImm() && !MO.isSymbol()) continue;

        // Do not disturb the original target flags.
        if (MO.isSymbol() && MO.getTargetFlags() != 0) continue;

        unsigned BitWidth = Annotator.getBitWidthOrZero(i);
        if (BitWidth == 0) {
          // Already have bitwidth information.
          if (MO.getTargetFlags()) continue;

          assert(Instr.getOpcode() == VTM::VOpInternalCall && MO.isImm()
                 && "Bitwidth info not available!");
          BitWidth = 64;
        }

        bool Changed = updateBitWidth(MO, BitWidth);
        if (MO.isReg() && MO.isDef() && Changed)
          propagateBitWidth(MO);
      }

      Annotator.changeToDefaultPred();
    }

  DEBUG(dbgs() << "---------- After bit width annotation.\n");
  DEBUG(MF.dump());

  // Tell the MachineFunctionInfo that we had changed all annotators to default
  // predicate operand.
  VFI->removeBitWidthAnnotators();
  return false;
}