void SMDiagnostic::print(const char *ProgName, raw_ostream &S, bool ShowColors) const { // Display colors only if OS supports colors. ShowColors &= S.has_colors(); if (ShowColors) S.changeColor(raw_ostream::SAVEDCOLOR, true); if (ProgName && ProgName[0]) S << ProgName << ": "; if (!Filename.empty()) { if (Filename == "-") S << "<stdin>"; else S << Filename; if (LineNo != -1) { S << ':' << LineNo; if (ColumnNo != -1) S << ':' << (ColumnNo+1); } S << ": "; } switch (Kind) { case SourceMgr::DK_Error: if (ShowColors) S.changeColor(raw_ostream::RED, true); S << "error: "; break; case SourceMgr::DK_Warning: if (ShowColors) S.changeColor(raw_ostream::MAGENTA, true); S << "warning: "; break; case SourceMgr::DK_Note: if (ShowColors) S.changeColor(raw_ostream::BLACK, true); S << "note: "; break; } if (ShowColors) { S.resetColor(); S.changeColor(raw_ostream::SAVEDCOLOR, true); } S << Message << '\n'; if (ShowColors) S.resetColor(); if (LineNo == -1 || ColumnNo == -1) return; // FIXME: If there are multibyte or multi-column characters in the source, all // our ranges will be wrong. To do this properly, we'll need a byte-to-column // map like Clang's TextDiagnostic. For now, we'll just handle tabs by // expanding them later, and bail out rather than show incorrect ranges and // misaligned fixits for any other odd characters. if (std::find_if(LineContents.begin(), LineContents.end(), isNonASCII) != LineContents.end()) { printSourceLine(S, LineContents); return; } size_t NumColumns = LineContents.size(); // Build the line with the caret and ranges. std::string CaretLine(NumColumns+1, ' '); // Expand any ranges. for (unsigned r = 0, e = Ranges.size(); r != e; ++r) { std::pair<unsigned, unsigned> R = Ranges[r]; std::fill(&CaretLine[R.first], &CaretLine[std::min((size_t)R.second, CaretLine.size())], '~'); } // Add any fix-its. // FIXME: Find the beginning of the line properly for multibyte characters. std::string FixItInsertionLine; buildFixItLine(CaretLine, FixItInsertionLine, FixIts, makeArrayRef(Loc.getPointer() - ColumnNo, LineContents.size())); // Finally, plop on the caret. if (unsigned(ColumnNo) <= NumColumns) CaretLine[ColumnNo] = '^'; else CaretLine[NumColumns] = '^'; // ... and remove trailing whitespace so the output doesn't wrap for it. We // know that the line isn't completely empty because it has the caret in it at // least. CaretLine.erase(CaretLine.find_last_not_of(' ')+1); printSourceLine(S, LineContents); if (ShowColors) S.changeColor(raw_ostream::GREEN, true); // Print out the caret line, matching tabs in the source line. for (unsigned i = 0, e = CaretLine.size(), OutCol = 0; i != e; ++i) { if (i >= LineContents.size() || LineContents[i] != '\t') { S << CaretLine[i]; ++OutCol; continue; } // Okay, we have a tab. Insert the appropriate number of characters. do { S << CaretLine[i]; ++OutCol; } while ((OutCol % TabStop) != 0); } S << '\n'; if (ShowColors) S.resetColor(); // Print out the replacement line, matching tabs in the source line. if (FixItInsertionLine.empty()) return; for (size_t i = 0, e = FixItInsertionLine.size(), OutCol = 0; i != e; ++i) { if (i >= LineContents.size() || LineContents[i] != '\t') { S << FixItInsertionLine[i]; ++OutCol; continue; } // Okay, we have a tab. Insert the appropriate number of characters. do { S << FixItInsertionLine[i]; // FIXME: This is trying not to break up replacements, but then to re-sync // with the tabs between replacements. This will fail, though, if two // fix-it replacements are exactly adjacent, or if a fix-it contains a // space. Really we should be precomputing column widths, which we'll // need anyway for multibyte chars. if (FixItInsertionLine[i] != ' ') ++i; ++OutCol; } while (((OutCol % TabStop) != 0) && i != e); } S << '\n'; }
void CheckOrImmMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "CheckOrImm " << Value << '\n'; }
void EmitStringIntegerMatcher:: printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "EmitStringInteger " << Val << " VT=" << getEnumName(VT) << '\n'; }
void CheckChildIntegerMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "CheckChildInteger " << ChildNo << " " << Value << '\n'; }
void CheckValueTypeMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "CheckValueType MVT::" << TypeName << '\n'; }
void CheckPatternPredicateMatcher:: printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "CheckPatternPredicate " << Predicate << '\n'; }
void CheckOpcodeMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "CheckOpcode " << Opcode.getEnumName() << '\n'; }
void EmitKey(raw_ostream &Out, key_type_ref K, offset_type N) { Out.write(K.data(), N); }
void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map<std::vector<Record*>, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, raw_ostream &OS) { int MinOperands = 0; if (!Inst.Operands.empty()) // Each logical operand can be multiple MI operands. MinOperands = Inst.Operands.back().MIOperandNo + Inst.Operands.back().MINumOperands; OS << " { "; OS << Num << ",\t" << MinOperands << ",\t" << Inst.Operands.NumDefs << ",\t" << SchedModels.getSchedClassIdx(Inst) << ",\t" << Inst.TheDef->getValueAsInt("Size") << ",\t0"; // Emit all of the target indepedent flags... if (Inst.isPseudo) OS << "|(1<<MCID::Pseudo)"; if (Inst.isReturn) OS << "|(1<<MCID::Return)"; if (Inst.isBranch) OS << "|(1<<MCID::Branch)"; if (Inst.isIndirectBranch) OS << "|(1<<MCID::IndirectBranch)"; if (Inst.isCompare) OS << "|(1<<MCID::Compare)"; if (Inst.isMoveImm) OS << "|(1<<MCID::MoveImm)"; if (Inst.isBitcast) OS << "|(1<<MCID::Bitcast)"; if (Inst.isSelect) OS << "|(1<<MCID::Select)"; if (Inst.isBarrier) OS << "|(1<<MCID::Barrier)"; if (Inst.hasDelaySlot) OS << "|(1<<MCID::DelaySlot)"; if (Inst.isCall) OS << "|(1<<MCID::Call)"; if (Inst.canFoldAsLoad) OS << "|(1<<MCID::FoldableAsLoad)"; if (Inst.mayLoad) OS << "|(1<<MCID::MayLoad)"; if (Inst.mayStore) OS << "|(1<<MCID::MayStore)"; if (Inst.isPredicable) OS << "|(1<<MCID::Predicable)"; if (Inst.isConvertibleToThreeAddress) OS << "|(1<<MCID::ConvertibleTo3Addr)"; if (Inst.isCommutable) OS << "|(1<<MCID::Commutable)"; if (Inst.isTerminator) OS << "|(1<<MCID::Terminator)"; if (Inst.isReMaterializable) OS << "|(1<<MCID::Rematerializable)"; if (Inst.isNotDuplicable) OS << "|(1<<MCID::NotDuplicable)"; if (Inst.Operands.hasOptionalDef) OS << "|(1<<MCID::HasOptionalDef)"; if (Inst.usesCustomInserter) OS << "|(1<<MCID::UsesCustomInserter)"; if (Inst.hasPostISelHook) OS << "|(1<<MCID::HasPostISelHook)"; if (Inst.Operands.isVariadic)OS << "|(1<<MCID::Variadic)"; if (Inst.hasSideEffects) OS << "|(1<<MCID::UnmodeledSideEffects)"; if (Inst.isAsCheapAsAMove) OS << "|(1<<MCID::CheapAsAMove)"; if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)"; if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)"; // Emit all of the target-specific flags... BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags"); if (!TSF) PrintFatalError("no TSFlags?"); uint64_t Value = 0; for (unsigned i = 0, e = TSF->getNumBits(); i != e; ++i) { if (BitInit *Bit = dyn_cast<BitInit>(TSF->getBit(i))) Value |= uint64_t(Bit->getValue()) << i; else PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName()); } OS << ", 0x"; OS.write_hex(Value); OS << "ULL, "; // Emit the implicit uses and defs lists... std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses"); if (UseList.empty()) OS << "NULL, "; else OS << "ImplicitList" << EmittedLists[UseList] << ", "; std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs"); if (DefList.empty()) OS << "NULL, "; else OS << "ImplicitList" << EmittedLists[DefList] << ", "; // Emit the operand info. std::vector<std::string> OperandInfo = GetOperandInfo(Inst); if (OperandInfo.empty()) OS << "0"; else OS << "OperandInfo" << OpInfo.find(OperandInfo)->second; OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; }
void DisassemblerTables::emitInstructionInfo(raw_ostream &o, unsigned &i) const { unsigned NumInstructions = InstructionSpecifiers.size(); o << "static const struct OperandSpecifier x86OperandSets[][" << X86_MAX_OPERANDS << "] = {\n"; typedef std::vector<std::pair<const char *, const char *> > OperandListTy; std::map<OperandListTy, unsigned> OperandSets; unsigned OperandSetNum = 0; for (unsigned Index = 0; Index < NumInstructions; ++Index) { OperandListTy OperandList; for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; ++OperandIndex) { const char *Encoding = stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index] .operands[OperandIndex].encoding); const char *Type = stringForOperandType((OperandType)InstructionSpecifiers[Index] .operands[OperandIndex].type); OperandList.push_back(std::make_pair(Encoding, Type)); } unsigned &N = OperandSets[OperandList]; if (N != 0) continue; N = ++OperandSetNum; o << " { /* " << (OperandSetNum - 1) << " */\n"; for (unsigned i = 0, e = OperandList.size(); i != e; ++i) { o << " { " << OperandList[i].first << ", " << OperandList[i].second << " },\n"; } o << " },\n"; } o << "};" << "\n\n"; o.indent(i * 2) << "static const struct InstructionSpecifier "; o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n"; i++; for (unsigned index = 0; index < NumInstructions; ++index) { o.indent(i * 2) << "{ /* " << index << " */" << "\n"; i++; OperandListTy OperandList; for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS; ++OperandIndex) { const char *Encoding = stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index] .operands[OperandIndex].encoding); const char *Type = stringForOperandType((OperandType)InstructionSpecifiers[index] .operands[OperandIndex].type); OperandList.push_back(std::make_pair(Encoding, Type)); } o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n"; o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */"; o << "\n"; i--; o.indent(i * 2) << "}"; if (index + 1 < NumInstructions) o << ","; o << "\n"; } i--; o.indent(i * 2) << "};" << "\n"; }
void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const { const unsigned int tableSize = 16384; o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR "[" << tableSize << "] = {\n"; i++; for (unsigned index = 0; index < tableSize; ++index) { o.indent(i * 2); if (index & ATTR_EVEX) { o << "IC_EVEX"; if (index & ATTR_EVEXL2) o << "_L2"; else if (index & ATTR_EVEXL) o << "_L"; if (index & ATTR_REXW) o << "_W"; if (index & ATTR_OPSIZE) o << "_OPSIZE"; else if (index & ATTR_XD) o << "_XD"; else if (index & ATTR_XS) o << "_XS"; if (index & ATTR_EVEXKZ) o << "_KZ"; else if (index & ATTR_EVEXK) o << "_K"; if (index & ATTR_EVEXB) o << "_B"; } else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) o << "IC_VEX_L_W_OPSIZE"; else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD)) o << "IC_VEX_L_W_XD"; else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS)) o << "IC_VEX_L_W_XS"; else if ((index & ATTR_VEXL) && (index & ATTR_REXW)) o << "IC_VEX_L_W"; else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE)) o << "IC_VEX_L_OPSIZE"; else if ((index & ATTR_VEXL) && (index & ATTR_XD)) o << "IC_VEX_L_XD"; else if ((index & ATTR_VEXL) && (index & ATTR_XS)) o << "IC_VEX_L_XS"; else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) o << "IC_VEX_W_OPSIZE"; else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD)) o << "IC_VEX_W_XD"; else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS)) o << "IC_VEX_W_XS"; else if (index & ATTR_VEXL) o << "IC_VEX_L"; else if ((index & ATTR_VEX) && (index & ATTR_REXW)) o << "IC_VEX_W"; else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE)) o << "IC_VEX_OPSIZE"; else if ((index & ATTR_VEX) && (index & ATTR_XD)) o << "IC_VEX_XD"; else if ((index & ATTR_VEX) && (index & ATTR_XS)) o << "IC_VEX_XS"; else if (index & ATTR_VEX) o << "IC_VEX"; else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS)) o << "IC_64BIT_REXW_XS"; else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD)) o << "IC_64BIT_REXW_XD"; else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_OPSIZE)) o << "IC_64BIT_REXW_OPSIZE"; else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE)) o << "IC_64BIT_XD_OPSIZE"; else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE)) o << "IC_64BIT_XS_OPSIZE"; else if ((index & ATTR_64BIT) && (index & ATTR_XS)) o << "IC_64BIT_XS"; else if ((index & ATTR_64BIT) && (index & ATTR_XD)) o << "IC_64BIT_XD"; else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE)) o << "IC_64BIT_OPSIZE"; else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE)) o << "IC_64BIT_ADSIZE"; else if ((index & ATTR_64BIT) && (index & ATTR_REXW)) o << "IC_64BIT_REXW"; else if ((index & ATTR_64BIT)) o << "IC_64BIT"; else if ((index & ATTR_XS) && (index & ATTR_OPSIZE)) o << "IC_XS_OPSIZE"; else if ((index & ATTR_XD) && (index & ATTR_OPSIZE)) o << "IC_XD_OPSIZE"; else if (index & ATTR_XS) o << "IC_XS"; else if (index & ATTR_XD) o << "IC_XD"; else if (index & ATTR_OPSIZE) o << "IC_OPSIZE"; else if (index & ATTR_ADSIZE) o << "IC_ADSIZE"; else o << "IC"; if (index < tableSize - 1) o << ","; else o << " "; o << " /* " << index << " */"; o << "\n"; } i--; o.indent(i * 2) << "};" << "\n"; }
void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2, unsigned &i1, unsigned &i2, unsigned &ModRMTableNum, ModRMDecision &decision) const { static uint32_t sTableNumber = 0; static uint32_t sEntryNumber = 1; ModRMDecisionType dt = getDecisionType(decision); if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0) { o2.indent(i2) << "{ /* ModRMDecision */" << "\n"; i2++; o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; o2.indent(i2) << 0 << " /* EmptyTable */\n"; i2--; o2.indent(i2) << "}"; return; } std::vector<unsigned> ModRMDecision; switch (dt) { default: llvm_unreachable("Unknown decision type"); case MODRM_ONEENTRY: ModRMDecision.push_back(decision.instructionIDs[0]); break; case MODRM_SPLITRM: ModRMDecision.push_back(decision.instructionIDs[0x00]); ModRMDecision.push_back(decision.instructionIDs[0xc0]); break; case MODRM_SPLITREG: for (unsigned index = 0; index < 64; index += 8) ModRMDecision.push_back(decision.instructionIDs[index]); for (unsigned index = 0xc0; index < 256; index += 8) ModRMDecision.push_back(decision.instructionIDs[index]); break; case MODRM_SPLITMISC: for (unsigned index = 0; index < 64; index += 8) ModRMDecision.push_back(decision.instructionIDs[index]); for (unsigned index = 0xc0; index < 256; ++index) ModRMDecision.push_back(decision.instructionIDs[index]); break; case MODRM_FULL: for (unsigned index = 0; index < 256; ++index) ModRMDecision.push_back(decision.instructionIDs[index]); break; } unsigned &EntryNumber = ModRMTable[ModRMDecision]; if (EntryNumber == 0) { EntryNumber = ModRMTableNum; ModRMTableNum += ModRMDecision.size(); o1 << "/* Table" << EntryNumber << " */\n"; i1++; for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(), E = ModRMDecision.end(); I != E; ++I) { o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* " << InstructionSpecifiers[*I].name << " */\n"; } i1--; } o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n"; i2++; o2.indent(i2) << stringForDecisionType(dt) << "," << "\n"; o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n"; i2--; o2.indent(i2) << "}"; switch (dt) { default: llvm_unreachable("Unknown decision type"); case MODRM_ONEENTRY: sEntryNumber += 1; break; case MODRM_SPLITRM: sEntryNumber += 2; break; case MODRM_SPLITREG: sEntryNumber += 16; break; case MODRM_SPLITMISC: sEntryNumber += 8 + 64; break; case MODRM_FULL: sEntryNumber += 256; break; } // We assume that the index can fit into uint16_t. assert(sEntryNumber < 65536U && "Index into ModRMDecision is too large for uint16_t!"); ++sTableNumber; }
static int printICE(int Res, const char **Argv, raw_ostream &Err, bool insidebugreport, int argc, const char **argv, const sys::Path* orig_err) { Err << "Program arguments:"; while (*Argv) { Err << " " << Argv[0]; Argv++; } Err << "\n"; Err.changeColor(raw_ostream::RED, true); Err << "\nInternal compiler error: "; #ifdef LLVM_ON_UNIX Err << strsignal(Res); #else Err << " killed by signal " << Res; #endif Err << "!\n"; Err.resetColor(); Err.changeColor(raw_ostream::SAVEDCOLOR, true); if (insidebugreport) return 2; std::string prefix, prepath, tmperr, tarpath; prefix = getTmpDir(); if (prefix.empty()) { Err << "Cannot open locate location to store temporary files\n"; return 117; } tmperr = prefix + "/bugreport-preprocessed"; prepath = prefix + "/bugreport-tmperr"; tarpath = prefix + "/bugreport.tar"; sys::Path Tmp(prepath); sys::Path TmpErr(tmperr); sys::Path TmpOut(tarpath); std::string ErrMsg; ErrMsg.clear(); if (Tmp.createTemporaryFileOnDisk(true, &ErrMsg) || TmpErr.createTemporaryFileOnDisk(true, &ErrMsg) || TmpOut.createTemporaryFileOnDisk(true, &ErrMsg)) { Err << "Unable to create temporary file for bugreport: " << ErrMsg << "\n\n"; Err << "Please submit a bugreport at http://bugs.clamav.net\n" ; Err << "Please include the full sourcecode that caused this internal compiler error and the full error message!\n"; } else { ErrMsg.clear(); raw_fd_ostream TmpErrF(TmpErr.c_str(), ErrMsg); // Create version info for bugreport CompileFile(argc, argv, &Tmp, &TmpErr, TmpErrF, true, true); // Create preprocessed file for bugreport CompileFile(argc, argv, &Tmp, &TmpErr, TmpErrF, true); TmpErrF.close(); int fd = open(TmpOut.c_str(), O_WRONLY); if (fd < 0) { Err << "Cannot open file " << TmpOut.str() << ": " << strerror(errno) << "\n"; } else { chdir(orig_err->getDirname().str().c_str()); tar_addfile(fd, orig_err->getLast().str().c_str()); chdir(Tmp.getDirname().str().c_str()); tar_addfile(fd, Tmp.getLast().str().c_str()); chdir(TmpErr.getDirname().str().c_str()); tar_addfile(fd, TmpErr.getLast().str().c_str()); close(fd); } Tmp.eraseFromDisk(); TmpErr.eraseFromDisk(); Err << "Please submit a bugreport at http://bugs.clamav.net\n" ; Err << "Please compress and attach this file to the bugreport: " << TmpOut.str() << "\n"; } Err.resetColor(); return 42; }
unsigned DeclContext::printContext(raw_ostream &OS, const unsigned indent, const bool onlyAPartialLine) const { unsigned Depth = 0; if (!onlyAPartialLine) if (auto *P = getParent()) Depth = P->printContext(OS, indent); const char *Kind; switch (getContextKind()) { case DeclContextKind::Module: Kind = "Module"; break; case DeclContextKind::FileUnit: Kind = "FileUnit"; break; case DeclContextKind::SerializedLocal: Kind = "Serialized Local"; break; case DeclContextKind::AbstractClosureExpr: Kind = "AbstractClosureExpr"; break; case DeclContextKind::GenericTypeDecl: switch (cast<GenericTypeDecl>(this)->getKind()) { #define DECL(ID, PARENT) \ case DeclKind::ID: Kind = #ID "Decl"; break; #include "swift/AST/DeclNodes.def" } break; case DeclContextKind::ExtensionDecl: Kind = "ExtensionDecl"; break; case DeclContextKind::TopLevelCodeDecl: Kind = "TopLevelCodeDecl"; break; case DeclContextKind::Initializer: Kind = "Initializer"; break; case DeclContextKind::AbstractFunctionDecl: Kind = "AbstractFunctionDecl"; break; case DeclContextKind::SubscriptDecl: Kind = "SubscriptDecl"; break; case DeclContextKind::EnumElementDecl: Kind = "EnumElementDecl"; break; } OS.indent(Depth*2 + indent) << (void*)this << " " << Kind; switch (getContextKind()) { case DeclContextKind::Module: OS << " name=" << cast<ModuleDecl>(this)->getName(); break; case DeclContextKind::FileUnit: switch (cast<FileUnit>(this)->getKind()) { case FileUnitKind::Builtin: OS << " Builtin"; break; case FileUnitKind::Source: OS << " file=\"" << cast<SourceFile>(this)->getFilename() << "\""; break; case FileUnitKind::SerializedAST: case FileUnitKind::ClangModule: case FileUnitKind::DWARFModule: OS << " file=\"" << cast<LoadedFile>(this)->getFilename() << "\""; break; } break; case DeclContextKind::AbstractClosureExpr: OS << " line=" << getLineNumber(cast<AbstractClosureExpr>(this)); OS << " : " << cast<AbstractClosureExpr>(this)->getType(); break; case DeclContextKind::GenericTypeDecl: OS << " name=" << cast<GenericTypeDecl>(this)->getName(); break; case DeclContextKind::ExtensionDecl: OS << " line=" << getLineNumber(cast<ExtensionDecl>(this)); OS << " base=" << cast<ExtensionDecl>(this)->getExtendedType(); break; case DeclContextKind::TopLevelCodeDecl: OS << " line=" << getLineNumber(cast<TopLevelCodeDecl>(this)); break; case DeclContextKind::AbstractFunctionDecl: { auto *AFD = cast<AbstractFunctionDecl>(this); OS << " name=" << AFD->getFullName(); if (AFD->hasInterfaceType()) OS << " : " << AFD->getInterfaceType(); else OS << " : (no type set)"; break; } case DeclContextKind::SubscriptDecl: { auto *SD = cast<SubscriptDecl>(this); OS << " name=" << SD->getBaseName(); if (SD->hasInterfaceType()) OS << " : " << SD->getInterfaceType(); else OS << " : (no type set)"; break; } case DeclContextKind::EnumElementDecl: { auto *EED = cast<EnumElementDecl>(this); OS << " name=" << EED->getBaseName(); if (EED->hasInterfaceType()) OS << " : " << EED->getInterfaceType(); else OS << " : (no type set)"; break; } case DeclContextKind::Initializer: switch (cast<Initializer>(this)->getInitializerKind()) { case InitializerKind::PatternBinding: { auto init = cast<PatternBindingInitializer>(this); OS << " PatternBinding 0x" << (void*) init->getBinding() << " #" << init->getBindingIndex(); break; } case InitializerKind::DefaultArgument: { auto init = cast<DefaultArgumentInitializer>(this); OS << " DefaultArgument index=" << init->getIndex(); break; } } break; case DeclContextKind::SerializedLocal: { auto local = cast<SerializedLocalDeclContext>(this); switch (local->getLocalDeclContextKind()) { case LocalDeclContextKind::AbstractClosure: { auto serializedClosure = cast<SerializedAbstractClosureExpr>(local); OS << " closure : " << serializedClosure->getType(); break; } case LocalDeclContextKind::DefaultArgumentInitializer: { auto init = cast<SerializedDefaultArgumentInitializer>(local); OS << "DefaultArgument index=" << init->getIndex(); break; } case LocalDeclContextKind::PatternBindingInitializer: { auto init = cast<SerializedPatternBindingInitializer>(local); OS << " PatternBinding 0x" << (void*) init->getBinding() << " #" << init->getBindingIndex(); break; } case LocalDeclContextKind::TopLevelCodeDecl: OS << " TopLevelCode"; break; } } } if (!onlyAPartialLine) OS << "\n"; return Depth + 1; }
void CheckSameMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "CheckSame " << MatchNumber << '\n'; }
/// Mangle this entity into the given stream. void LinkEntity::mangle(raw_ostream &buffer) const { std::string Result = mangleAsString(); buffer.write(Result.data(), Result.size()); }
void CheckChildSameMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "CheckChild" << ChildNo << "Same\n"; }
// // runTargetDesc - Output the target register and register file descriptions. // void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, CodeGenRegBank &RegBank){ emitSourceFileHeader("Target Register and Register Classes Information", OS); OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; OS << "#undef GET_REGINFO_TARGET_DESC\n"; OS << "namespace llvm {\n\n"; // Get access to MCRegisterClass data. OS << "extern const MCRegisterClass " << Target.getName() << "MCRegisterClasses[];\n"; // Start out by emitting each of the register classes. ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses(); ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices(); // Collect all registers belonging to any allocatable class. std::set<Record*> AllocatableRegs; // Collect allocatable registers. for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { const CodeGenRegisterClass &RC = *RegisterClasses[rc]; ArrayRef<Record*> Order = RC.getOrder(); if (RC.Allocatable) AllocatableRegs.insert(Order.begin(), Order.end()); } // Build a shared array of value types. SequenceToOffsetTable<SmallVector<MVT::SimpleValueType, 4> > VTSeqs; for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) VTSeqs.add(RegisterClasses[rc]->VTs); VTSeqs.layout(); OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; VTSeqs.emit(OS, printSimpleValueType, "MVT::Other"); OS << "};\n"; // Emit SubRegIndex names, skipping 0. OS << "\nstatic const char *const SubRegIndexNameTable[] = { \""; for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { OS << SubRegIndices[i]->getName(); if (i + 1 != e) OS << "\", \""; } OS << "\" };\n\n"; // Emit SubRegIndex lane masks, including 0. OS << "\nstatic const unsigned SubRegIndexLaneMaskTable[] = {\n ~0u,\n"; for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { OS << format(" 0x%08x, // ", SubRegIndices[i]->LaneMask) << SubRegIndices[i]->getName() << '\n'; } OS << " };\n\n"; OS << "\n"; // Now that all of the structs have been emitted, emit the instances. if (!RegisterClasses.empty()) { OS << "\nstatic const TargetRegisterClass *const " << "NullRegClasses[] = { NULL };\n\n"; // Emit register class bit mask tables. The first bit mask emitted for a // register class, RC, is the set of sub-classes, including RC itself. // // If RC has super-registers, also create a list of subreg indices and bit // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, // SuperRC, that satisfies: // // For all SuperReg in SuperRC: SuperReg:Idx in RC // // The 0-terminated list of subreg indices starts at: // // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... // // The corresponding bitmasks follow the sub-class mask in memory. Each // mask has RCMaskWords uint32_t entries. // // Every bit mask present in the list has at least one bit set. // Compress the sub-reg index lists. typedef std::vector<const CodeGenSubRegIndex*> IdxList; SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); SequenceToOffsetTable<IdxList, CodeGenSubRegIndex::Less> SuperRegIdxSeqs; BitVector MaskBV(RegisterClasses.size()); for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { const CodeGenRegisterClass &RC = *RegisterClasses[rc]; OS << "static const uint32_t " << RC.getName() << "SubClassMask[] = {\n "; printBitVectorAsHex(OS, RC.getSubClasses(), 32); // Emit super-reg class masks for any relevant SubRegIndices that can // project into RC. IdxList &SRIList = SuperRegIdxLists[rc]; for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { CodeGenSubRegIndex *Idx = SubRegIndices[sri]; MaskBV.reset(); RC.getSuperRegClasses(Idx, MaskBV); if (MaskBV.none()) continue; SRIList.push_back(Idx); OS << "\n "; printBitVectorAsHex(OS, MaskBV, 32); OS << "// " << Idx->getName(); } SuperRegIdxSeqs.add(SRIList); OS << "\n};\n\n"; } OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; SuperRegIdxSeqs.layout(); SuperRegIdxSeqs.emit(OS, printSubRegIndex); OS << "};\n\n"; // Emit NULL terminated super-class lists. for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { const CodeGenRegisterClass &RC = *RegisterClasses[rc]; ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses(); // Skip classes without supers. We can reuse NullRegClasses. if (Supers.empty()) continue; OS << "static const TargetRegisterClass *const " << RC.getName() << "Superclasses[] = {\n"; for (unsigned i = 0; i != Supers.size(); ++i) OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n"; OS << " NULL\n};\n\n"; } // Emit methods. for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { const CodeGenRegisterClass &RC = *RegisterClasses[i]; if (!RC.AltOrderSelect.empty()) { OS << "\nstatic inline unsigned " << RC.getName() << "AltOrderSelect(const MachineFunction &MF) {" << RC.AltOrderSelect << "}\n\n" << "static ArrayRef<MCPhysReg> " << RC.getName() << "GetRawAllocationOrder(const MachineFunction &MF) {\n"; for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) { ArrayRef<Record*> Elems = RC.getOrder(oi); if (!Elems.empty()) { OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; for (unsigned elem = 0; elem != Elems.size(); ++elem) OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); OS << " };\n"; } } OS << " const MCRegisterClass &MCR = " << Target.getName() << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" << " const ArrayRef<MCPhysReg> Order[] = {\n" << " makeArrayRef(MCR.begin(), MCR.getNumRegs()"; for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) if (RC.getOrder(oi).empty()) OS << "),\n ArrayRef<MCPhysReg>("; else OS << "),\n makeArrayRef(AltOrder" << oi; OS << ")\n };\n const unsigned Select = " << RC.getName() << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders() << ");\n return Order[Select];\n}\n"; } } // Now emit the actual value-initialized register class instances. OS << "namespace " << RegisterClasses[0]->Namespace << " { // Register class instances\n"; for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { const CodeGenRegisterClass &RC = *RegisterClasses[i]; OS << " extern const TargetRegisterClass " << RegisterClasses[i]->getName() << "RegClass = {\n " << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n " << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " << SuperRegIdxSeqs.get(SuperRegIdxLists[i]) << ",\n "; if (RC.getSuperClasses().empty()) OS << "NullRegClasses,\n "; else OS << RC.getName() << "Superclasses,\n "; if (RC.AltOrderSelect.empty()) OS << "0\n"; else OS << RC.getName() << "GetRawAllocationOrder\n"; OS << " };\n\n"; } OS << "}\n"; } OS << "\nnamespace {\n"; OS << " const TargetRegisterClass* const RegisterClasses[] = {\n"; for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) OS << " &" << RegisterClasses[i]->getQualifiedName() << "RegClass,\n"; OS << " };\n"; OS << "}\n"; // End of anonymous namespace... // Emit extra information about registers. const std::string &TargetName = Target.getName(); OS << "\nstatic const TargetRegisterInfoDesc " << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n"; OS << " { 0, 0 },\n"; const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters(); for (unsigned i = 0, e = Regs.size(); i != e; ++i) { const CodeGenRegister &Reg = *Regs[i]; OS << " { "; OS << Reg.CostPerUse << ", " << int(AllocatableRegs.count(Reg.TheDef)) << " },\n"; } OS << "};\n"; // End of register descriptors... std::string ClassName = Target.getName() + "GenRegisterInfo"; if (!SubRegIndices.empty()) emitComposeSubRegIndices(OS, RegBank, ClassName); // Emit getSubClassWithSubReg. if (!SubRegIndices.empty()) { OS << "const TargetRegisterClass *" << ClassName << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" << " const {\n"; // Use the smallest type that can hold a regclass ID with room for a // sentinel. if (RegisterClasses.size() < UINT8_MAX) OS << " static const uint8_t Table["; else if (RegisterClasses.size() < UINT16_MAX) OS << " static const uint16_t Table["; else PrintFatalError("Too many register classes."); OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n"; for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) { const CodeGenRegisterClass &RC = *RegisterClasses[rci]; OS << " {\t// " << RC.getName() << "\n"; for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) { CodeGenSubRegIndex *Idx = SubRegIndices[sri]; if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx)) OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName() << " -> " << SRC->getName() << "\n"; else OS << " 0,\t// " << Idx->getName() << "\n"; } OS << " },\n"; } OS << " };\n assert(RC && \"Missing regclass\");\n" << " if (!Idx) return RC;\n --Idx;\n" << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n" << " unsigned TV = Table[RC->getID()][Idx];\n" << " return TV ? getRegClass(TV - 1) : 0;\n}\n\n"; } EmitRegUnitPressure(OS, RegBank, ClassName); // Emit the constructor of the class... OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n"; OS << "extern const char " << TargetName << "RegStrings[];\n"; OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; OS << "extern const MCRegisterInfo::SubRegCoveredBits " << TargetName << "SubRegIdxRanges[];\n"; OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; EmitRegMappingTables(OS, Regs, true); OS << ClassName << "::\n" << ClassName << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n" << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" << " SubRegIndexNameTable, SubRegIndexLaneMaskTable, 0x"; OS.write_hex(RegBank.CoveringLanes); OS << ") {\n" << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size()+1 << ", RA, PC,\n " << TargetName << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" << " " << TargetName << "RegUnitRoots,\n" << " " << RegBank.getNumNativeRegUnits() << ",\n" << " " << TargetName << "RegDiffLists,\n" << " " << TargetName << "RegStrings,\n" << " " << TargetName << "SubRegIdxLists,\n" << " " << SubRegIndices.size() + 1 << ",\n" << " " << TargetName << "SubRegIdxRanges,\n" << " " << TargetName << "RegEncodingTable);\n\n"; EmitRegMapping(OS, Regs, true); OS << "}\n\n"; // Emit CalleeSavedRegs information. std::vector<Record*> CSRSets = Records.getAllDerivedDefinitions("CalleeSavedRegs"); for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) { Record *CSRSet = CSRSets[i]; const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); assert(Regs && "Cannot expand CalleeSavedRegs instance"); // Emit the *_SaveList list of callee-saved registers. OS << "static const MCPhysReg " << CSRSet->getName() << "_SaveList[] = { "; for (unsigned r = 0, re = Regs->size(); r != re; ++r) OS << getQualifiedName((*Regs)[r]) << ", "; OS << "0 };\n"; // Emit the *_RegMask bit mask of call-preserved registers. BitVector Covered = RegBank.computeCoveredRegisters(*Regs); // Check for an optional OtherPreserved set. // Add those registers to RegMask, but not to SaveList. if (DagInit *OPDag = dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { SetTheory::RecSet OPSet; RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); Covered |= RegBank.computeCoveredRegisters( ArrayRef<Record*>(OPSet.begin(), OPSet.end())); } OS << "static const uint32_t " << CSRSet->getName() << "_RegMask[] = { "; printBitVectorAsHex(OS, Covered, 32); OS << "};\n"; } OS << "\n\n"; OS << "} // End llvm namespace \n"; OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; }
void CheckPredicateMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "CheckPredicate " << getPredicate().getFnName() << '\n'; }
void RecordChildMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "RecordChild: " << ChildNo << '\n'; }
void CheckChildTypeMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "CheckChildType " << ChildNo << " " << getEnumName(Type) << '\n'; }
void RecordMemRefMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "RecordMemRef\n"; }
void CheckCondCodeMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "CheckCondCode ISD::" << CondCodeName << '\n'; }
void CaptureGlueInputMatcher::printImpl(raw_ostream &OS, unsigned indent) const{ OS.indent(indent) << "CaptureGlueInput\n"; }
void CheckComplexPatMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "CheckComplexPat " << Pattern.getSelectFunc() << '\n'; }
void MoveChildMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "MoveChild " << ChildNo << '\n'; }
void CheckFoldableChainNodeMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "CheckFoldableChainNode\n"; }
void MoveParentMatcher::printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "MoveParent\n"; }
void EmitConvertToTargetMatcher:: printImpl(raw_ostream &OS, unsigned indent) const { OS.indent(indent) << "EmitConvertToTarget " << Slot << '\n'; }
static int AsLexInput(SourceMgr &SrcMgr, MCAsmInfo &MAI, raw_ostream &OS) { AsmLexer Lexer(MAI); Lexer.setBuffer(SrcMgr.getMemoryBuffer(SrcMgr.getMainFileID())->getBuffer()); bool Error = false; while (Lexer.Lex().isNot(AsmToken::Eof)) { const AsmToken &Tok = Lexer.getTok(); switch (Tok.getKind()) { default: SrcMgr.PrintMessage(Lexer.getLoc(), SourceMgr::DK_Warning, "unknown token"); Error = true; break; case AsmToken::Error: Error = true; // error already printed. break; case AsmToken::Identifier: OS << "identifier: " << Lexer.getTok().getString(); break; case AsmToken::Integer: OS << "int: " << Lexer.getTok().getString(); break; case AsmToken::Real: OS << "real: " << Lexer.getTok().getString(); break; case AsmToken::String: OS << "string: " << Lexer.getTok().getString(); break; case AsmToken::Amp: OS << "Amp"; break; case AsmToken::AmpAmp: OS << "AmpAmp"; break; case AsmToken::At: OS << "At"; break; case AsmToken::Caret: OS << "Caret"; break; case AsmToken::Colon: OS << "Colon"; break; case AsmToken::Comma: OS << "Comma"; break; case AsmToken::Dollar: OS << "Dollar"; break; case AsmToken::Dot: OS << "Dot"; break; case AsmToken::EndOfStatement: OS << "EndOfStatement"; break; case AsmToken::Eof: OS << "Eof"; break; case AsmToken::Equal: OS << "Equal"; break; case AsmToken::EqualEqual: OS << "EqualEqual"; break; case AsmToken::Exclaim: OS << "Exclaim"; break; case AsmToken::ExclaimEqual: OS << "ExclaimEqual"; break; case AsmToken::Greater: OS << "Greater"; break; case AsmToken::GreaterEqual: OS << "GreaterEqual"; break; case AsmToken::GreaterGreater: OS << "GreaterGreater"; break; case AsmToken::Hash: OS << "Hash"; break; case AsmToken::LBrac: OS << "LBrac"; break; case AsmToken::LCurly: OS << "LCurly"; break; case AsmToken::LParen: OS << "LParen"; break; case AsmToken::Less: OS << "Less"; break; case AsmToken::LessEqual: OS << "LessEqual"; break; case AsmToken::LessGreater: OS << "LessGreater"; break; case AsmToken::LessLess: OS << "LessLess"; break; case AsmToken::Minus: OS << "Minus"; break; case AsmToken::Percent: OS << "Percent"; break; case AsmToken::Pipe: OS << "Pipe"; break; case AsmToken::PipePipe: OS << "PipePipe"; break; case AsmToken::Plus: OS << "Plus"; break; case AsmToken::RBrac: OS << "RBrac"; break; case AsmToken::RCurly: OS << "RCurly"; break; case AsmToken::RParen: OS << "RParen"; break; case AsmToken::Slash: OS << "Slash"; break; case AsmToken::Star: OS << "Star"; break; case AsmToken::Tilde: OS << "Tilde"; break; case AsmToken::PercentCall16: OS << "PercentCall16"; break; case AsmToken::PercentCall_Hi: OS << "PercentCall_Hi"; break; case AsmToken::PercentCall_Lo: OS << "PercentCall_Lo"; break; case AsmToken::PercentDtprel_Hi: OS << "PercentDtprel_Hi"; break; case AsmToken::PercentDtprel_Lo: OS << "PercentDtprel_Lo"; break; case AsmToken::PercentGot: OS << "PercentGot"; break; case AsmToken::PercentGot_Disp: OS << "PercentGot_Disp"; break; case AsmToken::PercentGot_Hi: OS << "PercentGot_Hi"; break; case AsmToken::PercentGot_Lo: OS << "PercentGot_Lo"; break; case AsmToken::PercentGot_Ofst: OS << "PercentGot_Ofst"; break; case AsmToken::PercentGot_Page: OS << "PercentGot_Page"; break; case AsmToken::PercentGottprel: OS << "PercentGottprel"; break; case AsmToken::PercentGp_Rel: OS << "PercentGp_Rel"; break; case AsmToken::PercentHi: OS << "PercentHi"; break; case AsmToken::PercentHigher: OS << "PercentHigher"; break; case AsmToken::PercentHighest: OS << "PercentHighest"; break; case AsmToken::PercentLo: OS << "PercentLo"; break; case AsmToken::PercentNeg: OS << "PercentNeg"; break; case AsmToken::PercentPcrel_Hi: OS << "PercentPcrel_Hi"; break; case AsmToken::PercentPcrel_Lo: OS << "PercentPcrel_Lo"; break; case AsmToken::PercentTlsgd: OS << "PercentTlsgd"; break; case AsmToken::PercentTlsldm: OS << "PercentTlsldm"; break; case AsmToken::PercentTprel_Hi: OS << "PercentTprel_Hi"; break; case AsmToken::PercentTprel_Lo: OS << "PercentTprel_Lo"; break; } // Print the token string. OS << " (\""; OS.write_escaped(Tok.getString()); OS << "\")\n"; } return Error; }