GitHub - dbancajas/dmr3d: This repo has the processor code for my paper DMR3D: Dynamic Memory Relocation for 3D Multicores published at DAC 2013. The DRAMSim2 code I used is located in another repo:https://github.com/dbancajas/DRAMSim2

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common		common
mem-hier		mem-hier
power		power
processor		processor
Makefile		Makefile
Makefile.bak		Makefile.bak
README		README
README_inegr_fix.txt		README_inegr_fix.txt
simics_3_port.sh		simics_3_port.sh

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This is my new project. ms2sim + dramsim2

This project combines ms2sim sparc simulator with the dram simulator from univ of maryland.
I will create a 3d-memory model based on DRAMSim2 as a baseline for this project.
Memory accesses of processors are then optimized using virtualization.


The initial commit of this project on beanstalkapp.com uses a fully functional simulator connected to DRAMSim2.
Dramsim has been extensively modified to be able to interface smoothly with main memory model of ms2sim.
I have added a transaction Id for every memory transaction in ms2sim.

Right now, the configuration is that of a uniprocessor + two-level cache. It will be extended soon for a 
CMP + caches + dram memory and then ultimately to using multiple memory controllers.

-Dean Ancajas

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This repo has the processor code for my paper DMR3D: Dynamic Memory Relocation for 3D Multicores published at DAC 2013. The DRAMSim2 code I used is located in another repo:https://github.com/dbancajas/DRAMSim2

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