- Xilinx ISE (tested with version 14.7)
gitmake(Linux only)
git clone https://github.com/cyrozap/Mimas-V2-UART-Demo.git
cd Mimas-V2-UART-Demo
git submodule update --init
source /opt/Xilinx/14.7/ISE_DS/settings64.sh
make bin
- Clone the repository with your favorite git client
git clone https://github.com/cyrozap/Mimas-V2-UART-Demo.git
- Using your git client, run a submodule update with init
cd Mimas-V2-UART-Demo && git submodule update --init
- Open the Xilinx ISE Project Navigator
- Create a new project (File -> New Project...)
- You can enter anything you want for the name, but the Location and Working Directory must be the same as the folder you just cloned the repository into
- The "Top-level source type" is "HDL"
- Family: Spartan6
- Device: XC6SLX9
- Package: CSG324
- Speed: -2
- Preferred Language: Verilog
- Add source files (Project -> Add Source...)
- Select
uart_demo.vandmimas_v2.ucf - Click "OK"
- Select
- Open the properties for the "Generate Programming File" process
- Under "General Options", enable "Create Binary Configuration File"
- Run the "Generate Programming File" process