/*
* This functions configures I2C and brings I2C out of reset.
* This function is called during I2C init function. This function
* also gets called if I2C encounetrs any errors. Clock calculation portion
* of this function has been taken from some other driver.
*/
static int i2c_davinci_reset(struct i2c_davinci_device *dev)
{
u16 psc;
u32 clk;
unsigned long flags;
spin_lock_irqsave( &i2c_spinlock, flags );
/* put I2C into reset */
dev->regs->icmdr &= ~DAVINCI_I2C_ICMDR_IRS_MASK;
/* NOTE: I2C Clock divider programming info
* As per I2C specs the following formulas provide prescalar and low/high divider values
*
* input clk --> PSC Div -----------> ICCL/H Div --> output clock
* module clk
*
* output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
*
* Thus,
* (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
*
* where if PSC == 0, d = 7,
* if PSC == 1, d = 6
* if PSC > 1 , d = 5
*/
psc = 2; /* To get 9MHz clock */
clk = ((i2c_davinci_inputClock/(psc + 1)) / (i2c_davinci_busFreq * 1000)) - 10;
dev->regs->icpsc = psc;
dev->regs->icclkh = (27 * clk) / 100; /* duty cycle should be 27% */
dev->regs->icclkl = (clk - dev->regs->icclkh);
DEB1("CLK = %d\n", clk);
DEB1("PSC = %d\n", dev->regs->icpsc);
DEB1("CLKL = %d\n", dev->regs->icclkl);
DEB1("CLKH = %d\n", dev->regs->icclkh);
/* Set Own Address: */
dev->regs->icoar = i2c_davinci_own_addr;
/* Enable interrupts */
dev->regs->icimr = I2C_DAVINCI_INTR_ALL;
/* Take the I2C module out of reset: */
dev->regs->icmdr |= DAVINCI_I2C_ICMDR_IRS_MASK;
spin_unlock_irqrestore( &i2c_spinlock, flags );
return 0;
}
/*
* Prepare controller for a transaction and call i2c_davinci_xfer_msg
*/
static int
i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
{
int count;
int ret = 0;
char retries = 5;
DEB1("msgs: %d", num);
if (num < 1 || num > MAX_MESSAGES)
return -EINVAL;
/* Check for valid parameters in messages */
for (count = 0; count < num; count++)
if (msgs[count].buf == NULL)
return -EINVAL;
if ((ret = i2c_davinci_wait_for_bb(1, adap)) < 0)
return ret;
for (count = 0; count < num; count++) {
DEB1("msg: %d, addr: 0x%04x, len: %d, flags: 0x%x",
count, msgs[count].addr, msgs[count].len,
msgs[count].flags);
do {
ret = i2c_davinci_xfer_msg(adap, &msgs[count],
(count == (num - 1)));
if (ret < 0) {
struct i2c_davinci_device *dev = i2c_get_adapdata(adap);
DEB1("i2c: retry %d - icstr = 0x%x",
retries, dev->regs->icstr);
mdelay (1);
retries--;
} else
break;
} while (retries);
DEB1("ret: %d", ret);
if (ret != msgs[count].len)
break;
}
if (ret >= 0 && num >= 1)
ret = num;
DEB1("ret: %d", ret);
return ret;
}
static int pca_init(struct i2c_algo_pca_data *adap)
{
static int freqs[] = {330,288,217,146,88,59,44,36};
int own, clock;
own = pca_own(adap);
clock = pca_clock(adap);
DEB1(KERN_INFO DRIVER ": own address is %#04x\n", own);
DEB1(KERN_INFO DRIVER ": clock freqeuncy is %dkHz\n", freqs[clock]);
pca_outw(adap, I2C_PCA_ADR, own << 1);
pca_set_con(adap, I2C_PCA_CON_ENSIO | clock);
udelay(500); /* 500 µs for oscilator to stabilise */
return 0;
}
/*
* Prepare controller for a transaction and call i2c_davinci_xfer_msg
*/
static int
i2c_davinci_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
{
int count;
int ret = 0;
DEB1("msgs: %d", num);
if (num < 1 || num > MAX_MESSAGES)
return -EINVAL;
/* Check for valid parameters in messages */
for (count = 0; count < num; count++)
if (msgs[count].buf == NULL)
return -EINVAL;
if ((ret = i2c_davinci_wait_for_bb(1)) < 0)
return ret;
for (count = 0; count < num; count++) {
DEB1("msg: %d, addr: 0x%04x, len: %d, flags: 0x%x",
count, msgs[count].addr, msgs[count].len,
msgs[count].flags);
ret =
i2c_davinci_xfer_msg(adap, &msgs[count],
(count == (num - 1)));
DEB1("ret: %d", ret);
if (ret != msgs[count].len)
break;
}
if (ret >= 0 && num > 1)
ret = num;
DEB1("ret xfer: %d", ret);
return ret;
}
static int __init i2c_davinci_init(void)
{
int status;
struct device *dev = NULL;
DEB0("%s %s", __TIME__, __DATE__);
DEB1("i2c_davinci_init()\n");
davinci_i2c_fix_ths7353_lockup( );
#if 0
if (i2c_davinci_busFreq > 200)
i2c_davinci_busFreq = 400; /*Fast mode */
else
i2c_davinci_busFreq = 100; /*Standard mode */
#endif
i2c_clock = clk_get (dev, "I2CCLK");
if (i2c_clock == NULL)
return -1;
clk_use (i2c_clock);
clk_enable (i2c_clock);
i2c_davinci_inputClock = clk_get_rate (i2c_clock);
DEB1 ("IP CLOCK = %ld\n", i2c_davinci_inputClock);
memset(&i2c_davinci_dev, 0, sizeof(i2c_davinci_dev));
i2c_davinci_dev.regs = (davinci_i2cregsovly)I2C_BASE;
status = (int)request_region(I2C_BASE, I2C_IOSIZE, MODULE_NAME);
if (!status) {
i2c_err("I2C is already in use\n");
return -ENODEV;
}
status = request_irq(IRQ_I2C, i2c_davinci_isr, 0, MODULE_NAME,
&i2c_davinci_dev);
if (status) {
i2c_err("failed to request I2C IRQ");
goto do_release_region;
}
i2c_set_adapdata(&i2c_davinci_adap, &i2c_davinci_dev);
status = i2c_add_adapter(&i2c_davinci_adap);
if (status) {
i2c_err("failed to add adapter");
goto do_free_irq;
return status;
}
i2c_davinci_reset(&i2c_davinci_dev);
if (driver_register(&davinci_i2c_driver) != 0)
printk(KERN_ERR "Driver register failed for davinci_i2c\n");
if (platform_device_register(&davinci_i2c_device) != 0) {
printk(KERN_ERR "Device register failed for i2c\n");
driver_unregister(&davinci_i2c_driver);
}
return 0;
do_free_irq:
free_irq(IRQ_I2C, &i2c_davinci_dev);
do_release_region:
release_region(I2C_BASE, I2C_IOSIZE);
return status;
}
/*
* Interrupt service routine. This gets called whenever an I2C interrupt
* occurs.
*/
static irqreturn_t
i2c_davinci_isr(int this_irq, void *dev_id, struct pt_regs *reg)
{
struct i2c_davinci_device *dev = dev_id;
u32 stat;
DEB1("i2c_davinci_isr()\n");
while ((stat = dev->regs->icivr) != 0) {
// printk( "\t%02x\n", stat );
switch (stat) {
case DAVINCI_I2C_ICIVR_INTCODE_AL:
dev->cmd_err |= DAVINCI_I2C_ICSTR_AL_MASK;
i2c_davinci_complete_cmd(dev);
break;
case DAVINCI_I2C_ICIVR_INTCODE_NACK:
dev->cmd_err |= DAVINCI_I2C_ICSTR_NACK_MASK;
i2c_davinci_complete_cmd(dev);
break;
case DAVINCI_I2C_ICIVR_INTCODE_RAR:
dev->regs->icstr |= DAVINCI_I2C_ICSTR_ARDY_MASK;
i2c_davinci_complete_cmd( dev );
break;
case DAVINCI_I2C_ICIVR_INTCODE_RDR:
if (dev->buf_len) {
*dev->buf++ = dev->regs->icdrr;
dev->buf_len--;
if (dev->buf_len) {
continue;
} else {
dev->regs->icimr &=
~DAVINCI_I2C_ICIMR_ICRRDY_MASK;
}
}
break;
case DAVINCI_I2C_ICIVR_INTCODE_TDR:
if (dev->buf_len) {
dev->regs->icdxr = *dev->buf++;
dev->buf_len--;
if (dev->buf_len)
continue;
else {
dev->regs->icimr &=
~DAVINCI_I2C_ICIMR_ICXRDY_MASK;
/* If no stop bit, then we are done ... */
if ( !(dev->regs->icmdr & DAVINCI_I2C_ICMDR_STP_MASK) ) {
i2c_davinci_complete_cmd( dev );
}
}
}
break;
case DAVINCI_I2C_ICIVR_INTCODE_SCD:
dev->regs->icstr |= DAVINCI_I2C_ICSTR_SCD_MASK;
i2c_davinci_complete_cmd(dev);
break;
case DAVINCI_I2C_ICIVR_INTCODE_AAS:
i2c_warn("Address as slave interrupt");
break;
default:
printk( "Unknown status 0x%04x\n", stat );
break;
} /* switch */
} /* while */
return IRQ_HANDLED;
}
/*
* Low level master read/write transaction. This function is called
* from i2c_davinci_xfer.
*/
static int
i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
{
struct i2c_davinci_device *dev = i2c_get_adapdata(adap);
u8 zero_byte = 0;
u32 flag = 0, stat = 0;
unsigned long flags;
int r;
int cnt = 2000;
/* Introduce a 20musec delay. Required for Davinci EVM */
while (cnt--);
DEB1("addr: 0x%04x, len: %d, flags: 0x%x, stop: %d",
msg->addr, msg->len, msg->flags, stop);
spin_lock_irqsave( &i2c_spinlock, flags );
/* set the slave address */
dev->regs->icsar = msg->addr;
/* Sigh, seems we can't do zero length transactions. Thus, we
* can't probe for devices w/o actually sending/receiving at least
* a single byte. So we'll set count to 1 for the zero length
* transaction case and hope we don't cause grief for some
* arbitrary device due to random byte write/read during
* probes.
*/
if (msg->len == 0) {
dev->buf = &zero_byte;
dev->buf_len = 1;
} else {
dev->buf = msg->buf;
dev->buf_len = msg->len;
}
dev->regs->iccnt = dev->buf_len;
dev->cmd_err = 0;
init_completion( &dev->cmd_completion );
/* Clear any pending interrupts by reading the IVR */
stat = dev->regs->icivr;
/* Take I2C out of reset, configure it as master and set the start bit */
flag =
DAVINCI_I2C_ICMDR_IRS_MASK | DAVINCI_I2C_ICMDR_MST_MASK |
DAVINCI_I2C_ICMDR_STT_MASK;
/* if the slave address is ten bit address, enable XA bit */
if (msg->flags & I2C_M_TEN)
flag |= DAVINCI_I2C_ICMDR_XA_MASK;
if (!(msg->flags & I2C_M_RD))
flag |= DAVINCI_I2C_ICMDR_TRX_MASK;
if (stop)
flag |= DAVINCI_I2C_ICMDR_STP_MASK;
/* write the data into mode register */
dev->regs->icmdr = flag;
/* Enable receive and transmit interrupts */
if (msg->flags & I2C_M_RD)
dev->regs->icimr |= DAVINCI_I2C_ICIMR_ICRRDY_MASK;
else {
dev->regs->icimr |= DAVINCI_I2C_ICIMR_ICXRDY_MASK;
/* Prime the pump */
if ( dev->regs->icstr & DAVINCI_I2C_ICSTR_ICXRDY_MASK ) {
dev->regs->icdxr = *dev->buf++;
dev->buf_len--;
}
}
spin_unlock_irqrestore( &i2c_spinlock, flags );
/* wait for the transaction to complete */
r = wait_for_completion_interruptible_timeout( &dev->cmd_completion,
DAVINCI_I2C_TIMEOUT );
dev->buf_len = 0;
if ( r < 0 ) {
return r;
}
if (r == 0 ) {
printk( "I2C command timeout, icivr=0x%04x, status=0x%04x\n",
dev->regs->icivr, dev->regs->icstr );
i2c_davinci_reset(dev);
return -ETIMEDOUT;
}
/* no error */
if (!dev->cmd_err)
return msg->len;
/* We have an error */
if (dev->cmd_err & DAVINCI_I2C_ICSTR_NACK_MASK) {
if (msg->flags & I2C_M_IGNORE_NAK)
return msg->len;
if (stop)
dev->regs->icmdr |= DAVINCI_I2C_ICMDR_STP_MASK;
return -EREMOTEIO;
}
if (dev->cmd_err & DAVINCI_I2C_ICSTR_AL_MASK ||
dev->cmd_err & DAVINCI_I2C_ICSTR_RSFULL_MASK) {
i2c_davinci_reset(dev);
return -EIO;
}
return msg->len;
}
static int pca_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg *msgs,
int num)
{
struct i2c_algo_pca_data *adap = i2c_adap->algo_data;
struct i2c_msg *msg = NULL;
int curmsg;
int numbytes = 0;
int state;
int ret;
int completed = 1;
unsigned long timeout = jiffies + i2c_adap->timeout;
while ((state = pca_status(adap)) != 0xf8) {
if (time_before(jiffies, timeout)) {
msleep(10);
} else {
dev_dbg(&i2c_adap->dev, "bus is not idle. status is "
"%#04x\n", state);
return -EAGAIN;
}
}
DEB1("{{{ XFER %d messages\n", num);
if (i2c_debug >= 2) {
for (curmsg = 0; curmsg < num; curmsg++) {
int addr, i;
msg = &msgs[curmsg];
addr = (0x7f & msg->addr) ;
if (msg->flags & I2C_M_RD)
printk(KERN_INFO " [%02d] RD %d bytes from %#02x [%#02x, ...]\n",
curmsg, msg->len, addr, (addr << 1) | 1);
else {
printk(KERN_INFO " [%02d] WR %d bytes to %#02x [%#02x%s",
curmsg, msg->len, addr, addr << 1,
msg->len == 0 ? "" : ", ");
for (i = 0; i < msg->len; i++)
printk("%#04x%s", msg->buf[i], i == msg->len - 1 ? "" : ", ");
printk("]\n");
}
}
}
curmsg = 0;
ret = -EREMOTEIO;
while (curmsg < num) {
state = pca_status(adap);
DEB3("STATE is 0x%02x\n", state);
msg = &msgs[curmsg];
switch (state) {
case 0xf8: /* On reset or stop the bus is idle */
completed = pca_start(adap);
break;
case 0x08: /* A START condition has been transmitted */
case 0x10: /* A repeated start condition has been transmitted */
completed = pca_address(adap, msg);
break;
case 0x18: /* SLA+W has been transmitted; ACK has been received */
case 0x28: /* Data byte in I2CDAT has been transmitted; ACK has been received */
if (numbytes < msg->len) {
completed = pca_tx_byte(adap,
msg->buf[numbytes]);
numbytes++;
break;
}
curmsg++; numbytes = 0;
if (curmsg == num)
pca_stop(adap);
else
completed = pca_repeated_start(adap);
break;
case 0x20: /* SLA+W has been transmitted; NOT ACK has been received */
DEB2("NOT ACK received after SLA+W\n");
pca_stop(adap);
goto out;
case 0x40: /* SLA+R has been transmitted; ACK has been received */
completed = pca_rx_ack(adap, msg->len > 1);
break;
case 0x50: /* Data bytes has been received; ACK has been returned */
if (numbytes < msg->len) {
pca_rx_byte(adap, &msg->buf[numbytes], 1);
numbytes++;
completed = pca_rx_ack(adap,
numbytes < msg->len - 1);
break;
}
curmsg++; numbytes = 0;
if (curmsg == num)
pca_stop(adap);
else
completed = pca_repeated_start(adap);
break;
case 0x48: /* SLA+R has been transmitted; NOT ACK has been received */
DEB2("NOT ACK received after SLA+R\n");
pca_stop(adap);
goto out;
case 0x30: /* Data byte in I2CDAT has been transmitted; NOT ACK has been received */
DEB2("NOT ACK received after data byte\n");
pca_stop(adap);
goto out;
case 0x38: /* Arbitration lost during SLA+W, SLA+R or data bytes */
DEB2("Arbitration lost\n");
/*
* The PCA9564 data sheet (2006-09-01) says "A
* START condition will be transmitted when the
* bus becomes free (STOP or SCL and SDA high)"
* when the STA bit is set (p. 11).
*
* In case this won't work, try pca_reset()
* instead.
*/
pca_start(adap);
goto out;
case 0x58: /* Data byte has been received; NOT ACK has been returned */
if (numbytes == msg->len - 1) {
pca_rx_byte(adap, &msg->buf[numbytes], 0);
curmsg++; numbytes = 0;
if (curmsg == num)
pca_stop(adap);
else
completed = pca_repeated_start(adap);
} else {
DEB2("NOT ACK sent after data byte received. "
"Not final byte. numbytes %d. len %d\n",
numbytes, msg->len);
pca_stop(adap);
goto out;
}
break;
case 0x70: /* Bus error - SDA stuck low */
DEB2("BUS ERROR - SDA Stuck low\n");
pca_reset(adap);
goto out;
case 0x90: /* Bus error - SCL stuck low */
DEB2("BUS ERROR - SCL Stuck low\n");
pca_reset(adap);
goto out;
case 0x00: /* Bus error during master or slave mode due to illegal START or STOP condition */
DEB2("BUS ERROR - Illegal START or STOP\n");
pca_reset(adap);
goto out;
default:
dev_err(&i2c_adap->dev, "unhandled SIO state 0x%02x\n", state);
break;
}
if (!completed)
goto out;
}
ret = curmsg;
out:
DEB1("}}} transfered %d/%d messages. "
"status is %#04x. control is %#04x\n",
curmsg, num, pca_status(adap),
pca_get_con(adap));
return ret;
}
static int pca_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg msgs[],
int num)
{
struct i2c_algo_pca_data *adap = i2c_adap->algo_data;
struct i2c_msg *msg = NULL;
int curmsg;
int numbytes = 0;
int state;
state = pca_status(adap);
if ( state != 0xF8 ) {
printk(KERN_ERR DRIVER ": bus is not idle. status is %#04x\n", state );
/* FIXME: what to do. Force stop ? */
return -EREMOTEIO;
}
DEB1("{{{ XFER %d messages\n", num);
if (i2c_debug>=2) {
for (curmsg = 0; curmsg < num; curmsg++) {
int addr, i;
msg = &msgs[curmsg];
addr = (0x7f & msg->addr) ;
if (msg->flags & I2C_M_RD )
printk(KERN_INFO " [%02d] RD %d bytes from %#02x [%#02x, ...]\n",
curmsg, msg->len, addr, (addr<<1) | 1);
else {
printk(KERN_INFO " [%02d] WR %d bytes to %#02x [%#02x%s",
curmsg, msg->len, addr, addr<<1,
msg->len == 0 ? "" : ", ");
for(i=0; i < msg->len; i++)
printk("%#04x%s", msg->buf[i], i == msg->len - 1 ? "" : ", ");
printk("]\n");
}
}
}
curmsg = 0;
while (curmsg < num) {
state = pca_status(adap);
DEB3("STATE is 0x%02x\n", state);
msg = &msgs[curmsg];
switch (state) {
case 0xf8: /* On reset or stop the bus is idle */
pca_start(adap);
break;
case 0x08: /* A START condition has been transmitted */
case 0x10: /* A repeated start condition has been transmitted */
pca_address(adap, msg);
break;
case 0x18: /* SLA+W has been transmitted; ACK has been received */
case 0x28: /* Data byte in I2CDAT has been transmitted; ACK has been received */
if (numbytes < msg->len) {
pca_tx_byte(adap, msg->buf[numbytes]);
numbytes++;
break;
}
curmsg++; numbytes = 0;
if (curmsg == num)
pca_stop(adap);
else
pca_repeated_start(adap);
break;
case 0x20: /* SLA+W has been transmitted; NOT ACK has been received */
DEB2("NOT ACK received after SLA+W\n");
pca_stop(adap);
return -EREMOTEIO;
case 0x40: /* SLA+R has been transmitted; ACK has been received */
pca_rx_ack(adap, msg->len > 1);
break;
case 0x50: /* Data bytes has been received; ACK has been returned */
if (numbytes < msg->len) {
pca_rx_byte(adap, &msg->buf[numbytes], 1);
numbytes++;
pca_rx_ack(adap, numbytes < msg->len - 1);
break;
}
curmsg++; numbytes = 0;
if (curmsg == num)
pca_stop(adap);
else
pca_repeated_start(adap);
break;
case 0x48: /* SLA+R has been transmitted; NOT ACK has been received */
DEB2("NOT ACK received after SLA+R\n");
pca_stop(adap);
return -EREMOTEIO;
case 0x30: /* Data byte in I2CDAT has been transmitted; NOT ACK has been received */
DEB2("NOT ACK received after data byte\n");
return -EREMOTEIO;
case 0x38: /* Arbitration lost during SLA+W, SLA+R or data bytes */
DEB2("Arbitration lost\n");
return -EREMOTEIO;
case 0x58: /* Data byte has been received; NOT ACK has been returned */
if ( numbytes == msg->len - 1 ) {
pca_rx_byte(adap, &msg->buf[numbytes], 0);
curmsg++; numbytes = 0;
if (curmsg == num)
pca_stop(adap);
else
pca_repeated_start(adap);
} else {
DEB2("NOT ACK sent after data byte received. "
"Not final byte. numbytes %d. len %d\n",
numbytes, msg->len);
pca_stop(adap);
return -EREMOTEIO;
}
break;
case 0x70: /* Bus error - SDA stuck low */
DEB2("BUS ERROR - SDA Stuck low\n");
pca_reset(adap);
return -EREMOTEIO;
case 0x90: /* Bus error - SCL stuck low */
DEB2("BUS ERROR - SCL Stuck low\n");
pca_reset(adap);
return -EREMOTEIO;
case 0x00: /* Bus error during master or slave mode due to illegal START or STOP condition */
DEB2("BUS ERROR - Illegal START or STOP\n");
pca_reset(adap);
return -EREMOTEIO;
default:
printk(KERN_ERR DRIVER ": unhandled SIO state 0x%02x\n", state);
break;
}
}
DEB1(KERN_CRIT "}}} transfered %d messages. "
"status is %#04x. control is %#04x\n",
num, pca_status(adap),
pca_get_con(adap));
return curmsg;
}
static int __init i2c_davinci_init(void)
{
int status;
struct device *dev = NULL;
DEB0("%s %s", __TIME__, __DATE__);
DEB1("i2c_davinci_init()");
if (cpu_is_davinci_dm6467())
davinci_i2c_expander_op (0x3A, I2C_INT_DM646X, 0);
/*
* NOTE: On DaVinci EVM, the i2c bus frequency is set to 20kHz
* so that the MSP430, which is doing software i2c, has
* some extra processing time
*/
if (machine_is_davinci_evm())
i2c_davinci_busFreq = 20;
else if (machine_is_davinci_dm6467_evm())
i2c_davinci_busFreq = 100;
else if (i2c_davinci_busFreq > 200)
i2c_davinci_busFreq = 400; /*Fast mode */
else
i2c_davinci_busFreq = 100; /*Standard mode */
i2c_clock = clk_get (dev, "I2CCLK");
if (IS_ERR(i2c_clock))
return -1;
clk_use (i2c_clock);
clk_enable (i2c_clock);
i2c_davinci_inputClock = clk_get_rate (i2c_clock);
DEB1 ("IP CLOCK = %ld", i2c_davinci_inputClock);
memset(&i2c_davinci_dev, 0, sizeof(i2c_davinci_dev));
init_waitqueue_head(&i2c_davinci_dev.cmd_wait);
i2c_davinci_dev.regs = (davinci_i2cregsovly)I2C_BASE;
status = (int)request_region(I2C_BASE, I2C_IOSIZE, MODULE_NAME);
if (!status) {
i2c_err("I2C is already in use\n");
return -ENODEV;
}
status = request_irq(IRQ_I2C, i2c_davinci_isr, 0, "i2c",
&i2c_davinci_dev);
if (status) {
i2c_err("failed to request I2C IRQ");
goto do_release_region;
}
i2c_set_adapdata(&i2c_davinci_adap, &i2c_davinci_dev);
status = i2c_add_adapter(&i2c_davinci_adap);
if (status) {
i2c_err("failed to add adapter");
goto do_free_irq;
}
i2c_davinci_reset(&i2c_davinci_dev);
if (driver_register(&davinci_i2c_driver) != 0)
printk(KERN_ERR "Driver register failed for davinci_i2c\n");
if (platform_device_register(&davinci_i2c_device) != 0) {
printk(KERN_ERR "Device register failed for i2c\n");
driver_unregister(&davinci_i2c_driver);
}
return 0;
do_free_irq:
free_irq(IRQ_I2C, &i2c_davinci_dev);
do_release_region:
release_region(I2C_BASE, I2C_IOSIZE);
return status;
}
/*
* Interrupt service routine. This gets called whenever an I2C interrupt
* occurs.
*/
static irqreturn_t
i2c_davinci_isr(int this_irq, void *dev_id, struct pt_regs *reg)
{
struct i2c_davinci_device *dev = dev_id;
u32 stat;
DEB1("i2c_davinci_isr()");
while ((stat = dev->regs->icivr) != 0) {
switch (stat) {
case DAVINCI_I2C_ICIVR_INTCODE_AL:
dev->cmd_err |= DAVINCI_I2C_ICSTR_AL_MASK;
i2c_warn("i2c: AL detected");
i2c_davinci_complete_cmd(dev);
break;
case DAVINCI_I2C_ICIVR_INTCODE_NACK:
dev->cmd_err |= DAVINCI_I2C_ICSTR_NACK_MASK;
i2c_warn("i2c: NACK detected");
i2c_davinci_complete_cmd(dev);
break;
case DAVINCI_I2C_ICIVR_INTCODE_RAR:
dev->regs->icstr |= DAVINCI_I2C_ICSTR_ARDY_MASK;
i2c_davinci_complete_cmd(dev);
break;
case DAVINCI_I2C_ICIVR_INTCODE_RDR:
if (dev->buf_len) {
*dev->buf++ = dev->regs->icdrr;
dev->buf_len--;
if (dev->buf_len) {
continue;
} else {
dev->regs->icimr &=
~DAVINCI_I2C_ICIMR_ICRRDY_MASK;
}
}
break;
case DAVINCI_I2C_ICIVR_INTCODE_TDR:
if (dev->buf_len) {
dev->regs->icdxr = *dev->buf++;
dev->buf_len--;
if (dev->buf_len)
continue;
else {
dev->regs->icimr &=
~DAVINCI_I2C_ICIMR_ICXRDY_MASK;
}
}
break;
case DAVINCI_I2C_ICIVR_INTCODE_SCD:
dev->regs->icstr |= DAVINCI_I2C_ICSTR_SCD_MASK;
i2c_davinci_complete_cmd(dev);
break;
case DAVINCI_I2C_ICIVR_INTCODE_AAS:
i2c_warn("i2c: AAS detected");
break;
default:
i2c_warn("i2c: unknown status: %d", stat);
break;
} /* switch */
} /* while */
return IRQ_HANDLED;
}
/*
* Low level master read/write transaction. This function is called
* from i2c_davinci_xfer.
*/
static int
i2c_davinci_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
{
struct i2c_davinci_device *dev = i2c_get_adapdata(adap);
u8 zero_byte = 0;
u32 flag = 0, stat = 0;
int i;
DEB1("addr: 0x%04x, len: %d, flags: 0x%x, stop: %d",
msg->addr, msg->len, msg->flags, stop);
/* Introduce a 100musec delay. Required for Davinci EVM board only */
if (cpu_is_davinci_dm644x())
udelay(100);
/* set the slave address */
dev->regs->icsar = msg->addr;
/* Sigh, seems we can't do zero length transactions. Thus, we
* can't probe for devices w/o actually sending/receiving at least
* a single byte. So we'll set count to 1 for the zero length
* transaction case and hope we don't cause grief for some
* arbitrary device due to random byte write/read during
* probes.
*/
if (msg->len == 0) {
dev->buf = &zero_byte;
dev->buf_len = 1;
} else {
dev->buf = msg->buf;
dev->buf_len = msg->len;
}
dev->regs->iccnt = dev->buf_len;
dev->cmd_complete = 0;
dev->cmd_err = 0;
/* Clear any pending interrupts by reading the IVR */
stat = dev->regs->icivr;
/* Take I2C out of reset, configure it as master and set the start bit */
flag =
DAVINCI_I2C_ICMDR_IRS_MASK | DAVINCI_I2C_ICMDR_MST_MASK |
DAVINCI_I2C_ICMDR_STT_MASK;
/* if the slave address is ten bit address, enable XA bit */
if (msg->flags & I2C_M_TEN)
flag |= DAVINCI_I2C_ICMDR_XA_MASK;
if (!(msg->flags & I2C_M_RD))
flag |= DAVINCI_I2C_ICMDR_TRX_MASK;
if (stop)
flag |= DAVINCI_I2C_ICMDR_STP_MASK;
/* Enable receive and transmit interrupts */
if (msg->flags & I2C_M_RD)
dev->regs->icimr |= DAVINCI_I2C_ICIMR_ICRRDY_MASK;
else
dev->regs->icimr |= DAVINCI_I2C_ICIMR_ICXRDY_MASK;
/* write the data into mode register */
dev->regs->icmdr = flag;
/* wait for the transaction to complete */
wait_event_timeout (dev->cmd_wait, dev->cmd_complete, DAVINCI_I2C_TIMEOUT);
dev->buf_len = 0;
if (!dev->cmd_complete) {
i2c_warn("i2c: cmd complete failed: complete = 0x%x, \
icstr = 0x%x\n", dev->cmd_complete,
dev->regs->icstr);
if (cpu_is_davinci_dm644x() || cpu_is_davinci_dm355()) {
/* Send the NACK to the slave */
dev->regs->icmdr |= DAVINCI_I2C_ICMDR_NACKMOD_MASK;
/* Disable I2C */
disable_i2c_pins();
/* Send high and low on the SCL line */
for (i = 0; i < 10; i++)
pulse_i2c_clock();
/* Re-enable I2C */
enable_i2c_pins();
}
i2c_davinci_reset(dev);
dev->cmd_complete = 0;
return -ETIMEDOUT;
}
dev->cmd_complete = 0;
/* no error */
if (!dev->cmd_err)
return msg->len;
/* We have an error */
if (dev->cmd_err & DAVINCI_I2C_ICSTR_NACK_MASK) {
if (msg->flags & I2C_M_IGNORE_NAK)
return msg->len;
if (stop)
dev->regs->icmdr |= DAVINCI_I2C_ICMDR_STP_MASK;
return -EREMOTEIO;
}
if (dev->cmd_err & DAVINCI_I2C_ICSTR_AL_MASK) {
i2c_davinci_reset(dev);
return -EIO;
}
return msg->len;
}
/*
* This functions configures I2C and brings I2C out of reset.
* This function is called during I2C init function. This function
* also gets called if I2C encounetrs any errors. Clock calculation portion
* of this function has been taken from some other driver.
*/
static int i2c_davinci_reset(struct i2c_davinci_device *dev)
{
u32 psc, d, div, clk;
DEB1("i2c: reset called");
/* put I2C into reset */
dev->regs->icmdr &= ~DAVINCI_I2C_ICMDR_IRS_MASK;
/* NOTE: I2C Clock divider programming info
* As per I2C specs the following formulas provide prescalar
* and low/high divider values
*
* input clk --> PSC Div -----------> ICCL/H Div --> output clock
* module clk
*
* output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
*
* Thus,
* (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
*
* where if PSC == 0, d = 7,
* if PSC == 1, d = 6
* if PSC > 1 , d = 5
*/
/*
* Choose PSC to get a 12MHz or lower clock frequency after the
* prescaler.
*/
psc = (i2c_davinci_inputClock + (I2C_PRESCALED_CLOCK - 1)) /
I2C_PRESCALED_CLOCK - 1;
if (psc == 0)
d = 7;
else if (psc == 1)
d = 6;
else
d = 5;
div = 2*(psc + 1)*i2c_davinci_busFreq*1000;
clk = (i2c_davinci_inputClock + div - 1)/div;
if (clk >= d)
clk -= d;
else
clk = 0;
dev->regs->icpsc = psc;
dev->regs->icclkh = clk; /* duty cycle should be 50% */
dev->regs->icclkl = clk;
DEB1("CLK = %ld KHz",
i2c_davinci_inputClock / (2 * (psc + 1) * (clk + d) * 1000));
DEB1("PSC = %d", dev->regs->icpsc);
DEB1("CLKL = %d", dev->regs->icclkl);
DEB1("CLKH = %d", dev->regs->icclkh);
/* Set Own Address: */
dev->regs->icoar = i2c_davinci_own_addr;
/* Enable interrupts */
dev->regs->icimr = I2C_DAVINCI_INTR_ALL;
enable_i2c_pins();
/* Take the I2C module out of reset: */
dev->regs->icmdr |= DAVINCI_I2C_ICMDR_IRS_MASK;
return 0;
}
static int pca_xfer(struct i2c_adapter *i2c_adap,
struct i2c_msg *msgs,
int num)
{
struct i2c_algo_pca_data *adap = i2c_adap->algo_data;
struct i2c_msg *msg = NULL;
int curmsg;
int numbytes = 0;
int state;
int ret;
int completed = 1;
unsigned long timeout = jiffies + i2c_adap->timeout;
while ((state = pca_status(adap)) != 0xf8) {
if (time_before(jiffies, timeout)) {
msleep(10);
} else {
dev_dbg(&i2c_adap->dev, "bus is not idle. status is "
"%#04x\n", state);
return -EAGAIN;
}
}
DEB1("{{{ XFER %d messages\n", num);
if (i2c_debug >= 2) {
for (curmsg = 0; curmsg < num; curmsg++) {
int addr, i;
msg = &msgs[curmsg];
addr = (0x7f & msg->addr) ;
if (msg->flags & I2C_M_RD)
#ifdef CONFIG_DEBUG_PRINTK
printk(KERN_INFO " [%02d] RD %d bytes from %#02x [%#02x, ...]\n",
curmsg, msg->len, addr, (addr << 1) | 1);
#else
;
#endif
else {
#ifdef CONFIG_DEBUG_PRINTK
printk(KERN_INFO " [%02d] WR %d bytes to %#02x [%#02x%s",
curmsg, msg->len, addr, addr << 1,
msg->len == 0 ? "" : ", ");
#else
;
#endif
for (i = 0; i < msg->len; i++)
#ifdef CONFIG_DEBUG_PRINTK
printk("%#04x%s", msg->buf[i], i == msg->len - 1 ? "" : ", ");
#else
;
#endif
#ifdef CONFIG_DEBUG_PRINTK
printk("]\n");
#else
;
#endif
}
}
}