void config_interrupts(void) { IRQ_map(IRQ_EVT_EDMAINT, 8); // CHECK same settings in BIOS!!! IRQ_clear(IRQ_EVT_EDMAINT); IRQ_enable(IRQ_EVT_EDMAINT); SWI_enable(); IRQ_globalEnable(); }
void config_interrupts(void) { LOG_printf(&myLog, "config interrupts begin"); //Wie muss das mapping genau stattfinden? // McBSP --> EDMA ? // EDMA --> CPU ? // IRQ_globalDisable(); IRQ_map(IRQ_EVT_EDMAINT, 8); // EIGEN!!!: Ist hier 8 richtig? IRQ_clear(IRQ_EVT_EDMAINT); // EIGEN!!!: IRQ_enable(IRQ_EVT_EDMAINT); // EIGEN!!!: IRQ_globalEnable(); LOG_printf(&myLog, "config interrupts end"); }
void convInit( ) { convObject.unMillimetersPerTrigger = CONV_MILLIMETERS_PER_TRIGGER; convObject.unLastTicks = 0; convObject.unLastDeltaTicks = 0; convObject.unNumTotalTriggerSignals = 0; convObject.unTimeoutTicks = timeFromMs( convHal.unTimeout ); convObject.bStanding = TRUE; // PRE: the HWI link to our handler function is set by the config tool. IRQ_clear( convHal.unExtInterrupt ); IRQ_enable( convHal.unExtInterrupt ); // Enable the interrupt in the FPGA ppuMemory[CONV_REG_INTENABLE_ADDR] |= CONV_REG_INTENABLE_MASK; // Init the high res timer that we're going to use timeInit(); }
/* * initIrq() - Initialize and enable the DMA receive interrupt using the CSL. * The interrupt service routine for this interrupt is edmaHwi. */ void initIrq(void) { /* Enable EDMA interrupts to the CPU */ IRQ_clear(IRQ_EVT_EDMAINT); // Clear any pending EDMA interrupts IRQ_enable(IRQ_EVT_EDMAINT); // Enable EDMA interrupt }
void DSK6713_configure_AIC23() { /* Configure McBSP0 as control interface for aic23 */ MCBSP_Handle MCBSP0_handle; MCBSP0_handle = MCBSP_open(MCBSP_DEV0, MCBSP_OPEN_RESET); MCBSP_config(MCBSP0_handle, &MCBSP0_config); MCBSP_start(MCBSP0_handle, MCBSP_XMIT_START | MCBSP_SRGR_START | MCBSP_SRGR_START, 220); set_aic23_register(MCBSP0_handle, RESET_REGISTER, 0x0000); set_aic23_register(MCBSP0_handle, POWER_DOWN_CONTROL, 0x0000); set_aic23_register(MCBSP0_handle, LEFT_LINE_INPUT_CHANNEL_VOLUME, 0x0017); set_aic23_register(MCBSP0_handle, RIGHT_LINE_INPUT_CHANNEL_VOLUME, 0x0017); set_aic23_register(MCBSP0_handle, LEFT_CHANNEL_HEADPHONE_VOLUME, 0x00f9); set_aic23_register(MCBSP0_handle, RIGHT_CHANNEL_HEADPHONE_VOLUME, 0x00f9); set_aic23_register(MCBSP0_handle, ANALOG_AUDIO_PATH, 0x0011); // 00001 0010 set_aic23_register(MCBSP0_handle, DIGITAL_AUDIO_PATH, 0x0000); // 000000000 set_aic23_register(MCBSP0_handle, DIGITAL_AUDIO_INTERFACE_FORMAT, 0x0043); //0 0100 0001 set_aic23_register(MCBSP0_handle, SAMPLE_RATE_CONTROL, 0x000d); // 01100 set_aic23_register(MCBSP0_handle, DIGITAL_INTERFACE_ACTIVATION, 0x0001); /* Configure McBSP1 as data interface for aic23 */ MCBSP_Handle MCBSP1_handle; MCBSP1_handle = MCBSP_open(MCBSP_DEV1, MCBSP_OPEN_RESET); MCBSP_config(MCBSP1_handle, &MCBSP1_config); MCBSP_start(MCBSP1_handle, MCBSP_XMIT_START|MCBSP_RCV_START|MCBSP_SRGR_FRAMESYNC|MCBSP_SRGR_START, 220); /* Configure receive EDMA */ EDMA_Handle hEdmaRcv; EDMA_Handle hEdmaRcvA; EDMA_Handle hEdmaRcvB; hEdmaRcv = EDMA_open(EDMA_CHA_REVT1, EDMA_OPEN_RESET); hEdmaRcvA = EDMA_allocTable(-1); hEdmaRcvB = EDMA_allocTable(-1); gEdmaRcvConfig.src = MCBSP_getRcvAddr(MCBSP1_handle); // Get address of DRR gTccRcvChan = EDMA_intAlloc(-1); // get next free transfer complete code gEdmaRcvConfig.opt |= EDMA_FMK(OPT, TCC, gTccRcvChan); EDMA_config(hEdmaRcv, &gEdmaRcvConfig); EDMA_config(hEdmaRcvA, &gEdmaRcvConfig); gEdmaRcvConfig.dst = EDMA_DST_OF(gRcvBufferB); EDMA_config(hEdmaRcvB, &gEdmaRcvConfig); EDMA_link(hEdmaRcv, hEdmaRcvB); EDMA_link(hEdmaRcvB, hEdmaRcvA); EDMA_link(hEdmaRcvA, hEdmaRcvB); /* Configure transmit EDMA */ EDMA_Handle hEdmaXmt; EDMA_Handle hEdmaXmtA; EDMA_Handle hEdmaXmtB; hEdmaXmt = EDMA_open(EDMA_CHA_XEVT1, EDMA_OPEN_RESET); hEdmaXmtA = EDMA_allocTable(-1); hEdmaXmtB = EDMA_allocTable(-1); gEdmaXmtConfig.dst = MCBSP_getXmtAddr(MCBSP1_handle); // Get address of DXR gTccXmtChan = EDMA_intAlloc(-1); // get next free transfer complete code gEdmaXmtConfig.opt |= EDMA_FMK(OPT, TCC, gTccXmtChan); EDMA_config(hEdmaXmt, &gEdmaXmtConfig); EDMA_config(hEdmaXmtA, &gEdmaXmtConfig); gEdmaXmtConfig.src = EDMA_DST_OF(gXmtBufferB); // set source to buffer B EDMA_config(hEdmaXmtB, &gEdmaXmtConfig); EDMA_link(hEdmaXmt, hEdmaXmtB); EDMA_link(hEdmaXmtB, hEdmaXmtA); EDMA_link(hEdmaXmtA, hEdmaXmtB); EDMA_intClear(gTccRcvChan); EDMA_intClear(gTccXmtChan); EDMA_intEnable(gTccRcvChan); EDMA_intEnable(gTccXmtChan); gBufferState.cpuBufferState = StateB; // inittial cpu buffer state EDMA_enableChannel(hEdmaRcv); EDMA_enableChannel(hEdmaXmt); IRQ_clear(IRQ_EVT_EDMAINT); IRQ_enable(IRQ_EVT_EDMAINT); MCBSP_write(MCBSP1_handle, 0x00); }