void vSetupHighFrequencyTimer( void ) { /* Timer CMT2 is used to generate the interrupts, and CMT3 is used to measure the jitter. */ /* Enable compare match timer 2 and 3. */ MSTP( CMT2 ) = 0; MSTP( CMT3 ) = 0; /* Interrupt on compare match. */ CMT2.CMCR.BIT.CMIE = 1; /* Set the compare match value. */ CMT2.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / timerINTERRUPT_FREQUENCY ) -1 ) / 8 ); /* Divide the PCLK by 8. */ CMT2.CMCR.BIT.CKS = 0; CMT3.CMCR.BIT.CKS = 0; /* Enable the interrupt... */ _IEN( _CMT2_CMI2 ) = 1; /* ...and set its priority to the maximum possible, this is above the priority set by configMAX_SYSCALL_INTERRUPT_PRIORITY so will nest. */ _IPR( _CMT2_CMI2 ) = timerHIGHEST_PRIORITY; /* Start the timers. */ CMT.CMSTR1.BIT.STR2 = 1; CMT.CMSTR1.BIT.STR3 = 1; }
/******************************************************************************* * Outline : Stopping the peripherals which start operations after a reset * Header : r_init_stop_module.h * Function Name: R_INIT_StopModule * Description : Configure the setting to enter module-stop state. * Arguments : none * Return Value : none *******************************************************************************/ void R_INIT_StopModule(void) { /* ---- Enable write protection ---- */ /* PRCR - Protect Register b15:b8 PRKEY - PRC Key Code - A5h (The write value should be A5h to permission writing PRCi bit) b1 PRC1 - Protect Bit 1 - Write enabled */ SYSTEM.PRCR.WORD = 0xA502; /* ---- Set transition to module-stop state ---- */ #if MSTP_STATE_DMACDTC == MODULE_STOP_ENABLE MSTP(DTC) = 1; /* DMAC/DTC trans to module-stop state */ #endif #if MSTP_STATE_EXDMAC == MODULE_STOP_ENABLE MSTP(EXDMAC) = 1; /* EXDMAC trans to module-stop state */ #endif #if MSTP_STATE_RAM0 == MODULE_STOP_ENABLE MSTP(RAM0) = 1; /* RAM0 trans to module-stop state */ #endif #if MSTP_STATE_RAM1 == MODULE_STOP_ENABLE MSTP(RAM1) = 1; /* RAM1 trans to module-stop state */ #endif /* ---- Disable write protection ---- */ /* PRCR - Protect Register b15:b8 PRKEY - PRC Key Code - A5h (The write value should be A5h to permission writing PRCi bit) b1 PRC1 - Protect Bit 1 - Write disabled*/ SYSTEM.PRCR.WORD = 0xA500; }
/****************************************************************************** * Function name : cmt_init * Description : Create one-shot timers based on PCLK / 3 * Arguments : None * Return Value : None ******************************************************************************/ void cmt_init(void) { #ifdef PLATFORM_BOARD_RDKRX63N SYSTEM.PRCR.WORD = 0xA50B; /* Protect off */ #endif /* Cancel CMT module stop state. */ MSTP(CMT0) = 0; MSTP(CMT1) = 0; #ifdef PLATFORM_BOARD_RDKRX63N SYSTEM.PRCR.WORD = 0xA500; /* Protect on */ #endif /* Compare Match Timer Control Register (CMCR) b15:b8 reserved: Read/Write value always 0 b7 reserved: Read undef. Write value always 1 b6 CMIE: Compare Match Interrupt Enable b5:b2 reserved: Read/Write value always 0 b1:b0 CKS: clock select 3 = count on PCLK / 512 */ CMT0.CMCR.WORD = 0x0003; /* Just set clock divisor for now. */ CMT1.CMCR.WORD = 0x0003; CMT2.CMCR.WORD = 0x0003; /* Compare Match Timer Counter (CMCNT) b15:b0 16-bit readable/writable up-counter to generate interrupt requests. */ CMT0.CMCNT = 0x00; /* Clear the count (default value). */ CMT1.CMCNT = 0x00; CMT2.CMCNT = 0x00; /* Compare Match Timer Constant Register (CMCOR)) b15:b0 16-bit register sets the value for a compare match with CMCNT. */ CMT0.CMCOR = 0xFFFF; /* Set to max (default value). */ CMT1.CMCOR = 0xFFFF; CMT2.CMCOR = 0xFFFF; IR (CMT0, CMI0); /* Interrupt reset. */ IR (CMT1, CMI1); IR (CMT2, CMI2); IPR(CMT0, CMI0) = 4; /* Interrupt priority set. */ IPR(CMT1, CMI1) = 4; IPR(CMT2, CMI2) = 4; IEN(CMT0, CMI0) = 1; /* Interrupt enable. */ IEN(CMT1, CMI1) = 1; IEN(CMT2, CMI2) = 1; } /* End of function cmt_init() */
/* The RX port uses this callback function to configure its tick interrupt. This allows the application to choose the tick interrupt source. */ void vApplicationSetupTimerInterrupt( void ) { const uint32_t ulEnableRegisterWrite = 0xA50BUL, ulDisableRegisterWrite = 0xA500UL; /* Disable register write protection. */ SYSTEM.PRCR.WORD = ulEnableRegisterWrite; /* Enable compare match timer 0. */ MSTP( CMT0 ) = 0; /* Interrupt on compare match. */ CMT0.CMCR.BIT.CMIE = 1; /* Set the compare match value. */ CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) -1 ) / 8 ); /* Divide the PCLK by 8. */ CMT0.CMCR.BIT.CKS = 0; /* Enable the interrupt... */ _IEN( _CMT0_CMI0 ) = 1; /* ...and set its priority to the application defined kernel priority. */ _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; /* Start the timer. */ CMT.CMSTR0.BIT.STR0 = 1; /* Reneable register protection. */ SYSTEM.PRCR.WORD = ulDisableRegisterWrite; }
void MTU5W_Setup() { // Unlock ports #ifdef PLATFORM_BOARD_RDKRX63N SYSTEM.PRCR.WORD = 0xA50B; #endif /* Setup echo read port PD5 (pin 18 on jn2) input */ // Input data register PORTD.PIDR.BIT.B5 = 0x0; // Direction register (input) PORTD.PDR.BIT.B5 = 0x0; // Mode register (peripheral) PORTD.PMR.BIT.B5 = 0x1; // Turn on MTU5 MSTP(MTU5) = 0; // Set MTU5 pre-scaler to PCLK/16 MTU5.TCRW.BIT.TPSC = 0x02; // Make MTU5W count MTU5.TIORW.BYTE= 0x1d; // Enable interrupt on input detected // MTU5.TIER.BIT.TGIE5W = 0x1; // Use pin with timer MPC.PD5PFS.BIT.PSEL = 0x01; // Ensure timer is stopped MTU5W_Stop(); // Lock ports #ifdef PLATFORM_BOARD_RDKRX63N SYSTEM.PRCR.WORD = 0xA500; #endif }
void vApplicationSetupTimerInterrupt(void) { //Disable protection SYSTEM.PRCR.WORD = 0xA50B; //Cancel CMT0 module stop state MSTP(CMT0) = 0; //Enable protection SYSTEM.PRCR.WORD = 0xA500; //Select PCLK/8 clock CMT0.CMCR.BIT.CKS = 0; //Set the compare match value CMT0.CMCOR = ((PCLK_HZ / configTICK_RATE_HZ) - 1) / 8; //Interrupt on compare match CMT0.CMCR.BIT.CMIE = 1; //Set interrupt priority _IPR(_CMT0_CMI0) = configKERNEL_INTERRUPT_PRIORITY; //Enable compare match interrupt _IEN(_CMT0_CMI0) = 1; //Start timer CMT.CMSTR0.BIT.STR0 = 1; }
/****************************************************************************** Function Name : vApplicationSetupTimerInterrupt Description : setup tick timer Arguments : none Return value : none ******************************************************************************/ void vApplicationSetupTimerInterrupt( void ) { /* protect off */ SYSTEM.PRCR.WORD = 0xA502; /* Enable compare match timer 0. */ MSTP( CMT0 ) = 0; /* Interrupt on compare match. */ //CMT0.CMCR.BIT.CMIE = 1; /* Divide the PCLK by 8. */ //CMT0.CMCR.BIT.CKS = 0; CMT0.CMCR.WORD = 0x00C0; // CKS=00b,CMIE=1; PCLK/8,Compare match interrupt (CMIn) enabled @48MHz /* Set the compare match value. */ CMT0.CMCOR = ( unsigned short ) ( ( ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ )) / 8 - 1); /* Enable the interrupt... */ _IEN( _CMT0_CMI0 ) = 1; /* ...and set its priority to the application defined kernel priority. */ _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; /* Start the timer. */ CMT.CMSTR0.BIT.STR0 = 1; /* protect on */ SYSTEM.PRCR.WORD = 0xA500; }
HalSci5::HalSci5(){ int i; PORTC.ICR.BIT.B2 = 1; PORTC.DDR.BIT.B2 = 0; PORTC.DDR.BIT.B3 = 1; MSTP(SCI5) = 0; SCI5.SCR.BYTE = 0x00; SCI5.SMR.BYTE = 0x00; SCI5.SCMR.BIT.SMIF= 0; SCI5.SCMR.BIT.SINV= 0; SCI5.SCMR.BIT.SDIR= 0; SCI5.BRR = 12; //SCI5.SEMR.BIT.ABCS = 1; for(i=0;i<0x800000;i++); SCI5.SCR.BYTE = 0x30; SCI5.SCR.BIT.TE=1; SCI5.SCR.BIT.TIE=1; SCI5.SCR.BIT.RE=1; SCI5.SCR.BIT.RIE=1; IEN(SCI5,RXI5)=0; IEN(SCI5,TXI5)=1; IPR(SCI5,TXI5)=GeneralConfig::gpsIpr; IPR(SCI5,RXI5)=GeneralConfig::gpsIpr; }
/****************************************************************************** * ID : 61.0 * Outline : YRDKRX62N_RSPIConfig * Include : YRDKRX62N_RSPI0.h * Function Name: YRDKRX62N_RSPIConfig * Description : Setup and ready the RSPI0 for communications. * Argument : none * Return Value : none * Calling Functions : YRDKRX62N_RSPIOpen ******************************************************************************/ void YRDKRX62N_RSPIConfig(void) { MSTP(RSPI0) = 0 ; /* Select proper bank of pins for SPI0 */ IOPORT.PFGSPI.BIT.RSPIS = 0 ; /* SCK (PC.5) is active */ IOPORT.PFGSPI.BIT.RSPCKE = 1 ; /* SSL3 (PC.2) is inactive (toggled as GPIO instead) */ IOPORT.PFGSPI.BIT.SSL3E = 0 ; /* MOSI (PC.6) is active */ IOPORT.PFGSPI.BIT.MOSIE = 1 ; /* Set up chip select pin */ /* Make it an output */ PORTC.DDR.BIT.B2 = 1 ; /* Set level to inactive */ PORTC.DR.BIT.B2 = 1 ; /* MISO as an input */ PORTC.DDR.BIT.B7 = 1 ; /* Enable input buffer for peripheral */ PORTC.DR.BIT.B7 = 1 ; /* MOSI as an output */ PORTC.DDR.BIT.B6 = 1 ; /* Enable input buffer for peripheral */ PORTC.DR.BIT.B6 = 1 ; /* SCK as an output */ PORTC.DDR.BIT.B5 = 1 ; /* Set level to inactive */ PORTC.DR.BIT.B5 = 1 ; /* Initialize SPI (per flowchart in hardware manual) */ /* No loopback, CMos Output */ RSPI0.SPPCR.BYTE = 0x00 ; /* Full Speed is 0x00 255 works */ RSPI0.SPBR.BYTE = 0x00 ; /* 16-bit data 1 frame 1 chip select */ RSPI0.SPDCR.BYTE = 0x00 ; /* 2 clock delay before next access to SPI device */ RSPI0.SPCKD.BYTE = 0x00 ; /* 2 clock delay after de-asserting SSL */ RSPI0.SSLND.BYTE = 0x00 ; /* 2 clock delay before next access to SPI device */ RSPI0.SPND.BYTE = 0x00 ; /* No parity no idle interrupts */ RSPI0.SPCR2.BYTE = 0x00 ; /* MSB first 8-bit data, keep SSL low */ RSPI0.SPCMD0.WORD = 0x0700 ; /* Enable RSPI 3wire in master mode with RSPI Enable Transmit Only and Interupt */ RSPI0.SPCR.BYTE = 0x6B ; /* SSL3A Polarity */ RSPI0.SSLP.BYTE = 0x08 ; /* One frame. */ RSPI0.SPSCR.BYTE = 0x00 ; }
/*********************************************************************************************************************** * Function Name: power_on_off * Description : Switches power to an MTU channel. Required by FIT spec. * Arguments : channel - * Which channel to use. * on_or_off - * What it says. * Return Value : none ***********************************************************************************************************************/ void power_on_off (uint8_t on_or_off) { R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); MSTP(MTU) = on_or_off; // All channels are on the same module stop register. R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); }
/*---------------------------------------------------------------------------* * Routine: IADCConfig *---------------------------------------------------------------------------* * Description: * Setup the ADC for reading but don't start it * Outputs: * T_RX63N_ADC_Workspace *aW -- Particular ADC workspace * ADC_RequestSingle *aRequest -- Configuration of ADC device *---------------------------------------------------------------------------*/ static void IADCConfig( T_RX63N_ADC_Workspace *p, ADC_RequestSingle *aRequest) { // Ensure the power is on MSTP(S12AD) = 0; S12AD.ADCSR.BIT.ADST = 0; // 0: Stops a scan conversion process. // 1: Starts a scan conversion process. S12AD.ADCSR.BIT.EXTRG = 0; // 0: Scan conversion is started by a timer // source selected by the A/D start // trigger select register (ADSTRGR). // 1: Scan conversion is started by an // external trigger (ADTRG0#). S12AD.ADCSR.BIT.TRGE = 0; // 0: Disables scan conversion to be started // by an external trigger (ADTRG0#) or a // trigger of MTU or TMR. // 1: Enables scan conversion to be started // by an external trigger (ADTRG0#) or a // trigger of MTU or TMR. S12AD.ADCSR.BIT.CKS = 0; // 00: PCLK/8 // 01: PCLK/4 // 10: PCLK/2 // 11: PCLK S12AD.ADCSR.BIT.ADIE = 0; // 0: Disables ADI interrupt generation // upon scan conversion completion. // 1: Enables ADI interrupt generation // upon scan conversion completion. S12AD.ADCSR.BIT.ADCS = 0; // 0: Single-cycle scan mode // 1: Continuous scan mode S12AD.ADCER.BIT.ACE = 0; // 0: Disables automatic clearing of the // A/D data register n (ADDRn) after // it has been read. // 1: Enables automatic clearing of the // A/D data register n (ADDRn) after // it has been read. S12AD.ADCER.BIT.ADRFMT = 0; // 0: Right-alignment is selected for the // A/D data register n (ADDRn) format. // 1: Left-alignment is selected for the // A/D data register n (ADDRn) format. // A/D Channel Select if(aRequest->iADCChannel < 16) { S12AD.ADANS0.WORD = 1<<aRequest->iADCChannel; S12AD.ADANS1.WORD = 0; } else { S12AD.ADANS0.WORD = 0; S12AD.ADANS1.WORD = 1<<(aRequest->iADCChannel-16); } }
void vInitialiseTimerForIntQueueTest( void ) { uint32_t ulCompareMatchValue; const uint32_t ulPeripheralClockDivider = 6UL, ulCMTClockDivider = 8UL; /* Disable CMI2 and CMI3 interrupts. */ VIC.IEC0.LONG = ( 1UL << 23UL ) | ( 1UL << 24UL ); /* Cancel CMT stop state in LPC. */ r_rst_write_enable(); MSTP( CMT1 ) = 0U; r_rst_write_disable(); /* Interrupt on compare match. */ CMT2.CMCR.BIT.CMIE = 1; CMT3.CMCR.BIT.CMIE = 1; /* Calculate the compare match value. */ ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider; ulCompareMatchValue /= ulCMTClockDivider; ulCompareMatchValue /= tmrCMT_1_CHANNEL_0_HZ; ulCompareMatchValue -= 1UL; CMT2.CMCOR = ( unsigned short ) ulCompareMatchValue; ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider; ulCompareMatchValue /= ulCMTClockDivider; ulCompareMatchValue /= tmrCMT_1_CHANNEL_1_HZ; ulCompareMatchValue -= 1UL; CMT3.CMCOR = ( unsigned short ) ulCompareMatchValue; /* Divide the PCLK by 8. */ CMT2.CMCR.BIT.CKS = 0; CMT3.CMCR.BIT.CKS = 0; /* Clear count to 0. */ CMT2.CMCNT = 0; CMT3.CMCNT = 0; /* Set CMI2 and CMI3 edge detection type. */ VIC.PLS0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL ); /* Set CMI2 and CMI3 priority levels so they nest. */ VIC.PRL23.LONG = _CMT_PRIORITY_LEVEL2; VIC.PRL24.LONG = _CMT_PRIORITY_LEVEL9; /* Set CMI2 and CMI3 interrupt address. */ VIC.VAD23.LONG = ( uint32_t ) vCMT_1_Channel_0_ISR_Entry; VIC.VAD24.LONG = ( uint32_t ) vCMT_1_Channel_1_ISR_Entry; /* Enable CMI2 and CMI3 interrupts in ICU. */ VIC.IEN0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL ); /* Start CMT1 channel 0 and 1 count. */ CMT.CMSTR1.BIT.STR2 = 1U; CMT.CMSTR1.BIT.STR3 = 1U; }
RX63N_CAN::RX63N_CAN() { port = &PORT3; CANx = &CAN0; MSTP(CAN0) = 0; transmission_config(); pin_config(); CAN_MODE_HALT(); default_mailbox_config(); CAN_MODE_TEST(0x3, true); /*Test Mode*/ CAN_MODE_OPERATION(); };
/*********************************************************************************************************************** * Function Name: R_RSPI1_Create * Description : This function initializes the RSPI1 module. * Arguments : None * Return Value : None ***********************************************************************************************************************/ void R_RSPI1_Create(void) { /* Disable RSPI interrupts */ VIC.IEC2.LONG = 0x00200000UL; /* Disable SPTI1 interrupt */ VIC.IEC2.LONG = 0x00400000UL; /* Disable SPEI1 interrupt */ VIC.IEC2.LONG = 0x00800000UL; /* Disable SPII1 interrupt */ /* Set interrupt detection type */ VIC.PLS2.LONG |= 0x00200000UL; /* Set SPTI1 edge detection interrupt */ /* Cancel RSPI module stop state */ MSTP(RSPI1) = 0U; /* Disable RSPI function */ RSPI1.SPCR.BIT.SPE = 0U; /* Set control registers */ RSPI1.SPPCR.BYTE = _RSPI_MOSI_LEVEL_HIGH | _RSPI_MOSI_FIXING_MOIFV_BIT | _RSPI_OUTPUT_PIN_CMOS | _RSPI_LOOPBACK_DISABLED | _RSPI_LOOPBACK2_DISABLED; RSPI1.SPBR = _RSPI1_DIVISOR; RSPI1.SPDCR.BYTE = _RSPI_ACCESS_LONGWORD | _RSPI_FRAMES_1; RSPI1.SPSCR.BYTE = _RSPI_SEQUENCE_LENGTH_1; RSPI1.SSLP.BYTE = _RSPI_SSL0_POLARITY_LOW | _RSPI_SSL1_POLARITY_LOW; RSPI1.SPCKD.BYTE = _RSPI_RSPCK_DELAY_1; RSPI1.SSLND.BYTE = _RSPI_SSL_NEGATION_DELAY_1; RSPI1.SPND.BYTE = _RSPI_NEXT_ACCESS_DELAY_1; RSPI1.SPCR2.BYTE = _RSPI_PARITY_DISABLE; RSPI1.SPCMD0.WORD = _RSPI_RSPCK_SAMPLING_EVEN | _RSPI_RSPCK_POLARITY_HIGH | _RSPI_BASE_BITRATE_1 | _RSPI_SIGNAL_ASSERT_SSL0 | _RSPI_SSL_KEEP_DISABLE | _RSPI_DATA_LENGTH_BITS_8 | _RSPI_MSB_FIRST | _RSPI_NEXT_ACCESS_DELAY_DISABLE | _RSPI_NEGATION_DELAY_DISABLE | _RSPI_RSPCK_DELAY_DISABLE; /* Set SPTI1 priority level */ VIC.PRL85.LONG = _RSPI_PRIORITY_LEVEL6; /* Set SPEI1 priority level */ VIC.PRL86.LONG = _RSPI_PRIORITY_LEVEL5; /* Set SPII1 priority level */ VIC.PRL87.LONG = _RSPI_PRIORITY_LEVEL7; /* Set SPTI1 interrupt address */ VIC.VAD85.LONG = (uint32_t)r_rspi1_transmit_interrupt; /* Set SPEI1 interrupt address */ VIC.VAD86.LONG = (uint32_t)r_rspi1_error_interrupt; /* Set SPII1 interrupt address */ VIC.VAD87.LONG = (uint32_t)r_rspi1_idle_interrupt; RSPI1.SPCR.BYTE = _RSPI_MODE_SPI | _RSPI_TRANSMIT_ONLY | _RSPI_MASTER_MODE; }
static void prvSetupTimerInterrupt( void ) { /* Unlock. */ SYSTEM.PRCR.WORD = portUNLOCK_KEY; /* Enable CMT0. */ MSTP( CMT0 ) = 0; /* Lock again. */ SYSTEM.PRCR.WORD = portLOCK_KEY; /* Interrupt on compare match. */ CMT0.CMCR.BIT.CMIE = 1; /* Set the compare match value. */ CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick; /* Divide the PCLK. */ #if portCLOCK_DIVISOR == 512 { CMT0.CMCR.BIT.CKS = 3; } #elif portCLOCK_DIVISOR == 128 { CMT0.CMCR.BIT.CKS = 2; } #elif portCLOCK_DIVISOR == 32 { CMT0.CMCR.BIT.CKS = 1; } #elif portCLOCK_DIVISOR == 8 { CMT0.CMCR.BIT.CKS = 0; } #else { #error Invalid portCLOCK_DIVISOR setting } #endif /* Enable the interrupt... */ _IEN( _CMT0_CMI0 ) = 1; /* ...and set its priority to the application defined kernel priority. */ _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY; /* Start the timer. */ CMT.CMSTR0.BIT.STR0 = 1; }
/*********************************************************************************************************************** * Function Name: R_CMT0_Create * Description : This function initializes the CMT0 channel. * Arguments : None * Return Value : None ***********************************************************************************************************************/ void R_CMT0_Create(void) { /* Disable CMI interrupt */ IEN(CMT0, CMI0) = 0U; /* Cancel CMT stop state in LPC */ MSTP(CMT0) = 0U; /* Set control registers */ CMT0.CMCR.WORD = _0002_CMT_CMCR_CKS_PCLK128 | _0040_CMT_CMCR_CMIE_ENABLE; CMT0.CMCOR = _B71B_CMT0_CMCOR_VALUE; /* Set CMI0 priority level */ IPR(CMT0,CMI0) = _08_CMT_PRIORITY_LEVEL8; }
void ADC_HALInit(void) { /***** 10ビットA/Dコンバータの初期設定 *****/ /* AD0モジュールストップ解除 */ MSTP(AD0) = 0; /* ADTRG0#からのトリガ選択 ,PCLK/8(6MHz≧4MHz),シングルモード選択 */ AD0.ADCR.BIT.TRGS = 0x3; AD0.ADCR.BIT.MODE = 0; AD0.ADCR.BIT.CKS = 0; /* AN0選択, 変換停止, ADI0割り込み要求の発生を許可 */ AD0.ADCSR.BIT.CH = 0; AD0.ADCSR.BIT.ADIE = 1; /* 割り込みステータスフラグクリア */ IR ( AD0, ADI0 )= 0; IEN( AD0, ADI0 )= 0; IPR( AD0, ADI0 )= 2; }
/* * The application must provide a function that configures a peripheral to * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() * in FreeRTOSConfig.h to call the function. */ void vConfigureTickInterrupt( void ) { uint32_t ulCompareMatchValue; const uint32_t ulPeripheralClockDivider = 6UL, ulCMTClockDivider = 8UL; /* Disable CMI5 interrupt. */ VIC.IEC9.LONG = 0x00001000UL; /* Cancel CMT stop state in LPC. */ r_rst_write_enable(); MSTP( CMT2 ) = 0U; r_rst_write_disable(); /* Interrupt on compare match. */ CMT5.CMCR.BIT.CMIE = 1; /* Calculate the compare match value. */ ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider; ulCompareMatchValue /= ulCMTClockDivider; ulCompareMatchValue /= configTICK_RATE_HZ; ulCompareMatchValue -= 1UL; /* Set the compare match value. */ CMT5.CMCOR = ( unsigned short ) ulCompareMatchValue; /* Divide the PCLK by 8. */ CMT5.CMCR.BIT.CKS = 0; CMT5.CMCNT = 0; /* Set CMI5 edge detection type. */ VIC.PLS9.LONG |= 0x00001000UL; /* Set CMI5 priority level to the lowest possible. */ VIC.PRL300.LONG = _CMT_PRIORITY_LEVEL31; /* Set CMI5 interrupt address */ VIC.VAD300.LONG = ( uint32_t ) FreeRTOS_Tick_Handler_Entry; /* Enable CMI5 interrupt in ICU. */ VIC.IEN9.LONG |= 0x00001000UL; /* Start CMT5 count. */ CMT.CMSTR2.BIT.STR5 = 1U; }
void debugInit(uint32_t baudrate) { //All-module clock stop mode is disabled SYSTEM.MSTPCRA.BIT.ACSE = 0; //Disable protection SYSTEM.PRCR.WORD = 0xA50B; //Cancel SCI2 module stop state MSTP(SCI2) = 0; //Enable protection SYSTEM.PRCR.WORD = 0xA500; //Disable SCI2 module SCI2.SCR.BYTE = 0x00; //Unlock MPC registers MPC.PWPR.BIT.B0WI = 0; MPC.PWPR.BIT.PFSWE = 1; //Configure TXD2 (P50) PORT5.PMR.BIT.B0 = 1; MPC.P50PFS.BYTE = 0x4A; //Configure RXD2 (P52) PORT5.PMR.BIT.B2 = 1; MPC.P52PFS.BYTE = 0x4A; //Lock MPC registers MPC.PWPR.BIT.PFSWE = 0; MPC.PWPR.BIT.B0WI = 0; //Configure UART (8 bits, no parity, 1 stop bit) SCI2.SMR.BYTE = 0; //Select serial communication mode SCI2.SCMR.BIT.SMIF = 0; //Set baudrate SCI2.BRR = PCLK_HZ / (32 * baudrate) - 1; //Enable transmission and reception SCI2.SCR.BYTE |= 0x30; }
/*********************************************************************************************************************** * Function Name: R_S12AD0_Create * Description : This function initializes the AD0 converter. * Arguments : None * Return Value : None ***********************************************************************************************************************/ void R_S12AD0_Create(void) { /* Cancel S12ADC0 module stop state */ MSTP(S12ADC0) = 0U; /* Disable and clear S12ADI0, S12GBADI0, S12CMPI0 interrupt flags */ S12ADC0.ADCSR.BIT.ADIE = 0U; S12ADC0.ADCSR.BIT.GBADIE = 0U; S12ADC0.ADCMPCR.BIT.CMPIE = 0U; VIC.IEC1.LONG = 0x00000008UL; /* Set S12AD0 control registers */ S12ADC0.ADDISCR.BYTE = _AD0_DISCONECT_SETTING; S12ADC0.ADCSR.WORD = _AD_DBLTRIGGER_DISABLE | _AD_SCAN_END_INTERRUPT_ENABLE | _AD_SINGLE_SCAN_MODE; S12ADC0.ADCER.WORD = _AD_AUTO_CLEARING_DISABLE | _AD_RIGHT_ALIGNMENT | _AD_RESOLUTION_12BIT; S12ADC0.ADADC.BYTE = _AD_1_TIME_CONVERSION | _AD_ADDITION_MODE; /* Set channels and sampling time */ S12ADC0.ADANSA.WORD = _AD0_CHANNEL_SELECT_A; S12ADC0.ADADS.WORD = _AD0_ADDAVG_CHANNEL_SELECT; S12ADC0.ADSSTR7.BYTE = _AD0_SAMPLING_STATE_7; /* Set compare control register */ S12ADC0.ADCMPCR.BYTE = _AD_WINDOWFUNCTION_DISABLE; S12ADC0.ADCMPANSR.WORD = _AD0_COMPARECHANNEL_SELECT; S12ADC0.ADCMPLR.WORD = _AD0_COMPARELEVEL_SELECT; S12ADC0.ADCMPDR0 = 0x0000U; /* Set S12ADI0 edge detection type */ VIC.PLS1.LONG |= 0x00000008UL; /* Set S12ADI0 interrupt priority level */ VIC.PRL35.LONG = _AD_PRIORITY_LEVEL0; /* Set S12ADI0 interrupt address */ VIC.VAD35.LONG = (uint32_t)r_s12ad_s12adi0_interrupt; }
/*---------------------------------------------------------------------------* * Routine: vApplicationSetupTimerInterrupt *---------------------------------------------------------------------------* * Description: * The RX port uses this callback function to configure its tick * interrupt. This allows the application to choose the tick interrupt * source. *---------------------------------------------------------------------------*/ void vApplicationSetupTimerInterrupt(void) { /* Enable compare match timer 0. */ MSTP( CMT0) = 0; /* Interrupt on compare match. */ CMT0.CMCR.BIT.CMIE = 1; /* Set the compare match value. */ CMT0.CMCOR = (unsigned short)(((PCLK_FREQUENCY / configTICK_RATE_HZ) - 1) / 8); /* Divide the PCLK by 8. */ CMT0.CMCR.BIT.CKS = 0; /* Enable the interrupt... */ _IEN( _CMT0_CMI0) = 1; /* ...and set its priority to the application defined kernel priority. */ _IPR( _CMT0_CMI0) = configKERNEL_INTERRUPT_PRIORITY; /* Start the timer. */ CMT.CMSTR0.BIT.STR0 = 1; }
HalSci0::HalSci0(){ int i; PORT2.ICR.BIT.B1 = 1; PORT2.DDR.BIT.B1 = 0; MSTP(SCI0) = 0; SCI0.SCR.BYTE = 0x00; SCI0.SMR.BYTE = 0x00; SCI0.SCMR.BIT.SMIF= 0; SCI0.SCMR.BIT.SINV= 0; SCI0.SCMR.BIT.SDIR= 0; SCI0.BRR = 12; //SCI0.SEMR.BIT.ABCS = 1; for(i=0;i<0x800000;i++); SCI0.SCR.BYTE = 0x30; SCI0.SCR.BIT.TE=1; SCI0.SCR.BIT.TIE=1; SCI0.SCR.BIT.RE=1; SCI0.SCR.BIT.RIE=1; IEN(SCI0,RXI0)=0; IEN(SCI0,TXI0)=1; IPR(SCI0,TXI0)=GeneralConfig::uartIpr; IPR(SCI0,RXI0)=GeneralConfig::uartIpr; SCI0.SSR.BYTE=(char)(SCI0.SSR.BYTE & 0x80); echo =0; }
/****************************************************************************** * タイトル :D U A L S H O C K * 関数名 : init_Rspi_dualshock * 戻り値 : void型 * 引数1 : char型 s[] ******************************************************************************/ void init_Rspi_dualshock(void) //(デュアルショック用) { MSTP(RSPI1) = 0; //RSPI1モジュールストップの解除 RSPI1.SPCR.BYTE = 0x00; //始めにRSPI通信を使用するために0x00で通信を有効に RSPI1.SPPCR.BIT.SPLP = 0; //RSPIループバックビルド=通常モード RSPI1.SPPCR.BIT.SPLP2 = 0; //RSPI2スープバックビルド=通常モード RSPI1.SPPCR.BIT.SPOM = 0; //RSPI出力端子モードビット=CMOS出力 RSPI1.SPPCR.BIT.MOIFV = 1; //MOSIアイドル固定値ビット1 RSPI1.SPPCR.BIT.MOIFE = 1; //MOSI出力値はMOIFVビットの設定値 RSPI1.SPBR = 75; //RSPIビットレートレジスタ=255最低速度 RSPI1.SPDCR.BIT.SPFC = 0x00; //SPDRレジスタに格納できるフレーム数を1にする RSPI1.SPDCR.BIT.SLSEL = 0x00; //SSL端子出力設定余ったポートをIOポートにする=すべて出力用 RSPI1.SPDCR.BIT.SPRDTD = 0; //RSPI受信/送信データ選択ビット=SPDRは受信バッファを読みだす RSPI1.SPDCR.BIT.SPLW = 1; //SPDRレジスタへはロングワードアクセス。 RSPI1.SPSCR.BIT.SPSLN = 0x02; //RSPIシーケンス長設定ビット=シーケンス長3 RSPI1.SPCKD.BIT.SCKDL = 0x00; //RSPCK遅延設定ビット=1RSPCK RSPI1.SSLND.BIT.SLNDL = 0x00; //SSLネゲート遅延設定ビット=1RSPCK RSPI1.SPND.BIT.SPNDL = 0x00; //RSPI次アクセス遅延設定ビット=1RSPCK+2PCLK RSPI1.SPCR2.BIT.SPPE = 0; //パリティ有効ビット、送信データのパリティビットを付加しない RSPI1.SPCR2.BIT.SPOE = 0; //パリティモードビット=偶数パリティイで送受信 RSPI1.SPCR2.BIT.SPIIE = 1; //アイドル割り込み要求の発生を許可 RSPI1.SPCR2.BIT.PTE = 0; //パリティ回路自己診断機能は無効 RSPI1.SPCMD0.BIT.CPHA = 1; //奇数エッジでデータ変化、偶数エッジでデータサンプル RSPI1.SPCMD0.BIT.CPOL = 1; //アイドル時のRSPCKが'1' RSPI1.SPCMD0.BIT.BRDV = 0x03; //ベースのビットレートを8分周を選択 RSPI1.SPCMD0.BIT.SSLA = 0x00; //SSL信号アサート設定ビット=SSLO RSPI1.SPCMD0.BIT.SSLKP = 1; //転送終了後から次アクセス開始までSSL信号レベルを保持 RSPI1.SPCMD0.BIT.SPB = 0x03; //RSPIデータ長設定ビット=32ビット RSPI1.SPCMD0.BIT.LSBF = 1; //RSPILSBファーストビット=LSBファーストビット RSPI1.SPCMD0.BIT.SPNDEN = 1; //次アクセス遅延はRSPI次アクセス遅延レジスタ(SPND)の設定値 RSPI1.SPCMD0.BIT.SLNDEN = 1; //次アクセス遅延設定許可ビット=SSLネゲート遅延はRSPIスレーブセレクトネゲート遅延レジスタ(SSLND)の設定値 RSPI1.SPCMD0.BIT.SCKDEN = 1; //RSPCK遅延はRSPCK遅延はRSPIクロック遅延レジスタ(SPCKD)の設定値 RSPI1.SPCMD1.WORD = RSPI1.SPCMD0.WORD; //4バイト毎の送信時に行う設定をコピーさせる RSPI1.SPCMD2.WORD = RSPI1.SPCMD0.WORD; //1バイト毎の送信時に行う設定をコピーさせる RSPI1.SPCMD2.BIT.SPB = 0x07; //RSPIデータ長設定ビット=8ビット RSPI1.SPCMD2.BIT.SSLKP = 0; //送信が終わった際に出力をHighにするため //割り込みコントローラの設定 //DMACAの設定 //入出力ポートの設定 (今回はシングルマスタ設定のため入出力が自動で決定される) PORTE.ICR.BIT.B7 = 1; IOPORT.PFHSPI.BIT.RSPIS = 1; IOPORT.PFHSPI.BIT.RSPCKE = 1; //RSPCKB端子有効 IOPORT.PFHSPI.BIT.MOSIE = 1; //MOSIB端子有効 IOPORT.PFHSPI.BIT.MISOE = 1; //MISOB端子有効 IOPORT.PFHSPI.BIT.SSL0E = 1; //SSLB0端子有効 IOPORT.PFHSPI.BIT.SSL1E = 1; //SSLB1端子有効 IOPORT.PFHSPI.BIT.SSL2E = 1; //SSLB2端子有効 IOPORT.PFHSPI.BIT.SSL3E = 1; //SSLB3端子有効 RSPI1.SPCR.BIT.SPMS = 0; //RSPIモード選択ビット=SPI動作(4線式) RSPI1.SPCR.BIT.TXMD = 0; //通信動作モード選択ビット=全二重同期式シリアル通信 RSPI1.SPCR.BIT.MODFEN = 0; //モードフォルトエラー検出を禁止 RSPI1.SPCR.BIT.MSTR = 1; //RSPIマスタ/スレーブモード選択=マスタモード RSPI1.SPCR.BIT.SPEIE = 0; //RSPIエラー割り込み要求の発生を禁止 RSPI1.SPCR.BIT.SPTIE = 0; //RSPI送信割り込み要求の発生を禁止 RSPI1.SPCR.BIT.SPE = 1; //RSPI機能を有効に RSPI1.SPCR.BIT.SPRIE = 1; //RSPI受信割り込み要求の発生を許可 RSPI1.SSLP.BIT.SSLP0 = 0; //SSL0信号は0アクティブ RSPI1.SSLP.BIT.SSLP1 = 0; //SSL1信号は0アクティブ RSPI1.SSLP.BIT.SSLP2 = 0; //SSL2信号は0アクティブ RSPI1.SSLP.BIT.SSLP3 = 0; //SSL3信号は0アクティブ //以下不要の場合は削除の事 RSPI1.SPSR.BIT.OVRF = 0; //オーバランエラーなし RSPI1.SPSR.BIT.IDLNF = 0; //RSPIがアイドル状態(後で送るときだけ1を代入するのだろうか)<武山のでは使用されていなかった>? RSPI1.SPSR.BIT.MODF = 0; //モードフォルトエラーなし RSPI1.SPSR.BIT.PERF = 0; //パリティエラーなし //以上不要の場合は削除の事 RSPI1.SPCR.BYTE; //SPCRのリード IEN(RSPI1,SPRI1) = 1; IPR(RSPI1,SPRI1) = 12; }
/*********************************************************************************************************************** * Function name: output_ports_configure * Description : Configures the port and pin direction settings, and sets the pin outputs to a safe level. * Arguments : none * Return value : none ***********************************************************************************************************************/ static void output_ports_configure(void) { /* Unlock MPC registers to enable writing to them. */ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_MPC); MSTP(EDMAC) = 0 ; /* Power up ethernet block */ /* Port 0 - DAC & ethernet IRQ */ PORT0.PODR.BYTE = 0x00 ; /* All outputs low to start */ PORT0.PDR.BYTE = 0x10 ; /* DA1 is an ouput, all others are inputs */ /* Port 1 - I2C and USB over-current & pull-up control */ PORT1.PODR.BYTE = 0x00 ; /* All outputs low to start */ PORT1.PDR.BYTE = 0x80 ; /* AUD_R (P1.7) is an output, all others are inputs (I2C lines setup by * I2C driver later */ /* Port 2 - USB control and some expansion signals */ PORT2.PODR.BYTE = 0x02 ; /* All outputs low to start except backlight enable */ PORT2.PDR.BYTE = 0x26 ; /* All inputs except backlight enable - some will be overridden by USB driver later */ /* Port 3 - Serial port & JTAG */ PORT3.PODR.BYTE = 0x00 ; /* All outputs low to start */ PORT3.PDR.BIT.B2 = 0x01 ; /* Transmit line for SCI6/ CAN 0 TxD is an output */ /* Port 4 - */ PORT4.PODR.BYTE = 0x00 ; /* These are all inputs */ PORT4.PDR.BYTE = 0x00 ; /* Analog inputs and switches, all inputs */ PORT4.PMR.BYTE = 0x00 ; MPC.P42PFS.BYTE = 0x80 ; /* P42 is used for AD input on pot. */ /* Port 5 - */ PORT5.PODR.BYTE = 0x00 ; /* All outputs low to start */ PORT5.PDR.BYTE = 0x13 ; /* SCI 2 TxD, LCD_RS, PWMLP_OUT are outputs */ PORT5.PMR.BYTE = 0x00 ; /* All GPIO for now */ MPC.P50PFS.BYTE = 0x0A ; /* P50 is TXD2. */ MPC.P52PFS.BYTE = 0x0A ; /* P52 is RXD2. */ PORT5.PMR.BYTE = 0x05 ; /* P50 and P52 are used for SCI2. */ /* Port A - Ethernet MDIO */ // PORTA.PODR.BYTE = 0x00 ; /* */ // PORTA.PMR.BYTE = 0x00 ; /* All GPIO for now */ // MPC.PA3PFS.BYTE = 0x11 ; /* PA3 is RMII MDIO */ // MPC.PA4PFS.BYTE = 0x11 ; /* PA4 is RMII MDC */ // MPC.PA5PFS.BYTE = 0x11 ; /* PA5 is RMII LINK_STA */ // PORTA.PMR.BYTE = 0x38 ; /* PA3-5 are used by Ethernet peripheral */ // PORTA.PDR.BYTE = 0xFF ; /* */ // /* Port B - Ethernet signals */ // PORTB.PODR.BYTE = 0x00 ; /* */ // PORTB.PMR.BYTE = 0x00 ; /* All GPIO for now */ // MPC.PB0PFS.BYTE = 0x12 ; /* PB0 is RMII_RXD1 */ // MPC.PB1PFS.BYTE = 0x12 ; /* PB1 is RMII_RXD0 */ // MPC.PB2PFS.BYTE = 0x12 ; /* PB2 is REF50CK */ // MPC.PB3PFS.BYTE = 0x12 ; /* PB3 is RMI_RX_ERR */ // MPC.PB4PFS.BYTE = 0x12 ; /* PB4 is RMII_TXD_EN */ // MPC.PB5PFS.BYTE = 0x12 ; /* PB5 is RMII_TXD0 */ // MPC.PB6PFS.BYTE = 0x12 ; /* PB6 is RMII_TXD1 */ // MPC.PB7PFS.BYTE = 0x12 ; /* PB7 is RMII_CRS_DV */ // PORTB.PMR.BYTE = 0xFF ; /* All pins assigned to peripheral */ // PORTB.PDR.BYTE = 0xF0 ; /* */ PORTB.PDR.BYTE = 0xFF; PORTB.PODR.BIT.B5 = 1; /* Port C - SPI signals, chip selects, peripheral reset */ PORTC.PODR.BYTE = 0x00 ; /* */ PORTC.PMR.BYTE = 0x00 ; /* All GPIO for now */ MPC.PC5PFS.BYTE = 0x0D ; /* PC5 is RSPCKA */ MPC.PC6PFS.BYTE = 0x0D ; /* PC6 is MOSIA */ MPC.PC7PFS.BYTE = 0x0D ; /* PC7 is MISOA */ PORTC.PMR.BYTE = 0xE0 ; /* PC5-7 assigned to SPI peripheral */ PORTC.PODR.BYTE = 0x17 ; /* All outputs low to start */ PORTC.PDR.BYTE = 0x7F ; /* All outputs except MISO */ /* Port D - LED's */ PORTD.PODR.BYTE = 0xFF ; /* All outputs LED's off */ PORTD.PDR.BYTE = 0xFF ; /* All outputs */ /* Port E - LED's, WiFi & PMOD control */ PORTE.PODR.BYTE = 0xFF ; /* All LED's off, all chip selects inactive */ PORTE.PDR.BYTE = 0x7F ; /* All outputs except PMOD_MISO */ /* Port J - WiFi chip select */ PORTJ.PODR.BYTE = 0x08 ; /* WiFi CS de-asserted at power up */ PORTJ.PDR.BYTE = 0x08 ; /* WiFi CS is an output */ /* Lock MPC registers. */ R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_MPC); }
error_t rx63nEthInit(NetInterface *interface) { error_t error; //Debug message TRACE_INFO("Initializing RX63N Ethernet MAC...\r\n"); //Disable protection SYSTEM.PRCR.WORD = 0xA50B; //Cancel EDMAC module stop state MSTP(EDMAC) = 0; //Enable protection SYSTEM.PRCR.WORD = 0xA500; //GPIO configuration rx63nEthInitGpio(interface); //Reset EMAC module EDMAC.EDMR.BIT.SWR = 1; sleep(10); //PHY transceiver initialization error = interface->phyDriver->init(interface); //Failed to initialize PHY transceiver? if(error) return error; //Initialize DMA descriptor lists rx63nEthInitDmaDesc(interface); //Maximum frame length that can be accepted ETHERC.RFLR.LONG = 1518; //Set default inter packet gap (96-bit time) ETHERC.IPGR.LONG = 0x14; //Set the upper 32 bits of the MAC address ETHERC.MAHR = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) | (interface->macAddr.b[2] << 8) | interface->macAddr.b[3]; //Set the lower 16 bits of the MAC address ETHERC.MALR.BIT.MA = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5]; //Set descriptor length (16 bytes) EDMAC.EDMR.BIT.DL = 0; //Select little endian mode EDMAC.EDMR.BIT.DE = 1; //Use store and forward mode EDMAC.TFTR.BIT.TFT = 0; //Set transmit FIFO size (2048 bytes) EDMAC.FDR.BIT.TFD = 7; //Set receive FIFO size (2048 bytes) EDMAC.FDR.BIT.RFD = 7; //Enable continuous reception of multiple frames EDMAC.RMCR.BIT.RNR = 1; //Accept transmit interrupt notifications EDMAC.TRIMD.BIT.TIM = 0; EDMAC.TRIMD.BIT.TIS = 1; //Disable all EDMAC interrupts EDMAC.EESIPR.LONG = 0; //Enable only the desired EDMAC interrupts EDMAC.EESIPR.BIT.TWBIP = 1; EDMAC.EESIPR.BIT.FRIP = 1; //Configure EDMAC interrupt priority IPR(ETHER, EINT) = RX63N_ETH_IRQ_PRIORITY; //Enable transmission and reception ETHERC.ECMR.BIT.TE = 1; ETHERC.ECMR.BIT.RE = 1; //Instruct the DMA to poll the receive descriptor list EDMAC.EDRRR.BIT.RR = 1; //Force the TCP/IP stack to check the link state osSetEvent(&interface->nicRxEvent); //RX63N Ethernet MAC is now ready to send osSetEvent(&interface->nicTxEvent); //Successful initialization return NO_ERROR; }
void BSP_Ser_Init (CPU_INT32U baud_rate) { CPU_INT08U baud_clk; CPU_INT16U brr; CPU_REG32 i; /* Initialize OS Objects. */ BSP_OS_SemCreate(&BSP_SerTxWait, 0, "Serial Tx Wait"); BSP_OS_SemCreate(&BSP_SerRxWait, 0, "Serial Rx Wait"); BSP_OS_SemCreate(&BSP_SerLock, 1, "Serial Lock"); SYSTEM.PRCR.WORD = 0xA50B; /* Protect off. */ MPC.PWPR.BIT.B0WI = 0; /* Unlock protection register. */ MPC.PWPR.BIT.PFSWE = 1; /* Unlock MPC registers. */ SYSTEM.MSTPCRA.BIT.ACSE = 0; /* clear ACSE Bit (All-Module Clock Stop Mode Enable). */ MSTP(SCI2) = 0; /* Cancel stop state of SCI2 Periph to en wr to it. */ SYSTEM.PRCR.WORD = 0xA500; /* Protect on. */ SCI2.SCR.BYTE = 0x00; /* Clear bits TIE, RIE, RE, and TEIE in SCR to 0 ... */ /* ... Set CKE to internal. */ /* Set up the UART I/O port and pins. */ MPC.P50PFS.BYTE = 0x4A; /* P50 is TxD2. */ MPC.P52PFS.BYTE = 0x4A; /* P52 is RxD2. */ PORT5.PDR.BIT.B0 = 1; /* TxD2 is output. */ PORT5.PDR.BIT.B2 = 0; /* RxD2 is input. */ PORT5.PMR.BIT.B0 = 1; /* TxD2 is peripheral. */ PORT5.PMR.BIT.B2 = 1; /* RxD2 is peripheral. */ IR(SCI2, RXI2) = 0; /* Clear any pending ISR. */ IR(SCI2, TXI2) = 0; IR(SCI2, TEI2) = 0; IPR(SCI2, RXI2) = BSP_CFG_SER_IPL; /* Set interrupt priority. */ IPR(SCI2, TXI2) = BSP_CFG_SER_IPL; IPR(SCI2, TEI2) = BSP_CFG_SER_IPL; IEN(SCI2, RXI2) = 1; /* Enable interrupt source. */ IEN(SCI2, TXI2) = 1; IEN(SCI2, TEI2) = 1; BSP_IntVectSet(VECT_SCI2_RXI2, (CPU_FNCT_VOID)BSP_Ser_ISR_Rx_Handler); BSP_IntVectSet(VECT_SCI2_TXI2, (CPU_FNCT_VOID)BSP_Ser_ISR_Tx_Handler); /* Set data transfer format in Serial Mode Register. */ /* -Asynchronous Mode. */ /* -8 bits. */ /* -no parity. */ /* -1 stop bit. */ /* -PCLK clock (n = 0). */ SCI2.SMR.BYTE = 0x00; SCI2.SCMR.BIT.SMIF = 0; /* Set to 0 for serial communications interface mode. */ baud_clk = 0; /* Algorithm for finding BRR value */ do { /* N = BRR (0-255), B = bit rate, n = baud clock */ brr = BSP_Ser_GetBRR(baud_clk, baud_rate); /* N = Pclk / (64 * 2^(2 * n - 1) * B) - 1 */ if (brr > 255) { baud_clk++; } } while (brr > 255); SCI2.SMR.BIT.CKS = baud_clk; SCI2.BRR = brr; for (i = 0; i < 10000; i++) { /* Wait for at least 1 bit time */ ; } /* Enable RXI and TXI interrupts in SCI peripheral. */ SCI2.SCR.BYTE |= 0x30; }
/******************************************************************************* * Function Name : R_CPG_PLL_Wait * Description : Wait about 100us for PLL stabilization by using CMT0 * Arguments : none * Return Value : none *******************************************************************************/ void R_CPG_PLL_Wait(void) { /* Enables writing to the registers related to Reset and Low-Power function */ r_rst_write_enable(); /* Release from the CMT0 module-stop state */ MSTP(CMT0) = 0; /* Disables writing to the registers related to Reset and Low-Power function */ r_rst_write_disable(); /* Set CMT0 to 100us interval operation */ CMT0.CMCR.BIT.CKS = CPG_CMT0_CLOCK_PCLKD_32; // Count clock = PCLKD/32 CMT0.CMCR.BIT.CMIE = CPG_CMT0_CMI0_ENABLE; // Enable CMI0 interrupt CMT0.CMCNT = CPG_CMT_REG_CLEAR; // Clear CMCNT counter CMT0.CMCOR = CPG_CMT0_CONST_100_us; // Set constant value for 100us /* Set IRQ21(CMI0) for polloing sequence */ VIC.IEC0.BIT.IEC21 = ICU_IEC_MASK_SET; // Mask IRQ21 interrupt VIC.PLS0.BIT.PLS21 = ICU_TYPE_EDGE; // Set EDGE type interrupt VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge /* Enable IRQ interrupt (Clear CPSR.I bit to 0) */ asm("cpsie i"); // Clear CPSR.I bit to 0 asm("isb"); // Ensuring Context-changing /* Start CMT0 count */ CMT.CMSTR0.BIT.STR0 = CPG_CMT0_START; /* Wait for 100us (IRQ21 is generated) */ while ( !(VIC.RAIS0.BIT.RAI21) ) { /* Wait */ } /* Stop CMT0 count */ CMT.CMSTR0.BIT.STR0 = CPG_CMT0_STOP; /* Initialize CMT0 settings and clear interrupt detection edge */ CMT0.CMCR.WORD = CPG_CMT_REG_CLEAR; CMT0.CMCNT = CPG_CMT_REG_CLEAR; CMT0.CMCOR = CPG_CMT_REG_CLEAR; CMT.CMSTR0.WORD = CPG_CMT_REG_CLEAR; VIC.PIC0.BIT.PIC21 = ICU_PIC_EDGE_CLEAR; // Clear interrupt detection edge /* Disable IRQ interrupt (Set CPSR.I bit to 1) */ asm("cpsid i"); asm("isb"); /* Enables writing to the registers related to Reset and Low-Power function */ r_rst_write_enable(); /* Set CMT0 to module-stop state */ MSTP(CMT0) = 1; /* Disables writing to the registers related to Reset and Low-Power function */ r_rst_write_disable(); }
int LCDInit(void) { MPC.P55PFS.BIT.PSEL = 0x18; // Setup P55 for EDREQ0 PORT5.PMR.BIT.B5 = 1; // P55 to peripheral MPC.P54PFS.BIT.PSEL = 0x18; // Setup P54 for EDACK0 PORT5.PMR.BIT.B4 = 1; // P54 to peripheral // Connect MTIOC3C-B to P56 MPC.P56PFS.BIT.PSEL = 0x01; // Setup P56 for MTIOC3C PORT5.PMR.BIT.B6 = 1; // P56 to peripheral // Connect MTIOC0C-A to P34 MPC.P34PFS.BIT.PSEL = 0x01; PORT3.PMR.BIT.B4 = 1; // Enable EXDMA SYSTEM.MSTPCRA.BIT.MSTPA29 /* MSTP_EXDMAC */= 0; // enable MTU 0-5 MSTP(MTU) = 0; // turn on all OE based outputs MTU.TOER.BYTE = 0xFF; // HSYNC //PORT2.PDR.BIT.B0 = 1; // Hsync active low , so set high. //PORT2.PODR.BIT.B0 = 1; // set Hsync to output MPC.P20PFS.BIT.PSEL = 0x01; // Setup P20 for MTIOC1A PORT2.PMR.BIT.B0 = 1; // P20 to peripheral // VSYNC //PORT8.PDR.BIT.B3 = 1; // Vsync active low , so set high //PORT8.PODR.BIT.B3 = 1; // set Vsync to output MPC.P83PFS.BIT.PSEL = 0x01; // Setup P83 for MTIOC4C PORT8.PMR.BIT.B3 = 1; // P83 to peripheral // Set to idle state of DOTCLK PORT5.PDR.BIT.B6 = 1; // Set EDACK2 to output DOTCLK when we're bit banging PORT5.PODR.BIT.B6 = 1; // configure ExDMA MPC.P55PFS.BIT.PSEL = 0x18; // Setup P55 for EDREQ0 PORT5.PMR.BIT.B5 = 1; // P55 to peripheral // stops DMA transfer EXDMAC0.EDMCNT.BIT.DTE = 0; // transfer source: 0=software, 2=external, 3=peripheral EXDMAC0.EDMTMD.BIT.DCTG = 2; // dma size: 0=8bit, 1=16 bit, 2=32bit EXDMAC0.EDMTMD.BIT.SZ = 1; // 0=rising edge, 1=falling edge, 2=low level EXDMAC0.EDMRMD.BIT.DREQS = 2; // transfer mode: 0= normal, 1= repeat, 2= block, 3=cluster EXDMAC0.EDMTMD.BIT.MD = 2; // 1=Allow EDACK to output, 0=Don't output EDACK EXDMAC0.EDMOMD.BIT.DACKE = 1; // sets register to reset state EXDMAC0.EDMAMD.LONG = 0; // single address mode selected EXDMAC0.EDMAMD.BIT.AMS = 1; // single address direction read from EDMSAR EXDMAC0.EDMAMD.BIT.DIR = 0; // 0=block repeat source, 1=block repeat destination, 2=no block repeat EXDMAC0.EDMTMD.BIT.DTS = 2; // start EXDMAC unit EXDMAC.EDMAST.BIT.DMST = 1; // 2=increment source address after each xfer, 3=decrement source address after each xfer #if LCD_FLIP_X EXDMAC0.EDMAMD.BIT.SM = 0x3; // NOTE: Change this to ROTATE panel #else EXDMAC0.EDMAMD.BIT.SM = 0x2; // NOTE: Change this to ROTATE panel #endif { // initialize line list with default values short region; for (region = 0; region < (sizeof(DD_RegionLines) / sizeof(DD_RegionLines[0])); region++) LCDSetLineSource(region, DD_FRAME_HEIGHT, DD_Frames[DD_Frame].raster, DD_FRAME_WIDTH); } //---- // SRAM read timing initial configuration // FRAME_BUS_CYCLES /* BSC.CS7WCR1.BIT.CSRWAIT = (((12000000L) * ((PROCESSOR_OSCILLATOR_FREQUENCY / 12000000L) / 2)) / 12000000L) - 1; BSC.CS7WCR2.BIT.RDON = 1; // required to work properly (At least one wait state for the read assert (RD#)) */ // Stop all LCD_DD channels MTU.TSTR.BYTE &= ~(0xC1); //---- // Configure Vertical SYNC (VSYNC) on MTU4 channel C // VSYNC uses PWM mode 1 MTU4.TMDR.BYTE = 0x02; // Synchronize this channel to HPER! // Configure it so that a clear in another channel // (HPER Sync Clear) will also clear this channel // (TSYR.SYNC bit will be set further below to 1 to make this happen) MTU4.TCR.BYTE = 0x60; // VSYNC starts HIGH, and stays HIGH on match (does not change yet) MTU4.TIORL.BIT.IOC = 0x06; // Set the period timeout... VSYNC pulse is multiples of Hperiod // We'll reset at least after this many clocks if HPER is not // resetting us. // ??? This will occur during the vertical blank periods. MTU4.TGRC = H_DOTS_PER_LINE * NUM_PCLOCKS_PER_DOT - 1; //---- // Configure Vertical Period (VPER) on MTU4 channel D // VPER uses PWM mode 1 MTU4.TMDR.BYTE = 0x02; // Synchronize this channel to HPER! // Configure it so that a clear in another channel // (HPER Sync Clear) will also clear this channel // (TSYR.SYNC bit will be set further below to 1 to make this happen) MTU4.TCR.BYTE = 0x60; // VPER will initially be HIGH, and HIGH on match (nothing happening) // (Later it will be initially LOW and trigger to go HIGH) MTU4.TIORL.BIT.IOD = 0x06; // Vsynch pulse is multiples of Hperiod // ??? What is this value supposed to be? MTU4.TGRD = V_LINES_PULSE; // was 10 //---- // Configure Horizontal Sync (HSYNC) on MTU1 channel A // use PWM mode 1 MTU1.TMDR.BYTE = 0x02; // Synchronize this channel to HPER! // Configure it so that a clear in another channel // (HPER Sync Clear) will also clear this channel // (TSYR.SYNC bit will be set further below to 1 to make this happen) MTU1.TCR.BYTE = 0x60; // HSYNC will initially be LOW, and then go HIGH on match. MTU1.TIOR.BIT.IOA = 0x2; // The HYSNC will wait H_DOT_PULSE pixels/dots before transitioning MTU1.TGRA = H_DOT_PULSE * NUM_PCLOCKS_PER_DOT - 1; //---- // Configure Data Enable on MTU0 channel A which triggers/enables // the ExDMA Request. // Use PWM mode 1 MTU0.TMDR.BYTE = 0x02; // Synchronize this channel to HPER! // Configure it so that a clear in another channel // (HPER Sync Clear) will also clear this channel // (TSYR.SYNC bit will be set further below to 1 to make this happen) MTU0.TCR.BYTE = 0x60; // Since we'll be starting in the vertical blank area, we // won't want any transitions. // Keep the Data Enable line initially high and transition to high // on matches. MTU0.TIORH.BIT.IOA = 0x6; // NOTE: extra -1 is necessary because in controlling the external // MUX we don't want to switch the CLK as it is changing to avoid // causing a potential "glitch" -- Output of MUX needs to be same // before and after. MTU0.TGRA = ((H_DOT_PULSE + H_DOT_BACK_PORCH) * NUM_PCLOCKS_PER_DOT) - 1 - 1; // Keep the Data Enable line high all the time while we are in // the display. // MTU0 channel B MTU0.TIORH.BIT.IOB = 0x6; // Setup the end of the data enable to drop after all the dots // of the display have been processed. MTU0.TGRB = ((H_DOT_PULSE + H_DOT_BACK_PORCH + H_DOT_DISPLAY) * NUM_PCLOCKS_PER_DOT) - 1; // because we're using PWM 1 mode for DOTCLOCK and HSYNC, we need // to phase HDEN 1 cycle earlier...as state change is at END of // DOTCLOCK and HSYNC (not 0 cycle) MTU0.TGRA -= 1; MTU0.TGRB -= 1; //---- // Configure Horizontal Period (HPER) for MTU1 channel B // NOTE: All the above PWM's depend on this one // When it resets, they all reset. // HPER uses PWM mode 1 MTU1.TMDR.BYTE = 0x02; // Set TCR to clear TCNT on match on TGRB (HPER) MTU1.TCR.BYTE = 0x40; // HPER will be HIGH, and then transition to LOW on match MTU1.TIOR.BIT.IOB = 0x5; // Period time is one complete line MTU0.TGRB = H_DOTS_PER_LINE * NUM_PCLOCKS_PER_DOT - 1; //---- // Configure Dot Clock (DOTCLK) & Dot Period (DOTPER) // NOTE: Must be on same channel! // The DOTCLK and DOTPER are used for outputting clocks // when the DMA is not generating the clocks. // They both use PWM mode 1 MTU3.TMDR.BYTE = 0x02; // Set TCR to clear TCNT on TGRD (DOTPER) MTU3.TCR.BYTE = 0xC0; #ifdef DOT_INVERT // DOTCLK will be initially HIGH, then go LOW on transitions MTU3.TIORL.BIT.IOC = 0x5; // DOTPER marks the reset point. // Just go from HIGH back to LOW. MTU3.TIORL.BIT.IOD = 0x6; #else // DOTCLK will be initially LOW, then go HIGH on transitions MTU3.TIORL.BIT.IOC = 0x2; // DOTPER marks the reset point. // Just go from LOW back to HIGH. MTU3.TIORL.BIT.IOD = 0x1; #endif // Set falling edge time to about half of the PCLK clock // cycles of a full dot clock. MTU3.TGRC = ((0.5) * NUM_PCLOCKS_PER_DOT) - 1; // The dot clock period is, well, the number of PCLK's // per dot. Again, minus one because the transition is at // the END. MTU3.TGRD = ((1) * NUM_PCLOCKS_PER_DOT) - 1; //---- // Configure Interrupts. // DD_PixelsLineISR() is called at the end of each data enable period MTU0.TIER.BIT.TGIEB = 1; // Run DD_BlankLineISR() at the end of each Data Enable section MTU0.TIER.BIT.TGIEA = 1; ICU.IPR[IPR_MTU0_TGIA0].BIT.IPR = 14; //ICU.IER[IPR_MTU0_TGIA0].BIT.IEN0 = 1; //ICU.IER[IER_MTU0_TGIA0].BIT.IEN0 = 1; IEN(MTU0, TGIA0) = 1; // Run DD_FrameISR() at start of Vertical Active period (via DOTCLK IRQ) ICU.IPR[IPR_MTU3_TGIC3].BIT.IPR = 14; MTU3.TIER.BIT.TGIEC = 1; //---- // Synchronize MTU4 and MTU0 together so whenever // MTU0.TGRD (HPER) hits, they both reset their counters (TCNT) MTU.TSYR.BYTE = 0x83; //---- // Start all MTU's we're using (MTU4, MTU3, MTU1, and MTU0) MTU.TSTR.BYTE |= 0xC3; // ensure first IRQ starts new frame DD_CurrentLine = 0; // Setup the total number of lines to get 60 Hz. // Found through testing. // To get the desired panel frequency, we have to insert // extra lines into the complete period, effectively creating // a larger time VSYNC period when no data is sent to the display. // This allows the CPU to catch up between frames and do other // processing while keeping a steady frame rate experience. // The formula is as follows: DD_LinesPerPeriod = (V_LINES_PER_FRAME) + EXTRA_LINES_NEEDED(DESIRED_FRAME_RATE); // Do we need to do this here? //IEN(MTU0, TGIB0); //IEN(MTU0, TGIA0); //IEN(MTU3, TGIC3); //ICU.IPR[IPR_MTU0_TGIB0].BIT.IPR = 14; //LCD_Frames_Init(); return 0; }
/****************************************************************************** * Function Name: adc_open * Description : This function applies power to the A/D peripheral, sets the * operational mode, trigger sources, interrupt priority, and * configurations common to all channels and sensors. If interrupt * priority is non-zero, the function takes a callback function * pointer for notifying the user at interrupt level whenever a * scan has completed. * * NOTE: The temperature sensor on the RX210 functionally behaves like a * regular software trigger. But instead of using the ADST bit, it has its * own PGAEN bit. For this bit to work, you must also have TRSA=0x0A, * TRGE=1, MSTP(TEMPS)=0, and TSEN=1. * The ADST bit will work with this configuration and will also work with * just MSTP(TEMPS)=0 and TSEN=1. However, the value read does not include * the temperature sensor gain value. This behavior is not documented in * the HW Manual, and accuracy is unknown. * Because of this, and portability concerns, the driver API is written * to look like the temp sensor runs on a normal software trigger. * * -Gain values will always be read. * -ADST could be used to check for scan complete when using PGAEN. * * Arguments : mode- * Operational mode (see enumeration below) * p_cfg- * Pointer to configuration structure (see below) * p_callback- * Optional pointer to function called from interrupt when * a scan completes * Return Value : ADC_SUCCESS- * Successful * ADC_ERR_AD_LOCKED- * Open() call is in progress elsewhere * ADC_ERR_AD_NOT_CLOSED- * Peripheral is still running in another mode; Perform * R_ADC_Close() first * ADC_ERR_INVALID_ARG- * mode or element of p_cfg structure has invalid value. * ADC_ERR_ILLEGAL_ARG- * an argument is illegal based upon mode * ADC_ERR_MISSING_PTR- * p_cfg pointer is FIT_NO_PTR/NULL *******************************************************************************/ adc_err_t adc_open(adc_mode_t const mode, adc_cfg_t * const p_cfg, void (* const p_callback)(void *p_args)) { #if ADC_CFG_PARAM_CHECKING_ENABLE == 1 if ((p_cfg == NULL) || (p_cfg == FIT_NO_PTR)) { return ADC_ERR_MISSING_PTR; } /* Check for valid argument values */ if ((mode >= ADC_MODE_MAX) || ((p_cfg->trigger >= ADC_TRIG_HW_MAX) && (p_cfg->trigger != ADC_TRIG_SOFTWARE)) || (p_cfg->priority > BSP_MCU_IPL_MAX) || (p_cfg->add_cnt >= ADC_ADD_MAX) || (p_cfg->trigger == ADC_TRIG_PLACEHOLDER) || ((p_cfg->clearing != ADC_CLEAR_AFTER_READ_OFF) && (p_cfg->clearing != ADC_CLEAR_AFTER_READ_ON))) { return ADC_ERR_INVALID_ARG; } /* If interrupt driven, must have callback function */ if ((p_cfg->priority != 0) && ((p_callback == NULL) || (p_callback == FIT_NO_FUNC))) { return ADC_ERR_ILLEGAL_ARG; } if (p_cfg->add_cnt == ADC_ADD_OFF) { /* Check alignment values only if addition is off */ if ((p_cfg->alignment != ADC_ALIGN_LEFT) && (p_cfg->alignment != ADC_ALIGN_RIGHT)) { return ADC_ERR_INVALID_ARG; } } else // addition on { /* Addition not allowed with temperature sensor on RX210 */ if (mode == ADC_MODE_SS_TEMPERATURE) { return ADC_ERR_ILLEGAL_ARG; } } /* For portability, only allow software trigger because that is the functional * behavior of the sensor. Will map to actual "synchronous temperature trigger" * (0x0A) later. */ if ((mode == ADC_MODE_SS_TEMPERATURE) && (p_cfg->trigger != ADC_TRIG_SOFTWARE)) { return ADC_ERR_ILLEGAL_ARG; } /* In double trigger mode, SW and async triggers not allowed */ if ((mode == ADC_MODE_SS_ONE_CH_DBLTRIG) && ((p_cfg->trigger == ADC_TRIG_SOFTWARE) || (p_cfg->trigger == ADC_TRIG_ASYNC_ADTRG0))) { return ADC_ERR_ILLEGAL_ARG; } /* Group checking; only synchronous triggers allowed; must be unique */ if ((mode == ADC_MODE_SS_MULTI_CH_GROUPED) || (mode == ADC_MODE_SS_MULTI_CH_GROUPED_DBLTRIG_A)) { if ((p_cfg->trigger == ADC_TRIG_ASYNC_ADTRG0) || (p_cfg->trigger_groupb == ADC_TRIG_ASYNC_ADTRG0) || (p_cfg->trigger_groupb == ADC_TRIG_PLACEHOLDER) || (p_cfg->trigger == p_cfg->trigger_groupb) || (p_cfg->trigger == ADC_TRIG_SOFTWARE) || (p_cfg->trigger_groupb == ADC_TRIG_SOFTWARE)) { return ADC_ERR_ILLEGAL_ARG; } if ((p_cfg->priority_groupb > BSP_MCU_IPL_MAX) || (p_cfg->trigger >= ADC_TRIG_HW_MAX) || (p_cfg->trigger_groupb >= ADC_TRIG_HW_MAX)) { return ADC_ERR_INVALID_ARG; } if ((p_cfg->priority_groupb != 0) // interrupt driven; must have callback func && ((p_callback == NULL) || (p_callback == FIT_NO_FUNC))) { return ADC_ERR_ILLEGAL_ARG; } } #endif // parameter checking if (g_dcb.opened == true) { return ADC_ERR_AD_NOT_CLOSED; } if (R_BSP_HardwareLock(BSP_LOCK_S12AD) == false) { return ADC_ERR_AD_LOCKED; } /* APPLY POWER TO PERIPHERAL */ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_LPC_CGC_SWR); MSTP(S12AD) = 0; if (mode == ADC_MODE_SS_TEMPERATURE) { MSTP(TEMPS) = 0; } R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_LPC_CGC_SWR); S12AD.ADCSR.WORD = 0; S12AD.ADEXICR.WORD = 0; TEMPS.TSCR.BYTE = 0; /* SET MODE RELATED REGISTER FIELDS */ g_dcb.mode = mode; if ((mode == ADC_MODE_SS_MULTI_CH_GROUPED) || (mode == ADC_MODE_SS_MULTI_CH_GROUPED_DBLTRIG_A)) { S12AD.ADCSR.BIT.ADCS = ADC_ADCS_GROUP_SCAN; } else { if ((mode == ADC_MODE_CONT_ONE_CH) || (mode == ADC_MODE_CONT_MULTI_CH)) { S12AD.ADCSR.BIT.ADCS = ADC_ADCS_CONT_SCAN; } // other modes have ADCS=0 } if ((mode == ADC_MODE_SS_ONE_CH_DBLTRIG) || (mode == ADC_MODE_SS_MULTI_CH_GROUPED_DBLTRIG_A)) { S12AD.ADCSR.BIT.DBLE = 1; // enable double trigger } /* SET TRIGGER AND INTERRUPT PRIORITY REGISTER FIELDS */ if (mode == ADC_MODE_SS_TEMPERATURE) { S12AD.ADSTRGR.BIT.TRSA = 0x0A; // synchronous temperature trigger } if (p_cfg->trigger != ADC_TRIG_SOFTWARE) { S12AD.ADSTRGR.BIT.TRSA = p_cfg->trigger; } if (p_cfg->trigger == ADC_TRIG_ASYNC_ADTRG0) { S12AD.ADCSR.BIT.EXTRG = 1; // set ext trigger for async trigger } if (S12AD.ADCSR.BIT.ADCS == ADC_ADCS_GROUP_SCAN) { S12AD.ADSTRGR.BIT.TRSB = p_cfg->trigger_groupb; IPR(S12AD,GBADI) = p_cfg->priority_groupb; } IPR(S12AD,S12ADI0) = p_cfg->priority; /* SET REGISTER FIELDS FOR REMAINING PARAMETERS */ S12AD.ADADC.BIT.ADC = p_cfg->add_cnt; S12AD.ADCER.WORD = (uint16_t) (p_cfg->alignment | p_cfg->clearing); /* SAVE CALLBACK FUNCTION POINTER */ g_dcb.callback = p_callback; /* MARK DRIVER AS OPENED */ g_dcb.opened = true; R_BSP_HardwareUnlock(BSP_LOCK_S12AD); return ADC_SUCCESS; }
void main(void) { int cnt=0; // ICLK = EXTAL*8 = 12M*8 = 96 MHz. SYSTEM.SCKCR.BIT.ICK = 0; // PCLK = EXTAL*4 = 12M*4 = 48 MHz. SYSTEM.SCKCR.BIT.PCK = 1; // BCLK = EXTAL*2 = 12M*2 = 24 MHz. SYSTEM.SCKCR.BIT.BCK = 2; // Enable BCLK output (high level). SYSTEM.SCKCR.BIT.PSTOP1 = 0; //SYSTEM.SCKCR.LONG = 0x00020100; //Configura puertos. LED0_PDR = 1; LED0 = 0; LED1_PDR = 1; LED1 = 0; LED2_PDR = 1; LED2 = 0; SW1_PDR = 0; //Configura TMR0 // 256 *1/PCLK =256 * 20.8 ns = 5333 ns MSTP(TMR0) = 0; //Activate TMR0 unit IPR(TMR0,OVI0) = 7; //prioridad 2 TMR0.TCCR.BIT.CSS = 1; TMR0.TCCR.BIT.CKS = 6; //48/8192Mhz TMR0.TCR.BIT.CCLR = 1; // ICU.IR[176].BIT.IR = 0; //flag a 0 IEN(TMR0,OVI0) = 1; //enable INT TMR0.TCR.BIT.OVIE = 1; MSTP(MTU1) = 0; //habilita MTU1.TCR.BIT.TPSC = 2 ; //48Mhz PCLK MTU1.TCR.BIT.CKEG = 0 ; //rising edge MTU1.TCR.BIT.CCLR = 1 ; //TGRA MTU1.TGRA = 3225; MTU1.TIER.BIT.TGIEA = 1; // INT ovf IEN(MTU1,TGIA1) = 1; IPR(MTU1,TGIA1) = 2; // prioridad baja IR(MTU1,TGIA1) = 1; // Start TCNT MTUA.TSTR.BIT.CST1 = 1; //start channel 1 //sw1,irq14 SW1_ICR = 1; // Configure falling-edge interrupts on corresponding IRQ's ICU.IRQCR[14].BIT.IRQMD = 1; // Clear IR flags for the IRQ's IR(ICU, IRQ14) = 0; // Set interrupt priority levels IPR(ICU, IRQ14) = 1; // Enable interrupts on the corresponding pins IEN(ICU, IRQ14) = 1; while(1){ delay_ms(100); LED2 ^= 1; }// fin while }//fin main