/** * @brief Configures the different system clocks. * @param None * @retval None */ void RCC_Configuration(void) { /* RCC system reset(for debug purpose) */ RCC_DeInit(); /* Enable HSE */ RCC_HSEConfig(RCC_HSE_ON); /* Wait till HSE is ready */ HSEStartUpStatus = RCC_WaitForHSEStartUp(); if(HSEStartUpStatus == SUCCESS) { /* Enable Prefetch Buffer */ FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); /* Flash 2 wait state */ FLASH_SetLatency(FLASH_Latency_2); /* HCLK = SYSCLK */ RCC_HCLKConfig(RCC_SYSCLK_Div1); /* PCLK2 = HCLK */ RCC_PCLK2Config(RCC_HCLK_Div1); /* PCLK1 = HCLK/2 */ RCC_PCLK1Config(RCC_HCLK_Div2); /* ADCCLK = PCLK2/4 */ RCC_ADCCLKConfig(RCC_PCLK2_Div4); #ifndef STM32F10X_CL /* PLLCLK = 8MHz * 9 = 72 MHz */ RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); #else /* Configure PLLs *********************************************************/ /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ RCC_PREDIV2Config(RCC_PREDIV2_Div5); RCC_PLL2Config(RCC_PLL2Mul_8); /* Enable PLL2 */ RCC_PLL2Cmd(ENABLE); /* Wait till PLL2 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) {} /* PLL configuration: PLLCLK = (PLL2 / 5) * 9 = 72 MHz */ RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div5); RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_9); /* PPL3 configuration: PLL3CLK = (HSE / 5) * 11 = PLL3_VCO = 110 MHz */ RCC_PLL3Config(RCC_PLL3Mul_11); /* Enable PLL3 */ RCC_PLL3Cmd(ENABLE); /* Wait till PLL3 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET) {} /* Configure I2S clock source: On Connectivity-Line Devices, the I2S can be clocked by PLL3 VCO instead of SYS_CLK in order to guarantee higher precision */ RCC_I2S3CLKConfig(RCC_I2S3CLKSource_PLL3_VCO); RCC_I2S2CLKConfig(RCC_I2S2CLKSource_PLL3_VCO); #endif /* Enable PLL */ RCC_PLLCmd(ENABLE); /* Wait till PLL is ready */ while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) { } /* Select PLL as system clock source */ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); /* Wait till PLL is used as system clock source */ while(RCC_GetSYSCLKSource() != 0x08) { } } /* Enable peripheral clocks --------------------------------------------------*/ /* GPIOA, GPIOB and AFIO clocks enable */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_AFIO, ENABLE); #ifdef USE_STM3210C_EVAL /* GPIOC Clock enable (for the SPI3 remapped pins) */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC , ENABLE); #endif /* USE_STM3210C_EVAL */ /* SPI2 and SPI3 clocks enable */ RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2 | RCC_APB1Periph_SPI3, ENABLE); }
/******************************************************************************* * Function Name : Set_System * Description : Configures Main system clocks & power * Input : None. * Return : None. *******************************************************************************/ void Set_System(void) { /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration -----------------------------*/ /* RCC system reset(for debug purpose) */ RCC_DeInit(); /* Enable HSE */ RCC_HSEConfig(RCC_HSE_ON); /* Wait till HSE is ready */ HSEStartUpStatus = RCC_WaitForHSEStartUp(); if (HSEStartUpStatus == SUCCESS) { /* Enable Prefetch Buffer */ FLASH_PrefetchBufferCmd(FLASH_PrefetchBuffer_Enable); /* Flash 2 wait state */ FLASH_SetLatency(FLASH_Latency_2); /* HCLK = SYSCLK */ RCC_HCLKConfig(RCC_SYSCLK_Div1); /* PCLK2 = HCLK */ RCC_PCLK2Config(RCC_HCLK_Div1); /* PCLK1 = HCLK/2 */ RCC_PCLK1Config(RCC_HCLK_Div2); #ifdef STM32F10X_CL /* Configure PLLs *********************************************************/ #ifdef EXTERNAL_CRYSTAL_25MHz /* PLL2 configuration: PLL2CLK = (HSE / 9) * 13 = 36.111 MHz */ RCC_PREDIV2Config(RCC_PREDIV2_Div9); RCC_PLL2Config(RCC_PLL2Mul_13); /* Enable PLL2 */ RCC_PLL2Cmd(ENABLE); /* Wait till PLL2 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) {} /* PPL3 configuration: PLL3CLK = (HSE / 9) * 14 = PLL3_VCO = 77.777 MHz */ RCC_PLL3Config(RCC_PLL3Mul_14); /* Enable PLL3 */ RCC_PLL3Cmd(ENABLE); /* Wait till PLL3 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET) {} /* PLL configuration: PLLCLK = (PLL2 / 4) * 8 = 72.222 MHz */ RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div4); RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_8); #elif defined (EXTERNAL_CRYSTAL_14_7456MHz) /* PLL2 configuration: PLL2CLK = (HSE / 4) * 13 = 47.932 MHz */ RCC_PREDIV2Config(RCC_PREDIV2_Div4); RCC_PLL2Config(RCC_PLL2Mul_13); /* Enable PLL2 */ RCC_PLL2Cmd(ENABLE); /* Wait till PLL2 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL2RDY) == RESET) {} /* PPL3 configuration: PLL3CLK = (HSE / 4) * 20 = PLL3_VCO = 147.456 MHz */ RCC_PLL3Config(RCC_PLL3Mul_20); /* Enable PLL3 */ RCC_PLL3Cmd(ENABLE); /* Wait till PLL3 is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET) {} /* PPL1 configuration: PLL1CLK = (PLL2 / 4) * 6 = 71.8848 MHz */ RCC_PREDIV1Config(RCC_PREDIV1_Source_PLL2, RCC_PREDIV1_Div4); RCC_PLLConfig(RCC_PLLSource_PREDIV1, RCC_PLLMul_6); #endif /* EXTERNAL_CRYSTAL_25MHz */ /* Configure I2S clock source: PLL3 VCO clock */ RCC_I2S2CLKConfig(RCC_I2S2CLKSource_PLL3_VCO); #else /* PLLCLK = 8MHz * 9 = 72 MHz */ RCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9); #endif /* STM32F10X_CL */ /* Enable PLL */ RCC_PLLCmd(ENABLE); /* Wait till PLL is ready */ while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET) { } /* Select PLL as system clock source */ RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK); /* Wait till PLL is used as system clock source */ while(RCC_GetSYSCLKSource() != 0x08) { } } else { /* If HSE fails to start-up, the application will have wrong clock configuration. User can add here some code to deal with this error */ /* Go to infinite loop */ while (1) { } } }