/*-------------------------------------------------------------------*/ void Map48_Init() { int nPage; /* Initialize Mapper */ MapperInit = Map48_Init; /* Write to Mapper */ MapperWrite = Map48_Write; /* Write to SRAM */ MapperSram = Map0_Sram; /* Write to APU */ MapperApu = Map0_Apu; /* Read from APU */ MapperReadApu = Map0_ReadApu; /* Callback at VSync */ MapperVSync = Map0_VSync; /* Callback at HSync */ MapperHSync = Map48_HSync; /* Callback at PPU */ MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ SRAMBANK = SRAM; /* Set ROM Banks */ ROMBANK0 = ROMPAGE( 0 ); ROMBANK1 = ROMPAGE( 1 ); ROMBANK2 = ROMLASTPAGE( 1 ); ROMBANK3 = ROMLASTPAGE( 0 ); /* Set PPU Banks */ if ( NesHeader.byVRomSize > 0 ) { for ( nPage = 0; nPage < 8; ++nPage ) PPUBANK[ nPage ] = VROMPAGE( nPage ); InfoNES_SetupChr(); } /* Initialize IRQ Registers */ Map48_Regs[ 0 ] = 0; Map48_IRQ_Enable = 0; Map48_IRQ_Cnt = 0; /* Set up wiring of the interrupt pin */ K6502_Set_Int_Wiring( 1, 1 ); }
/*-------------------------------------------------------------------*/ void Map230_Init() { /* Initialize Mapper */ MapperInit = Map230_Init; /* Write to Mapper */ MapperWrite = Map230_Write; /* Write to SRAM */ MapperSram = Map0_Sram; /* Write to APU */ MapperApu = Map0_Apu; /* Read from APU */ MapperReadApu = Map0_ReadApu; /* Callback at VSync */ MapperVSync = Map0_VSync; /* Callback at HSync */ MapperHSync = Map0_HSync; /* Callback at PPU */ MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ SRAMBANK = SRAM; /* Initialize Registers */ if( Map230_RomSw ) { Map230_RomSw = 0; } else { Map230_RomSw = 1; } /* Set ROM Banks */ if( Map230_RomSw ) { ROMBANK0 = ROMPAGE( 0 ); ROMBANK1 = ROMPAGE( 1 ); ROMBANK2 = ROMPAGE( 14 ); ROMBANK3 = ROMPAGE( 15 ); } else { ROMBANK0 = ROMPAGE( 16 ); ROMBANK1 = ROMPAGE( 17 ); ROMBANK2 = ROMLASTPAGE( 1 ); ROMBANK3 = ROMLASTPAGE( 0 ); } /* Set up wiring of the interrupt pin */ K6502_Set_Int_Wiring( 1, 1 ); }
/*-------------------------------------------------------------------*/ void Map91_Init() { /* Initialize Mapper */ MapperInit = Map91_Init; /* Write to Mapper */ MapperWrite = Map0_Write; /* Write to SRAM */ MapperSram = Map91_Sram; /* Write to APU */ MapperApu = Map0_Apu; /* Read from APU */ MapperReadApu = Map0_ReadApu; /* Callback at VSync */ MapperVSync = Map0_VSync; /* Callback at HSync */ MapperHSync = Map0_HSync; /* Callback at PPU */ MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ W.SRAMBANK = S.SRAM; /* Set ROM Banks */ W.ROMBANK0 = ROMLASTPAGE( 1 ); W.ROMBANK1 = ROMLASTPAGE( 0 ); W.ROMBANK2 = ROMLASTPAGE( 1 ); W.ROMBANK3 = ROMLASTPAGE( 0 ); /* Set PPU Banks */ if ( S.NesHeader.VROMSize > 0 ) { int nPage ; for (nPage = 0; nPage < 8; ++nPage ) W.PPUBANK[ nPage ] = VROMPAGE( nPage ); NESCore_Develop_Character_Data(); } /* Set Name Table Mirroring */ NESCore_Mirroring( 1 ); }
/*-------------------------------------------------------------------*/ void Map188_Init() { /* Initialize Mapper */ MapperInit = Map188_Init; /* Write to Mapper */ MapperWrite = Map188_Write; /* Write to SRAM */ MapperSram = Map0_Sram; /* Write to APU */ MapperApu = Map0_Apu; /* Read from APU */ MapperReadApu = Map0_ReadApu; /* Callback at VSync */ MapperVSync = Map0_VSync; /* Callback at HSync */ MapperHSync = Map0_HSync; /* Callback at PPU */ MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ SRAMBANK = Map188_Dummy; /* Set ROM Banks */ if ( ( NesHeader.byRomSize << 1 ) > 16 ) { ROMBANK0 = ROMPAGE( 0 ); ROMBANK1 = ROMPAGE( 1 ); ROMBANK2 = ROMPAGE( 14 ); ROMBANK3 = ROMPAGE( 15 ); } else { ROMBANK0 = ROMPAGE( 0 ); ROMBANK1 = ROMPAGE( 1 ); ROMBANK2 = ROMLASTPAGE( 1 ); ROMBANK3 = ROMLASTPAGE( 0 ); } /* Magic Code */ Map188_Dummy[ 0 ] = 0x03; /* Set up wiring of the interrupt pin */ K6502_Set_Int_Wiring( 1, 1 ); }
/*-------------------------------------------------------------------*/ void Map18_Init() { /* Initialize Mapper */ MapperInit = Map18_Init; /* Write to Mapper */ MapperWrite = Map18_Write; /* Write to SRAM */ MapperSram = Map0_Sram; /* Write to APU */ MapperApu = Map0_Apu; /* Read from APU */ MapperReadApu = Map0_ReadApu; /* Callback at VSync */ MapperVSync = Map0_VSync; /* Callback at HSync */ MapperHSync = Map18_HSync; /* Callback at PPU */ MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ SRAMBANK = SRAM; /* Set ROM Banks */ ROMBANK0 = ROMPAGE( 0 ); ROMBANK1 = ROMPAGE( 1 ); ROMBANK2 = ROMLASTPAGE( 1 ); ROMBANK3 = ROMLASTPAGE( 0 ); /* Initialize Regs */ int i ; for (i = 0; i < sizeof( Map18_Regs ); i++ ) { Map18_Regs[ i ] = 0; } Map18_IRQ_Enable = 0; Map18_IRQ_Latch = 0; Map18_IRQ_Cnt = 0; /* Set up wiring of the interrupt pin */ K6502_Set_Int_Wiring( 1, 1 ); }
/*-------------------------------------------------------------------*/ void Map248_Set_CPU_Banks() { if( Map248_Reg[0] & 0x40 ) { ROMBANK0 = ROMLASTPAGE( 1 ); ROMBANK1 = ROMPAGE(Map248_Prg1 % (NesHeader.byRomSize<<1)); ROMBANK2 = ROMPAGE(Map248_Prg0 % (NesHeader.byRomSize<<1)); ROMBANK3 = ROMLASTPAGE( 0 ); } else { ROMBANK0 = ROMPAGE(Map248_Prg0 % (NesHeader.byRomSize<<1)); ROMBANK1 = ROMPAGE(Map248_Prg1 % (NesHeader.byRomSize<<1)); ROMBANK2 = ROMLASTPAGE( 1 ); ROMBANK3 = ROMLASTPAGE( 0 ); } }
/*-------------------------------------------------------------------*/ void Map248_Set_CPU_Banks() { if( Map248_Reg[0] & 0x40 ) { W.ROMBANK0 = ROMLASTPAGE( 1 ); W.ROMBANK1 = ROMPAGE(Map248_Prg1 % (S.NesHeader.ROMSize<<1)); W.ROMBANK2 = ROMPAGE(Map248_Prg0 % (S.NesHeader.ROMSize<<1)); W.ROMBANK3 = ROMLASTPAGE( 0 ); } else { W.ROMBANK0 = ROMPAGE(Map248_Prg0 % (S.NesHeader.ROMSize<<1)); W.ROMBANK1 = ROMPAGE(Map248_Prg1 % (S.NesHeader.ROMSize<<1)); W.ROMBANK2 = ROMLASTPAGE( 1 ); W.ROMBANK3 = ROMLASTPAGE( 0 ); } }
/*-------------------------------------------------------------------*/ void Map251_Init() { /* Initialize Mapper */ MapperInit = Map251_Init; /* Write to Mapper */ MapperWrite = Map251_Write; /* Write to SRAM */ MapperSram = Map251_Sram; /* Write to APU */ MapperApu = Map0_Apu; /* Read from APU */ MapperReadApu = Map0_ReadApu; /* Callback at VSync */ MapperVSync = Map0_VSync; /* Callback at HSync */ MapperHSync = Map0_HSync; /* Callback at PPU */ MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ SRAMBANK = SRAM; /* Set ROM Banks */ ROMBANK0 = ROMPAGE( 0 ); ROMBANK1 = ROMPAGE( 1 ); ROMBANK2 = ROMLASTPAGE( 1 ); ROMBANK3 = ROMLASTPAGE( 0 ); /* Set Registers */ InfoNES_Mirroring( 1 ); int i; for( i = 0; i < 11; i++ ) Map251_Reg[i] = 0; for( i = 0; i < 4; i++ ) Map251_Breg[i] = 0; /* Set up wiring of the interrupt pin */ K6502_Set_Int_Wiring( 1, 1 ); }
/*-------------------------------------------------------------------*/ void Map114_Set_CPU_Banks() { if ( Map114_Prg_Swap() ) { ROMBANK0 = ROMLASTPAGE( 1 ); ROMBANK1 = ROMPAGE( Map114_Prg1 % ( NesHeader.byRomSize << 1 ) ); ROMBANK2 = ROMPAGE( Map114_Prg0 % ( NesHeader.byRomSize << 1 ) ); ROMBANK3 = ROMLASTPAGE( 0 ); } else { ROMBANK0 = ROMPAGE( Map114_Prg0 % ( NesHeader.byRomSize << 1 ) ); ROMBANK1 = ROMPAGE( Map114_Prg1 % ( NesHeader.byRomSize << 1 ) ); ROMBANK2 = ROMLASTPAGE( 1 ); ROMBANK3 = ROMLASTPAGE( 0 ); } }
void Map4_Set_CPU_Banks() { if (Map4_Prg_Swap()) { W.ROMBANK0 = ROMLASTPAGE( 1 ); W.ROMBANK1 = ROMPAGE( MS4.Prg1 % ( S.NesHeader.ROMSize << 1 ) ); W.ROMBANK2 = ROMPAGE( MS4.Prg0 % ( S.NesHeader.ROMSize << 1 ) ); W.ROMBANK3 = ROMLASTPAGE( 0 ); } else { W.ROMBANK0 = ROMPAGE( MS4.Prg0 % ( S.NesHeader.ROMSize << 1 ) ); W.ROMBANK1 = ROMPAGE( MS4.Prg1 % ( S.NesHeader.ROMSize << 1 ) ); W.ROMBANK2 = ROMLASTPAGE( 1 ); W.ROMBANK3 = ROMLASTPAGE( 0 ); } }
/*-------------------------------------------------------------------*/ void Map232_Init() { /* Initialize Mapper */ MapperInit = Map232_Init; /* Write to Mapper */ MapperWrite = Map232_Write; /* Write to SRAM */ MapperSram = Map0_Sram; /* Write to APU */ MapperApu = Map0_Apu; /* Read from APU */ MapperReadApu = Map0_ReadApu; /* Callback at VSync */ MapperVSync = Map0_VSync; /* Callback at HSync */ MapperHSync = Map0_HSync; /* Callback at PPU */ MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ W.SRAMBANK = S.SRAM; /* Set ROM Banks */ W.ROMBANK0 = ROMPAGE( 0 ); W.ROMBANK1 = ROMPAGE( 1 ); W.ROMBANK2 = ROMLASTPAGE( 1 ); W.ROMBANK3 = ROMLASTPAGE( 0 ); /* Initialize Registers */ Map232_Regs[0] = 0x0C; Map232_Regs[1] = 0x00; }
void Map33_Init() { MapperInit = Map33_Init; MapperWrite = Map33_Write; MapperSram = Map0_Sram; MapperApu = Map0_Apu; MapperReadApu = Map0_ReadApu; MapperVSync = Map0_VSync; MapperHSync = Map0_HSync; MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; W.SRAMBANK = S.SRAM; W.ROMBANK0 = ROMPAGE( 0 ); W.ROMBANK1 = ROMPAGE( 1 ); W.ROMBANK2 = ROMLASTPAGE( 1 ); W.ROMBANK3 = ROMLASTPAGE( 0 ); /* Set PPU Banks */ if ( S.NesHeader.VROMSize > 0 ) { int nPage ; for (nPage = 0; nPage < 8; ++nPage ) { W.PPUBANK[ nPage ] = VROMPAGE( nPage ); Map33_Regs[ nPage ] = nPage; } NESCore_Develop_Character_Data(); } else { int nPage ; for (nPage = 0; nPage < 8; ++nPage ) Map33_Regs[ nPage ] = 0; } Map33_Switch = 0; Map33_IRQ_Enable = 0; Map33_IRQ_Cnt = 0; }
void Map24_Init() { MapperInit = Map24_Init; MapperWrite = Map24_Write; MapperSram = Map0_Sram; MapperApu = Map0_Apu; MapperReadApu = Map0_ReadApu; MapperVSync = Map0_VSync; MapperHSync = Map24_HSync; MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; W.SRAMBANK = S.SRAM; W.ROMBANK0 = ROMPAGE( 0 ); W.ROMBANK1 = ROMPAGE( 1 ); W.ROMBANK2 = ROMLASTPAGE( 1 ); W.ROMBANK3 = ROMLASTPAGE( 0 ); }
void Map71_Init() { MapperInit = Map71_Init; MapperWrite = Map71_Write; MapperSram = Map0_Sram; MapperApu = Map0_Apu; MapperReadApu = Map0_ReadApu; MapperVSync = Map0_VSync; MapperHSync = Map0_HSync; MapperPPU = Map0_PPU; MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ W.SRAMBANK = S.SRAM; /* Set ROM Banks */ W.ROMBANK0 = ROMPAGE( 0 ); W.ROMBANK1 = ROMPAGE( 1 ); W.ROMBANK2 = ROMLASTPAGE( 1 ); W.ROMBANK3 = ROMLASTPAGE( 0 ); }
void Map10_Init() { int nPage; MapperInit = Map10_Init; MapperWrite = Map10_Write; MapperSram = Map0_Sram; MapperApu = Map0_Apu; MapperReadApu = Map0_ReadApu; MapperVSync = Map0_VSync; MapperHSync = Map0_HSync; MapperPPU = Map10_PPU; MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ W.SRAMBANK = S.SRAM; W.ROMBANK0 = ROMPAGE( 0 ); W.ROMBANK1 = ROMPAGE( 1 ); W.ROMBANK2 = ROMLASTPAGE( 1 ); W.ROMBANK3 = ROMLASTPAGE( 0 ); /* Set PPU Banks */ if ( S.NesHeader.VROMSize > 0 ) { for ( nPage = 0; nPage < 8; ++nPage ) W.PPUBANK[ nPage ] = VROMPAGE( nPage ); NESCore_Develop_Character_Data(); } /* Init Latch Selector */ latch3.state = 0xfe; latch3.lo_bank = 0; latch3.hi_bank = 0; latch4.state = 0xfe; latch4.lo_bank = 0; latch4.hi_bank = 0; }
void Map67_Init() { MapperInit = Map67_Init; MapperWrite = Map67_Write; MapperSram = Map0_Sram; MapperApu = Map0_Apu; MapperReadApu = Map0_ReadApu; MapperVSync = Map0_VSync; MapperHSync = Map67_HSync; MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; W.SRAMBANK = S.SRAM; W.ROMBANK0 = ROMPAGE( 0 ); W.ROMBANK1 = ROMPAGE( 1 ); W.ROMBANK2 = ROMLASTPAGE( 1 ); W.ROMBANK3 = ROMLASTPAGE( 0 ); /* Set PPU Banks */ W.PPUBANK[ 0 ] = VROMPAGE( 0 ); W.PPUBANK[ 1 ] = VROMPAGE( 1 ); W.PPUBANK[ 2 ] = VROMPAGE( 2 ); W.PPUBANK[ 3 ] = VROMPAGE( 3 ); W.PPUBANK[ 4 ] = VROMPAGE( ( S.NesHeader.VROMSize << 3 ) - 4 ); W.PPUBANK[ 5 ] = VROMPAGE( ( S.NesHeader.VROMSize << 3 ) - 3 ); W.PPUBANK[ 6 ] = VROMPAGE( ( S.NesHeader.VROMSize << 3 ) - 2 ); W.PPUBANK[ 7 ] = VROMPAGE( ( S.NesHeader.VROMSize << 3 ) - 1 ); NESCore_Develop_Character_Data(); /* Initialize IRQ Registers */ Map67_IRQ_Enable = 0; Map67_IRQ_Cnt = 0; Map67_IRQ_Latch = 0; }
/*-------------------------------------------------------------------*/ void Map90_Sync_Prg_Banks( void ) { switch ( Map90_Prg_Bank_Size ) { case 0: ROMBANK0 = ROMLASTPAGE( 3 ); ROMBANK1 = ROMLASTPAGE( 2 ); ROMBANK2 = ROMLASTPAGE( 1 ); ROMBANK3 = ROMLASTPAGE( 0 ); break; case 1: ROMBANK0 = ROMPAGE( ( ( Map90_Prg_Reg[ 1 ] << 1 ) + 0 ) % ( NesHeader.byRomSize << 1 ) ); ROMBANK1 = ROMPAGE( ( ( Map90_Prg_Reg[ 1 ] << 1 ) + 1 ) % ( NesHeader.byRomSize << 1 ) ); ROMBANK2 = ROMLASTPAGE( 1 ); ROMBANK3 = ROMLASTPAGE( 0 ); break; case 2: if ( Map90_Prg_Bank_E000 ) { ROMBANK0 = ROMPAGE( Map90_Prg_Reg[ 0 ] % ( NesHeader.byRomSize << 1 ) ); ROMBANK1 = ROMPAGE( Map90_Prg_Reg[ 1 ] % ( NesHeader.byRomSize << 1 ) ); ROMBANK2 = ROMPAGE( Map90_Prg_Reg[ 2 ] % ( NesHeader.byRomSize << 1 ) ); ROMBANK3 = ROMPAGE( Map90_Prg_Reg[ 3 ] % ( NesHeader.byRomSize << 1 ) ); } else { if ( Map90_Prg_Bank_6000 ) { SRAMBANK = ROMPAGE( Map90_Prg_Reg[ 3 ] % ( NesHeader.byRomSize << 1 ) ); } ROMBANK0 = ROMPAGE( Map90_Prg_Reg[ 0 ] % ( NesHeader.byRomSize << 1 ) ); ROMBANK1 = ROMPAGE( Map90_Prg_Reg[ 1 ] % ( NesHeader.byRomSize << 1 ) ); ROMBANK2 = ROMPAGE( Map90_Prg_Reg[ 2 ] % ( NesHeader.byRomSize << 1 ) ); ROMBANK3 = ROMLASTPAGE( 0 ); } break; default: /* 8k in reverse mode? */ ROMBANK0 = ROMPAGE( Map90_Prg_Reg[ 3 ] % ( NesHeader.byRomSize << 1 ) ); ROMBANK1 = ROMPAGE( Map90_Prg_Reg[ 2 ] % ( NesHeader.byRomSize << 1 ) ); ROMBANK2 = ROMPAGE( Map90_Prg_Reg[ 1 ] % ( NesHeader.byRomSize << 1 ) ); ROMBANK3 = ROMPAGE( Map90_Prg_Reg[ 0 ] % ( NesHeader.byRomSize << 1 ) ); break; } }
/*-------------------------------------------------------------------*/ void Map83_Init() { /* Initialize Mapper */ MapperInit = Map83_Init; /* Write to Mapper */ MapperWrite = Map83_Write; /* Write to SRAM */ MapperSram = Map0_Sram; /* Write to APU */ MapperApu = Map83_Apu; /* Read from APU */ MapperReadApu = Map83_ReadApu; /* Callback at VSync */ MapperVSync = Map0_VSync; /* Callback at HSync */ MapperHSync = Map83_HSync; /* Callback at PPU */ MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ W.SRAMBANK = S.SRAM; /* Initialize Registers */ Map83_Regs[0] = Map83_Regs[1] = Map83_Regs[2] = 0; /* Set ROM Banks */ if ( ( S.NesHeader.ROMSize << 1 ) >= 32 ) { W.ROMBANK0 = ROMPAGE( 0 ); W.ROMBANK1 = ROMPAGE( 1 ); W.ROMBANK2 = ROMPAGE( 30 ); W.ROMBANK3 = ROMPAGE( 31 ); Map83_Regs[1] = 0x30; } else { W.ROMBANK0 = ROMPAGE( 0 ); W.ROMBANK1 = ROMPAGE( 1 ); W.ROMBANK2 = ROMLASTPAGE( 1 ); W.ROMBANK3 = ROMLASTPAGE( 0 ); } /* Set PPU Banks */ if ( S.NesHeader.VROMSize > 0 ) { int nPage ; for (nPage = 0; nPage < 8; ++nPage ) W.PPUBANK[nPage] = VROMPAGE( nPage ); NESCore_Develop_Character_Data(); } /* Initialize IRQ Registers */ Map83_IRQ_Enabled = 0; Map83_IRQ_Cnt = 0; Map83_Chr_Bank = 0; }
/*-------------------------------------------------------------------*/ void Map90_Init() { int nPage; BYTE byPage; /* Initialize Mapper */ MapperInit = Map90_Init; /* Write to Mapper */ MapperWrite = Map90_Write; /* Write to SRAM */ MapperSram = Map0_Sram; /* Write to APU */ MapperApu = Map90_Apu; /* Read from APU */ MapperReadApu = Map90_ReadApu; /* Callback at VSync */ MapperVSync = Map0_VSync; /* Callback at HSync */ MapperHSync = Map90_HSync; /* Callback at PPU */ MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ SRAMBANK = SRAM; /* Set ROM Banks */ ROMBANK0 = ROMLASTPAGE( 3 ); ROMBANK1 = ROMLASTPAGE( 2 ); ROMBANK2 = ROMLASTPAGE( 1 ); ROMBANK3 = ROMLASTPAGE( 0 ); /* Set PPU Banks */ if ( NesHeader.byVRomSize > 0 ) { for ( nPage = 0; nPage < 8; ++nPage ) PPUBANK[ nPage ] = VROMPAGE( nPage ); InfoNES_SetupChr(); } /* Initialize IRQ Registers */ Map90_IRQ_Cnt = 0; Map90_IRQ_Latch = 0; Map90_IRQ_Enable = 0; for ( byPage = 0; byPage < 4; byPage++ ) { Map90_Prg_Reg[ byPage ] = ( NesHeader.byRomSize << 1 ) - 4 + byPage; Map90_Nam_Low_Reg[ byPage ] = 0; Map90_Nam_High_Reg[ byPage ] = 0; Map90_Chr_Low_Reg[ byPage ] = byPage; Map90_Chr_High_Reg[ byPage ] = 0; Map90_Chr_Low_Reg[ byPage + 4 ] = byPage + 4; Map90_Chr_High_Reg[ byPage + 4 ] = 0; } /* Set up wiring of the interrupt pin */ K6502_Set_Int_Wiring( 1, 1 ); }
/*-------------------------------------------------------------------*/ void Map19_Init() { /* Initialize Mapper */ MapperInit = Map19_Init; /* Write to Mapper */ MapperWrite = Map19_Write; /* Write to SRAM */ MapperSram = Map0_Sram; /* Write to APU */ MapperApu = Map19_Apu; /* Read from APU */ MapperReadApu = Map19_ReadApu; /* Callback at VSync */ MapperVSync = Map0_VSync; /* Callback at HSync */ MapperHSync = Map19_HSync; /* Callback at PPU */ MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ SRAMBANK = SRAM; /* Set ROM Banks */ ROMBANK0 = ROMPAGE( 0 ); ROMBANK1 = ROMPAGE( 1 ); ROMBANK2 = ROMLASTPAGE( 1 ); ROMBANK3 = ROMLASTPAGE( 0 ); /* Set PPU Banks */ if ( NesHeader.byVRomSize > 0 ) { DWORD dwLastPage = (DWORD)NesHeader.byVRomSize << 3; PPUBANK[ 0 ] = VROMPAGE( dwLastPage - 8 ); PPUBANK[ 1 ] = VROMPAGE( dwLastPage - 7 ); PPUBANK[ 2 ] = VROMPAGE( dwLastPage - 6 ); PPUBANK[ 3 ] = VROMPAGE( dwLastPage - 5 ); PPUBANK[ 4 ] = VROMPAGE( dwLastPage - 4 ); PPUBANK[ 5 ] = VROMPAGE( dwLastPage - 3 ); PPUBANK[ 6 ] = VROMPAGE( dwLastPage - 2 ); PPUBANK[ 7 ] = VROMPAGE( dwLastPage - 1 ); InfoNES_SetupChr(); } /* Initialize State Register */ Map19_Regs[ 0 ] = 0x00; Map19_Regs[ 1 ] = 0x00; Map19_Regs[ 2 ] = 0x00; /* Set up wiring of the interrupt pin */ K6502_Set_Int_Wiring( 1, 1 ); }
/*-------------------------------------------------------------------*/ void Map100_Init() { /* Initialize Mapper */ MapperInit = Map100_Init; /* Write to Mapper */ MapperWrite = Map100_Write; /* Write to SRAM */ MapperSram = Map0_Sram; /* Write to APU */ MapperApu = Map0_Apu; /* Read from APU */ MapperReadApu = Map0_ReadApu; /* Callback at VSync */ MapperVSync = Map0_VSync; /* Callback at HSync */ MapperHSync = Map100_HSync; /* Callback at PPU */ MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ SRAMBANK = SRAM; /* Set ROM Banks */ ROMBANK0 = ROMPAGE( 0 ); ROMBANK1 = ROMPAGE( 1 ); ROMBANK2 = ROMLASTPAGE( 1 ); ROMBANK3 = ROMLASTPAGE( 0 ); /* Set PPU Banks */ if ( NesHeader.byVRomSize > 0 ) { Map100_Chr0 = 0; Map100_Chr1 = 1; Map100_Chr2 = 2; Map100_Chr3 = 3; Map100_Chr4 = 4; Map100_Chr5 = 5; Map100_Chr6 = 6; Map100_Chr7 = 7; Map100_Set_PPU_Banks(); } else { Map100_Chr0 = Map100_Chr2 = Map100_Chr4 = Map100_Chr5 = Map100_Chr6 = Map100_Chr7 = 0; Map100_Chr1 = Map100_Chr3 = 1; } /* Set IRQ Registers */ Map100_IRQ_Enable = 0; Map100_IRQ_Cnt = 0; Map100_IRQ_Latch = 0; for( int i = 0; i < 8; i++ ) { Map100_Reg[ i ] = 0x00; } /* Set up wiring of the interrupt pin */ K6502_Set_Int_Wiring( 1, 1 ); }
/*-------------------------------------------------------------------*/ void Map249_Init() { /* Initialize Mapper */ MapperInit = Map249_Init; /* Write to Mapper */ MapperWrite = Map249_Write; /* Write to SRAM */ MapperSram = Map0_Sram; /* Write to APU */ MapperApu = Map249_Apu; /* Read from APU */ MapperReadApu = Map0_ReadApu; /* Callback at VSync */ MapperVSync = Map0_VSync; /* Callback at HSync */ MapperHSync = Map249_HSync; /* Callback at PPU */ MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ W.SRAMBANK = S.SRAM; /* Set Registers */ int i ; for (i = 0; i < 8; i++ ) { Map249_Reg[i] = 0x00; } /* Set ROM Banks */ W.ROMBANK0 = ROMPAGE( 0 ); W.ROMBANK1 = ROMPAGE( 1 ); W.ROMBANK2 = ROMLASTPAGE( 1 ); W.ROMBANK3 = ROMLASTPAGE( 0 ); /* Set PPU Banks */ if ( S.NesHeader.VROMSize > 0 ) { int nPage ; for (nPage = 0; nPage < 8; ++nPage ) W.PPUBANK[ nPage ] = VROMPAGE( nPage ); NESCore_Develop_Character_Data(); } /* Set Registers */ Map249_IRQ_Enable = 0; // Disable Map249_IRQ_Counter = 0; Map249_IRQ_Latch = 0; Map249_IRQ_Request = 0; Map249_Spdata = 0; }
/*-------------------------------------------------------------------*/ void Map245_Init() { /* Initialize Mapper */ MapperInit = Map245_Init; /* Write to Mapper */ MapperWrite = Map245_Write; /* Write to SRAM */ MapperSram = Map0_Sram; /* Write to APU */ MapperApu = Map0_Apu; /* Read from APU */ MapperReadApu = Map0_ReadApu; /* Callback at VSync */ MapperVSync = Map0_VSync; /* Callback at HSync */ MapperHSync = Map245_HSync; /* Callback at PPU */ MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map0_RenderScreen; /* Set SRAM Banks */ SRAMBANK = SRAM; /* Set Registers */ int i ; for (i = 0; i < 8; i++ ) { Map245_Reg[i] = 0x00; } Map245_Prg0 = 0; Map245_Prg1 = 1; /* Set ROM Banks */ ROMBANK0 = ROMPAGE( 0 ); ROMBANK1 = ROMPAGE( 1 ); ROMBANK2 = ROMLASTPAGE( 1 ); ROMBANK3 = ROMLASTPAGE( 0 ); /* Set PPU Banks */ if ( NesHeader.byVRomSize > 0 ) { int nPage ; for (nPage = 0; nPage < 8; ++nPage ) PPUBANK[ nPage ] = VROMPAGE( nPage ); InfoNES_SetupChr(); } Map245_WeSram = 0; // Disable Map245_IRQ_Enable = 0; // Disable Map245_IRQ_Counter = 0; Map245_IRQ_Latch = 0; Map245_IRQ_Request = 0; /* Set up wiring of the interrupt pin */ K6502_Set_Int_Wiring( 1, 1 ); }
/*-------------------------------------------------------------------*/ void Map5_Init() { int nPage; /* Initialize Mapper */ MapperInit = Map5_Init; /* Write to Mapper */ MapperWrite = Map5_Write; /* Write to SRAM */ MapperSram = Map0_Sram; /* Write to APU */ MapperApu = Map5_Apu; /* Read from APU */ MapperReadApu = Map5_ReadApu; /* Callback at VSync */ MapperVSync = Map0_VSync; /* Callback at HSync */ MapperHSync = Map5_HSync; /* Callback at PPU */ MapperPPU = Map0_PPU; /* Callback at Rendering Screen ( 1:BG, 0:Sprite ) */ MapperRenderScreen = Map5_RenderScreen; /* Set SRAM Banks */ SRAMBANK = SRAM; /* Set ROM Banks */ ROMBANK0 = ROMLASTPAGE( 0 ); ROMBANK1 = ROMLASTPAGE( 0 ); ROMBANK2 = ROMLASTPAGE( 0 ); ROMBANK3 = ROMLASTPAGE( 0 ); /* Set PPU Banks */ for ( nPage = 0; nPage < 8; ++nPage ) PPUBANK[ nPage ] = VROMPAGE( nPage ); InfoNES_SetupChr(); /* Initialize State Registers */ for ( nPage = 4; nPage < 8; ++nPage ) { Map5_Prg_Reg[ nPage ] = ( NesHeader.byRomSize << 1 ) - 1; Map5_Wram_Reg[ nPage ] = 0xff; } Map5_Wram_Reg[ 3 ] = 0xff; for ( BYTE byPage = 4; byPage < 8; ++byPage ) { Map5_Chr_Reg[ byPage ][ 0 ] = byPage; Map5_Chr_Reg[ byPage ][ 1 ] = ( byPage & 0x03 ) + 4; } InfoNES_MemorySet( Map5_Wram, 0x00, sizeof( Map5_Wram ) ); InfoNES_MemorySet( Map5_Ex_Ram, 0x00, sizeof( Map5_Ex_Ram ) ); InfoNES_MemorySet( Map5_Ex_Vram, 0x00, sizeof( Map5_Ex_Vram ) ); InfoNES_MemorySet( Map5_Ex_Nam, 0x00, sizeof( Map5_Ex_Nam ) ); Map5_Prg_Size = 3; Map5_Wram_Protect0 = 0; Map5_Wram_Protect1 = 0; Map5_Chr_Size = 3; Map5_Gfx_Mode = 0; Map5_IRQ_Enable = 0; Map5_IRQ_Status = 0; Map5_IRQ_Line = 0; /* Set up wiring of the interrupt pin */ K6502_Set_Int_Wiring( 1, 1 ); }