/******************************************************************************* * 名 称: TIM4_Config * 功 能: 配置TIM4,为定时中断10ms, 频率100Hz * 入口参数: 无 * 出口参数: 无 * 作 者: Roger-WY * 创建日期: 2014-08-20 * 修 改: * 修改日期: * 备 注: *******************************************************************************/ static void TIM4_Config(void) { #if 1 /* 空间不足,优化代码 */ /* TIM4是自动重载的8位定时器,计数方向为递增,当递增到0时可以产生定时器中断,并自动重装定时器初值 */ /* 计算期望的计数时钟个数, 由于TIM4是8位的定时器,因此如果该值大于255,则需要进行分频 */ TIM4_DeInit(); /* 复位TIM4所有寄存器 */ TIM4_ARRPreloadConfig(ENABLE); /* 预先装载使能 */ TIM4_TimeBaseInit(TIM4_PRESCALER_128, (16000000u / (1000 / SYSTICK_PERIOD)) / 128); /* 设置预分频和定时器重载 */ /* Clear TIM4 update flag */ TIM4_ClearFlag(TIM4_FLAG_UPDATE); TIM4_ITConfig(TIM4_IT_UPDATE, ENABLE); /* 使能TIM4中断 */ //TIM4_UpdateDisableConfig(ENABLE); /* 使能TIM4自动溢出事件 */ TIM4_Cmd(ENABLE); /* 使能TIM4 */ #else /* 下面这个分支,可以根据时钟自动计算TIM4定时器初值 */ uint32_t uiSysClkFreq; uint32_t uiCount; uiSysClkFreq = CLK_GetClockFreq(); /* 获得当前的系统时钟频率 */ TIM4_DeInit(); /* 复位TIM4所有寄存器 */ TIM4_ARRPreloadConfig(ENABLE); /* 预先装载使能 */ /* TIM4是自动重载的8位定时器,计数方向为递增,当递增到0时可以产生定时器中断,并自动重装定时器初值 */ /* 计算期望的计数时钟个数, 由于TIM4是8位的定时器,因此如果该值大于255,则需要进行分频 */ uiCount = uiSysClkFreq / (1000 / SYSTICK_PERIOD); if (uiCount <= (1u << 8)) { TIM4_TimeBaseInit(TIM4_PRESCALER_1, uiCount); /* 设置预分频和定时器重载 */ } else if (uiCount <= (1u << 9)) { TIM4_TimeBaseInit(TIM4_PRESCALER_2, uiCount / 2); /* 设置预分频和定时器重载 */ } else if (uiCount <= (1u << 10)) { TIM4_TimeBaseInit(TIM4_PRESCALER_4, uiCount / 4); /* 设置预分频和定时器重载 */ } else if (uiCount <= (1u << 11)) { TIM4_TimeBaseInit(TIM4_PRESCALER_8, uiCount / 8); /* 设置预分频和定时器重载 */ } else if (uiCount <= (1u << 12)) { TIM4_TimeBaseInit(TIM4_PRESCALER_16, uiCount / 16); /* 设置预分频和定时器重载 */ } else if (uiCount <= (1u << 13)) { TIM4_TimeBaseInit(TIM4_PRESCALER_32, uiCount / 32); /* 设置预分频和定时器重载 */ } else if (uiCount < (1u << 14)) { TIM4_TimeBaseInit(TIM4_PRESCALER_64, uiCount / 64); /* 设置预分频和定时器重载 */ } else if (uiCount < (1u << 15)) { TIM4_TimeBaseInit(TIM4_PRESCALER_128, uiCount / 128); /* 设置预分频和定时器重载 */ } else { while (1); /* 异常,死机等待排错 */ } /* Clear TIM4 update flag */ TIM4_ClearFlag(TIM4_FLAG_UPDATE); TIM4_ITConfig(TIM4_IT_UPDATE, ENABLE); /* 使能TIM4中断 */ //TIM4_UpdateDisableConfig(ENABLE); /* 使能TIM4自动溢出事件 */ TIM4_Cmd(ENABLE); /* 使能TIM4 */ #endif }
void MOD_TIM_Config(Mod_Master_Frame_TypeDef* aFrame) { TIM2_DeInit(); TIM2_TimeBaseInit(0x0F, 1500); //2ms comm response time TIM2_UpdateRequestConfig(TIM2_UPDATESOURCE_REGULAR); TIM2_GenerateEvent(TIM2_EVENTSOURCE_UPDATE); TIM2_Cmd(DISABLE); TIM2_ClearITPendingBit(TIM2_IT_UPDATE); TIM2_ITConfig(TIM2_IT_UPDATE, ENABLE); TIM2_ClearFlag(TIM2_FLAG_UPDATE); TIM4_DeInit(); TIM4_TimeBaseInit(0x07, 126); //128 * 126 = 16128 = 2ms (8MHz), frame check TIM4_UpdateRequestConfig(TIM4_UPDATESOURCE_REGULAR); TIM4_GenerateEvent(TIM4_EVENTSOURCE_UPDATE); TIM4_Cmd(DISABLE); TIM4_ClearITPendingBit(TIM4_IT_UPDATE); TIM4_ITConfig(TIM4_IT_UPDATE, ENABLE); TIM4_ClearFlag(TIM4_FLAG_UPDATE); }
void resetTim4For500us(void) { TIM4_DeInit(); TIM4_TimeBaseInit(TIM4_PRESCALER_32,250); TIM4_ITConfig(TIM4_IT_UPDATE,ENABLE); TIM4_ARRPreloadConfig(ENABLE); TIM4_Cmd(ENABLE); }
void TIM4_Init(void) { TIM4_DeInit(); // 24000000/128/1000 = 187.5 /* Time base configuration */ TIM4_TimeBaseInit(TIM4_PRESCALER_128, FMASTER/128/1000); // 1ms中断 TIM4_ITConfig(TIM4_IT_UPDATE, ENABLE); TIM4_Cmd(ENABLE); }
void dev_vtimerInit(void) { TIM4_DeInit(); /* Time base configuration */ TIM4_TimeBaseInit(TIM4_PRESCALER_128,ARRVALUE); // Setting for 1ms Delta time //ITC_SetSoftwarePriority(ITC_IRQ_TIM4_OVF, ITC_PRIORITYLEVEL_1); ITC->ISPR6 |= 0xC0; ITC->ISPR6 &= 0x7F; TIM4_ITConfig(TIM4_IT_UPDATE, ENABLE); enableInterrupts(); /* Enable TIM4 */ TIM4_Cmd(ENABLE); }
void Tim4_init(void) { // reset all registers TIM4_DeInit(); // 10ms TIM4_TimeBaseInit(TIM4_PRESCALER_128, 156); // interrupt config TIM4_ITConfig(TIM4_FLAG_UPDATE, ENABLE); // source d'IT : quand on atteint la valeur. // TIM4_UpdateRequestConfig(TIM4_UPDATESOURCE_GLOBAL); //TIM4_UPDATESOURCE_REGULAR // tourne en boucle TIM4_SelectOnePulseMode(TIM4_OPMODE_REPETITIVE); // TIM4_ARR manuel // TIM4_ARRPreloadConfig(DISABLE); }