void FiniDebugPubnames(
dw_client cli )
{
static char const zeros[ sizeof( uint_32 ) ];
char buf[ sizeof( debug_ref ) ];
debug_ref offset;
/* write the set terminator */
CLIWrite( DW_DEBUG_PUBNAMES, zeros, sizeof( uint_32 ) );
/* backpatch the section length */
offset = CLITell( DW_DEBUG_PUBNAMES )
- cli->section_base[ DW_DEBUG_PUBNAMES ] - sizeof( debug_ref );
WriteRef( buf, offset );
CLISeek( DW_DEBUG_PUBNAMES, cli->section_base[ DW_DEBUG_PUBNAMES ],
DW_SEEK_SET );
CLIWrite( DW_DEBUG_PUBNAMES, buf, sizeof( debug_ref ) );
CLISeek( DW_DEBUG_PUBNAMES, 0, DW_SEEK_END );
}
void DispatchStage::dispatch(InstRef IR) {
assert(!CarryOver && "Cannot dispatch another instruction!");
Instruction &IS = *IR.getInstruction();
const InstrDesc &Desc = IS.getDesc();
const unsigned NumMicroOps = Desc.NumMicroOps;
if (NumMicroOps > DispatchWidth) {
assert(AvailableEntries == DispatchWidth);
AvailableEntries = 0;
CarryOver = NumMicroOps - DispatchWidth;
} else {
assert(AvailableEntries >= NumMicroOps);
AvailableEntries -= NumMicroOps;
}
// A dependency-breaking instruction doesn't have to wait on the register
// input operands, and it is often optimized at register renaming stage.
// Update RAW dependencies if this instruction is not a dependency-breaking
// instruction. A dependency-breaking instruction is a zero-latency
// instruction that doesn't consume hardware resources.
// An example of dependency-breaking instruction on X86 is a zero-idiom XOR.
bool IsDependencyBreaking = IS.isDependencyBreaking();
for (std::unique_ptr<ReadState> &RS : IS.getUses())
if (RS->isImplicitRead() || !IsDependencyBreaking)
updateRAWDependencies(*RS, STI);
// By default, a dependency-breaking zero-latency instruction is expected to
// be optimized at register renaming stage. That means, no physical register
// is allocated to the instruction.
bool ShouldAllocateRegisters =
!(Desc.isZeroLatency() && IsDependencyBreaking);
SmallVector<unsigned, 4> RegisterFiles(PRF.getNumRegisterFiles());
for (std::unique_ptr<WriteState> &WS : IS.getDefs()) {
PRF.addRegisterWrite(WriteRef(IR.first, WS.get()), RegisterFiles,
ShouldAllocateRegisters);
}
// Reserve slots in the RCU, and notify the instruction that it has been
// dispatched to the schedulers for execution.
IS.dispatch(RCU.reserveSlot(IR, NumMicroOps));
// Notify listeners of the "instruction dispatched" event.
notifyInstructionDispatched(IR, RegisterFiles);
}
