void _bsp_exit_handler
(
void
)
{
#ifndef BSP_CACHE_INHIBIT
_dcache_flush();
_dcache_disable();
_icache_disable();
#endif
}
void _icache_disable
(
void
)
{ /* Body */
#if defined(PSP_PPC403) || defined(PSP_PPC401) || defined(PSP_IOP480) || \
defined(PSP_PPC405)
_icache_invalidate();
_PSP_ISYNC();
_PSP_SPR_SET(1019, 0); // ICCR <= 0
#elif defined(PSP_PPC603) || defined(PSP_PPC740) || defined(PSP_PPC750) || \
defined(PSP_MPC8240) || defined(PSP_G2_CORE) || defined(PSP_PPC7400) || \
defined(PSP_E300_CORE)
_icache_invalidate();
asm(" mfspr r3,1008");
asm(" rlwinm r3,r3,0,17,15");
_PSP_ISYNC();
asm(" mtspr 1008,r3");
_PSP_ISYNC();
#elif defined(PSP_E500_CORE) || (defined(PSP_E200_CORE) && defined (PSP_E200_CORE_Z7))
register uint_32 val;
_dcache_flush();
_PSP_SPR_GET(val,1011); /* L1CSR1 */
val &= ~0x01;
#ifdef PSP_BOOKE
asm ("msync");
#else
_PSP_SYNC();
#endif
_PSP_ISYNC();
_PSP_SPR_SET(1011,val);
_PSP_ISYNC();
#elif defined(PSP_MPC555) || defined(PSP_MPC566)
/* Has no cache */
#elif defined(PSP_MPC505) || defined(PSP_MPC821) || defined(PSP_MPC823) || \
defined(PSP_MPC850) || defined(PSP_MPC855) || defined(PSP_MPC860) || \
defined(PSP_MPC866) || defined(PSP_MPC875)
_icache_invalidate();
asm(" mfspr r3,560");
asm(" oris r3,r3,0x0400");
asm(" mtspr 560,r3");
_PSP_ISYNC();
#elif defined(PSP_PPC440)
// Cache cannot be easily disabled. You must modify the appropriate
// TLB entries....
#elif defined(PSP_E200_CORE)
/* catch ERROR : undefined cpu type " */
#else
#error "CPU NOT DEFINED"
#endif
} /* Endbody */
void _dcache_disable
(
void
)
{ /* Body */
#if defined(PSP_PPC403) || defined(PSP_PPC401) || defined(PSP_IOP480) || \
defined(PSP_PPC405)
_dcache_flush();
_PSP_SPR_SET(1018,0); // mtspr dccr,0
_PSP_SYNC();
#elif defined(PSP_PPC603) || defined(PSP_PPC740) || defined(PSP_PPC750) || \
defined(PSP_MPC8240) || defined(PSP_G2_CORE) || defined(PSP_PPC7400) || \
defined(PSP_E300_CORE)
register uint_32 val;
_dcache_flush();
_PSP_SPR_GET(val,1008);
val &= ~0x4000;
_PSP_SYNC();
_PSP_SPR_SET(1008,val);
_PSP_SYNC();
#elif defined(PSP_E500_CORE) || defined(PSP_E200_CORE)
register uint_32 val;
_dcache_flush();
_PSP_SPR_GET(val,1010); /* L1CSR0 */
val &= ~0x01;
#ifdef PSP_BOOKE
asm ("msync");
#else
_PSP_SYNC();
#endif
_PSP_ISYNC();
_PSP_SPR_SET(1010,val);
_PSP_ISYNC();
#elif defined(PSP_MPC555) || defined(PSP_MPC566)
/* Has no cache */
/* define PSP_MPC823 in macro */
#elif defined(PSP_MPC821) || defined(PSP_MPC823) || defined(PSP_MPC850) || \
defined(PSP_MPC855) || defined(PSP_MPC860) || defined(PSP_MPC866) || \
defined(PSP_MPC875)
register uint_32 val;
_dcache_flush();
_PSP_SPR_GET(val,568);
val |= 0x04000000;
_PSP_SYNC();
_PSP_SPR_SET(568,val);
#elif defined(PSP_PPC440)
// Cache cannot be easily disabled. You must modify the appropriate
// TLB entries that allow cache to disallow it. I'm not sure that's
// a good idea.
/* catch ERROR : undefined cpu type " */
#else
#error "CPU NOT DEFINED"
#endif
} /* Endbody */
