void sb1480_clockevent_init(void)
{
unsigned int cpu = smp_processor_id();
unsigned int irq = K_BCM1480_INT_TIMER_0 + cpu;
struct irqaction *action = &per_cpu(sibyte_hpt_irqaction, cpu);
struct clock_event_device *cd = &per_cpu(sibyte_hpt_clockevent, cpu);
unsigned char *name = per_cpu(sibyte_hpt_name, cpu);
BUG_ON(cpu > 3); /* Only have 4 general purpose timers */
sprintf(name, "bcm1480-counter-%d", cpu);
cd->name = name;
cd->features = CLOCK_EVT_FEAT_PERIODIC |
CLOCK_EVT_FEAT_ONESHOT;
clockevent_set_clock(cd, V_SCD_TIMER_FREQ);
cd->max_delta_ns = clockevent_delta2ns(0x7fffff, cd);
cd->min_delta_ns = clockevent_delta2ns(2, cd);
cd->rating = 200;
cd->irq = irq;
cd->cpumask = cpumask_of(cpu);
cd->set_next_event = sibyte_next_event;
cd->set_state_shutdown = sibyte_shutdown;
cd->set_state_periodic = sibyte_set_periodic;
cd->set_state_oneshot = sibyte_shutdown;
clockevents_register_device(cd);
bcm1480_mask_irq(cpu, irq);
/*
* Map the timer interrupt to IP[4] of this cpu
*/
__raw_writeq(IMR_IP4_VAL,
IOADDR(A_BCM1480_IMR_REGISTER(cpu,
R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (irq << 3)));
bcm1480_unmask_irq(cpu, irq);
action->handler = sibyte_counter_handler;
action->flags = IRQF_PERCPU | IRQF_TIMER;
action->name = name;
action->dev_id = cd;
irq_set_affinity(irq, cpumask_of(cpu));
setup_irq(irq, action);
}
void bcm1480_time_init(void)
{
int cpu = smp_processor_id();
int irq = K_BCM1480_INT_TIMER_0+cpu;
/* Only have 4 general purpose timers */
if (cpu > 3) {
BUG();
}
bcm1480_mask_irq(cpu, irq);
/* Map the timer interrupt to ip[4] of this cpu */
__raw_writeq(IMR_IP4_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H)
+ (irq<<3)));
/* the general purpose timer ticks at 1 Mhz independent of the rest of the system */
/* Disable the timer and set up the count */
__raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
__raw_writeq(
BCM1480_HPT_VALUE/HZ
, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT)));
/* Set the timer running */
__raw_writeq(M_SCD_TIMER_ENABLE|M_SCD_TIMER_MODE_CONTINUOUS,
IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG)));
bcm1480_unmask_irq(cpu, irq);
bcm1480_steal_irq(irq);
/*
* This interrupt is "special" in that it doesn't use the request_irq
* way to hook the irq line. The timer interrupt is initialized early
* enough to make this a major pain, and it's also firing enough to
* warrant a bit of special case code. bcm1480_timer_interrupt is
* called directly from irq_handler.S when IP[4] is set during an
* interrupt
*/
}
void __init arch_init_irq(void)
{
unsigned int i, cpu;
u64 tmp;
unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
STATUSF_IP1 | STATUSF_IP0;
/* Default everything to IP2 */
/* Start with _high registers which has no bit 0 interrupt source */
for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_BCM1480_IMR_REGISTER(cpu,
R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) + (i << 3)));
}
}
/* Now do _low registers */
for (i = 0; i < BCM1480_NR_IRQS_HALF; i++) {
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(IMR_IP2_VAL,
IOADDR(A_BCM1480_IMR_REGISTER(cpu,
R_BCM1480_IMR_INTERRUPT_MAP_BASE_L) + (i << 3)));
}
}
init_bcm1480_irqs();
/*
* Map the high 16 bits of mailbox_0 registers to IP[3], for
* inter-cpu messages
*/
/* Was I1 */
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(IMR_IP3_VAL, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
(K_BCM1480_INT_MBOX_0_0 << 3)));
}
/* Clear the mailboxes. The firmware may leave them dirty */
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_0_CLR_CPU)));
__raw_writeq(0xffffffffffffffffULL,
IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_MAILBOX_1_CLR_CPU)));
}
/* Mask everything except the high 16 bit of mailbox_0 registers for all cpus */
tmp = ~((u64) 0) ^ ( (((u64) 1) << K_BCM1480_INT_MBOX_0_0));
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_H)));
}
tmp = ~((u64) 0);
for (cpu = 0; cpu < 4; cpu++) {
__raw_writeq(tmp, IOADDR(A_BCM1480_IMR_REGISTER(cpu, R_BCM1480_IMR_INTERRUPT_MASK_L)));
}
bcm1480_steal_irq(K_BCM1480_INT_MBOX_0_0);
/*
* Note that the timer interrupts are also mapped, but this is
* done in bcm1480_time_init(). Also, the profiling driver
* does its own management of IP7.
*/
#ifdef CONFIG_KGDB
imask |= STATUSF_IP6;
#endif
/* Enable necessary IPs, disable the rest */
change_c0_status(ST0_IM, imask);
#ifdef CONFIG_KGDB
if (kgdb_flag) {
kgdb_irq = K_BCM1480_INT_UART_0 + kgdb_port;
#ifdef CONFIG_SIBYTE_SB1250_DUART
sb1250_duart_present[kgdb_port] = 0;
#endif
/* Setup uart 1 settings, mapper */
/* QQQ FIXME */
__raw_writeq(M_DUART_IMR_BRK, IO_SPACE_BASE + A_DUART_IMRREG(kgdb_port));
bcm1480_steal_irq(kgdb_irq);
__raw_writeq(IMR_IP6_VAL,
IO_SPACE_BASE + A_BCM1480_IMR_REGISTER(0, R_BCM1480_IMR_INTERRUPT_MAP_BASE_H) +
(kgdb_irq<<3));
bcm1480_unmask_irq(0, kgdb_irq);
#ifdef CONFIG_GDB_CONSOLE
register_gdb_console();
#endif
prom_printf("Waiting for GDB on UART port %d\n", kgdb_port);
set_debug_traps();
breakpoint();
}
#endif
}
static void end_bcm1480_irq(unsigned int irq)
{
if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
}
}
static void enable_bcm1480_irq(unsigned int irq)
{
bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
}
static unsigned int startup_bcm1480_irq(unsigned int irq)
{
bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
return 0; /* never anything pending */
}
static void enable_bcm1480_irq(struct irq_data *d)
{
unsigned int irq = d->irq;
bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
}