Ejemplo n.º 1
0
void bsp_start( void )
{
  rtems_status_code sc = RTEMS_SUCCESSFUL;
  uintptr_t intrStackStart;
  uintptr_t intrStackSize;

  /*
   * Note we can not get CPU identification dynamically, so
   * force current_ppc_cpu.
   */
  current_ppc_cpu = PPC_PSIM;

  /*
   *  initialize the device driver parameters
   * assume we are running with 20MHz bus
   * this should speed up some tests :-)
   */
  BSP_bus_frequency        = 20;
  bsp_time_base_frequency  = 20000000;
  bsp_clicks_per_usec      = BSP_bus_frequency;
  rtems_counter_initialize_converter(bsp_time_base_frequency);

  /*
   * Initialize the interrupt related settings.
   */
  intrStackStart = (uintptr_t) bsp_interrupt_stack_start;
  intrStackSize =  (uintptr_t) bsp_interrupt_stack_size;

  BSP_mem_size = (uint32_t )RamSize;

  /*
   * Initialize default raw exception handlers.
   */
  ppc_exc_initialize(intrStackStart, intrStackSize);

  /* Install default handler for the decrementer exception */
  sc = ppc_exc_set_handler( ASM_DEC_VECTOR, default_decrementer_exception_handler);
  if (sc != RTEMS_SUCCESSFUL) {
    BSP_panic("cannot install decrementer exception handler");
  }

  /* Initalize interrupt support */
  bsp_interrupt_initialize();

#if 0
  /*
   * Setup BATs and enable MMU
   */
  /* Memory */
  setdbat(0, 0x0<<24, 0x0<<24, 2<<24, _PAGE_RW);
  setibat(0, 0x0<<24, 0x0<<24, 2<<24,        0);
  /* PCI    */
  setdbat(1, 0x8<<24, 0x8<<24, 1<<24,  IO_PAGE);
  setdbat(2, 0xc<<24, 0xc<<24, 1<<24,  IO_PAGE);

  _write_MSR(_read_MSR() | MSR_DR | MSR_IR);
  __asm__ volatile("sync; isync");
#endif
}
Ejemplo n.º 2
0
void bsp_start(void)
{
  stm32f4_gpio_set_config_array(&stm32f4_start_config_gpio [0]);

  if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
    _CPU_Fatal_halt(0xe);
  }
}
Ejemplo n.º 3
0
void bsp_start(void)
{
    a9mpcore_clock_initialize_early();
    bsp_interrupt_initialize();
    rtems_cache_coherent_add_area(
        bsp_section_nocacheheap_begin,
        (uintptr_t) bsp_section_nocacheheap_size
    );
}
Ejemplo n.º 4
0
/*
 *
 * NAME: bsp_start_default - BSP initialization function
 *
 * DESCRIPTION:
 *   This function is called before RTEMS is initialized and used
 *   adjust the kernel's configuration.
 *
 *   This function also configures the CPU's memory protection unit.
 *
 * RESTRICTIONS/LIMITATIONS:
 *   Since RTEMS is not configured, no RTEMS functions can be called.
 *
 */
void bsp_start_default( void )
{
  /* disable interrupts */
  XSCALE_INT_ICMR = 0x0;
  rtems_exception_init_mngt();
  if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
    _CPU_Fatal_halt(0xe);
  }
} /* bsp_start */
Ejemplo n.º 5
0
/*
 * bsp_start_default - BSP initialization function
 *
 * This function is called before RTEMS is initialized and used
 * adjust the kernel's configuration.
 *
 * This function also configures the CPU's memory protection unit.
 *
 * RESTRICTIONS/LIMITATIONS:
 *   Since RTEMS is not configured, no RTEMS functions can be called.
 */
static void bsp_start_default( void )
{
  PINSEL2 =0x0f814914;
  BCFG0 = 0x1000ffef;
  BCFG1 = 0x1000ffef;

  MEMMAP = 0x2;  //debug and excute outside chip

  PLLCON = 1;
  #if (Fpclk / (Fcclk / 4)) == 1
    VPBDIV = 0;
  #endif
  #if (Fpclk / (Fcclk / 4)) == 2
    VPBDIV = 2;
  #endif
  #if (Fpclk / (Fcclk / 4)) == 4
    VPBDIV = 1;
  #endif

  #if (Fcco / Fcclk) == 2
    PLLCFG = ((Fcclk / Fosc) - 1) | (0 << 5);
  #endif
  #if (Fcco / Fcclk) == 4
    PLLCFG = ((Fcclk / Fosc) - 1) | (1 << 5);
  #endif
  #if (Fcco / Fcclk) == 8
    PLLCFG = ((Fcclk / Fosc) - 1) | (2 << 5);
  #endif
  #if (Fcco / Fcclk) == 16
    PLLCFG = ((Fcclk / Fosc) - 1) | (3 << 5);
  #endif
  PLLFEED = 0xaa;
  PLLFEED = 0x55;
  while((PLLSTAT & (1 << 10)) == 0);
  PLLCON = 3;
  PLLFEED = 0xaa;
  PLLFEED = 0x55;

  /* memory configure */
  /* it is not needed in my formatter board */
  //MAMCR = 0;
  // MAMTIM = 3;
  //MAMCR = 2;

  UART0_Ini();

  /*
   * Init rtems exceptions management
   */
  /* FIXME: Use shared start.S */
  rtems_exception_init_mngt();

  /*
   * Init rtems interrupt management
   */
  bsp_interrupt_initialize();
} /* bsp_start */
Ejemplo n.º 6
0
void bsp_start(void)
{
  unsigned long i = 0;

  ppc_cpu_id_t myCpu;
  ppc_cpu_revision_t myCpuRevision;

  /*
   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
   * store the result in global variables so that it can be used latter...
   */
  myCpu = get_ppc_cpu_type();
  myCpuRevision = get_ppc_cpu_revision();

  /* Initialize some device driver parameters */
  #ifdef HAS_UBOOT
    BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq;
    bsp_clicks_per_usec = bsp_uboot_board_info.bi_busfreq / 8000000;
  #endif /* HAS_UBOOT */
  rtems_counter_initialize_converter(BSP_bus_frequency / 8);

  /* Initialize some console parameters */
  for (i = 0; i < Console_Configuration_Count; ++i) {
    console_tbl *ct = &Console_Configuration_Ports[i];

    ct->ulClock = BSP_bus_frequency;

    #ifdef HAS_UBOOT
      if (ct->deviceType == SERIAL_NS16550) {
        ct->pDeviceParams = (void *) bsp_uboot_board_info.bi_baudrate;
      }
    #endif
  }

  /* Disable decrementer */
  PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(BOOKE_TCR, BOOKE_TCR_DIE);

  /* Initialize exception handler */
  ppc_exc_initialize_with_vector_base(
    (uintptr_t) bsp_section_work_begin,
    rtems_configuration_get_interrupt_stack_size(),
    bsp_exc_vector_base
  );

  /* Now it is possible to make the code execute only */
  qoriq_mmu_change_perm(
    FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX,
    FSL_EIS_MAS3_SX,
    FSL_EIS_MAS3_SR
  );

  /* Initalize interrupt support */
  bsp_interrupt_initialize();

  /* Disable boot page translation */
  qoriq.lcc.bptr &= ~BPTR_EN;
}
Ejemplo n.º 7
0
void bsp_start(void)
{
	rtems_status_code sc = RTEMS_SUCCESSFUL;
	ppc_cpu_id_t myCpu;
	ppc_cpu_revision_t myCpuRevision;
#if defined(MPC55XX_BOARD_MPC5674FEVB)
        unsigned system_clock_divider = 2;
#else
        unsigned system_clock_divider = 1;
#endif

        null_pointer_protection();

	/*
	 * make sure BSS/SBSS is cleared
	 */
	memset(&bsp_section_bss_begin [0], 0, (size_t) bsp_section_bss_size);

	/*
	 * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
	 * function store the result in global variables so that it can be used
	 * latter...
	 */
	myCpu = get_ppc_cpu_type();
	myCpuRevision = get_ppc_cpu_revision();

	/*
	 * determine clock speed
	 */
	bsp_clock_speed = mpc55xx_get_system_clock() / system_clock_divider;

	/* Time reference value */
	bsp_clicks_per_usec = bsp_clock_speed / 1000000;

	/* Initialize exceptions */
	ppc_exc_vector_base = (uint32_t) mpc55xx_exc_vector_base;
	sc = ppc_exc_initialize(
		PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
                (uintptr_t) bsp_section_work_begin,
                Configuration.interrupt_stack_size
	);
	if (sc != RTEMS_SUCCESSFUL) {
		BSP_panic( "Cannot initialize exceptions");
	}
	ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler);

	/* Initialize interrupts */
	sc = bsp_interrupt_initialize();
	if (sc != RTEMS_SUCCESSFUL) {
		BSP_panic( "Cannot initialize interrupts");
	}

	mpc55xx_edma_init();
	#ifdef MPC55XX_EMIOS_PRESCALER
		mpc55xx_emios_initialize(MPC55XX_EMIOS_PRESCALER);
	#endif
}
Ejemplo n.º 8
0
/*
 *  bsp_start
 *
 *  This routine does the bulk of the system initialization.
 */
void bsp_start( void )
{
    unsigned int compare = 0;

    mips_set_sr( 0x7f00 );  /* all interrupts unmasked but globally off */
    /* depend on the IRC to take care of things */
    __asm__ volatile ("mtc0 %0, $11\n" :: "r" (compare));
    bsp_interrupt_initialize();
}
Ejemplo n.º 9
0
void bsp_start( void )
{
  /* set the cpu mode to supervisor and big endian */
  arm_cpu_mode = 0x213;

  tms570_pom_remap();

  /* Interrupts */
  bsp_interrupt_initialize();

}
Ejemplo n.º 10
0
void bsp_start(void)
{
  if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
    _CPU_Fatal_halt(0xe);
  }

  bsp_stack_initialize(
    bsp_section_stack_begin,
    (uintptr_t) bsp_section_stack_size
  );

  lpc32xx_timer_initialize();
}
Ejemplo n.º 11
0
/*
 * NAME: bsp_start_default - BSP initialization function
 *
 *   This function is called before RTEMS is initialized
 *   This function also configures the CPU's memory protection unit.
 *
 *
 * RESTRICTIONS/LIMITATIONS:
 *   Since RTEMS is not configured, no RTEMS functions can be called.
 *
 */
void bsp_start_default( void )
{
  /* disable interrupts */
  *EP7312_INTMR1 = 0;
  *EP7312_INTMR2 = 0;

  /*
   * Init rtems exceptions management
   */
  rtems_exception_init_mngt();

  /*
   * Init rtems interrupt management
   */
  bsp_interrupt_initialize();
} /* bsp_start */
Ejemplo n.º 12
0
void bsp_start(void)
{
	null_pointer_protection();

	/*
	 * make sure BSS/SBSS is cleared
	 */
	memset(&bsp_section_bss_begin [0], 0, (size_t) bsp_section_bss_size);

	/*
	 * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
	 * function store the result in global variables so that it can be used
	 * latter...
	 */
	get_ppc_cpu_type();
	get_ppc_cpu_revision();

	/*
	 * determine clock speed
	 */
	bsp_clock_speed = mpc55xx_get_system_clock() / MPC55XX_SYSTEM_CLOCK_DIVIDER;

	/* Time reference value */
	bsp_clicks_per_usec = bsp_clock_speed / 1000000;

	/* Initialize exceptions */
	ppc_exc_initialize_with_vector_base(
		PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
		(uintptr_t) bsp_section_work_begin,
		rtems_configuration_get_interrupt_stack_size(),
		mpc55xx_exc_vector_base
	);
	#ifndef PPC_EXC_CONFIG_USE_FIXED_HANDLER
		ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler);
	#endif

	/* Initialize interrupts */
	bsp_interrupt_initialize();

	#if MPC55XX_CHIP_FAMILY != 566
		mpc55xx_edma_init();
	#endif

	#ifdef MPC55XX_EMIOS_PRESCALER
		mpc55xx_emios_initialize(MPC55XX_EMIOS_PRESCALER);
	#endif
}
Ejemplo n.º 13
0
void bsp_start( void )
{
#if BYTE_ORDER == BIG_ENDIAN
    /*
     * If CPU is big endian (TMS570 family variant)
     * set the CPU mode to supervisor and big endian.
     * Do not set mode if CPU is little endian
     * (RM48 family variant) for which default mode 0x13
     * defined in cpukit/score/cpu/arm/cpu.c
     * is right.
     */
    arm_cpu_mode = 0x213;
#endif

    tms570_initialize_and_clear();

    /*
     * If RTEMS image does not start at address 0x00000000
     * then first level exception table at memory begin has
     * to be replaced to point to RTEMS handlers addresses.
     *
     * There is no VBAR or other option because Cortex-R
     * does provides only fixed address 0x00000000 for exceptions
     * (0xFFFF0000-0xFFFF001C alternative SCTLR.V = 1 cannot
     * be used because target area corersponds to PMM peripheral
     * registers on TMS570).
     *
     * Alternative is to use jumps over SRAM based trampolines
     * but that is not compatible with
     *   Check TCRAM1 ECC error detection logic
     * which intentionally introduces data abort during startup
     * to check SRAM and if exception processing goes through
     * SRAM then it leads to CPU error halt.
     *
     * So use of POM to replace jumps to vectors target
     * addresses seems to be the best option.
     */
    if ( (uintptr_t)bsp_start_vector_table_begin != 0 ) {
        tms570_pom_remap();
    }

    /* Interrupts */
    bsp_interrupt_initialize();

}
Ejemplo n.º 14
0
/* Initialize interrupts */
int BSP_shared_interrupt_init(void)
{
       rtems_vector_number vector;
       rtems_isr_entry previous_isr;
       int sc, i;

       for (i=0; i <= BSP_INTERRUPT_VECTOR_MAX_STD; i++) {
               vector = SPARC_ASYNCHRONOUS_TRAP(i) + 0x10;
               rtems_interrupt_catch(BSP_ISR_handler, vector, &previous_isr);
       }

       /* Initalize interrupt support */
       sc = bsp_interrupt_initialize();
       if (sc != RTEMS_SUCCESSFUL)
               return -1;

       return 0;
}
Ejemplo n.º 15
0
/*
 *  bsp_start
 *
 *  This routine does the bulk of the system initialization.
 */
void bsp_start( void )
{
  /* uint32_t  board_ID = 0x420; */
  static    int j = 1;
  int       pci_init_retval;

  /*
   * Note: This is the value that works for qemu, and it was
   * unable to be validated on the actual hardware.
   */
  mips_set_sr( 0x04100000 );

  bsp_interrupt_initialize();

  /*
   *  XXX need to figure out a real value. :)
   *  This works for the qemu simulation, but timeing may
   *  be off for the actual hardware.
   */
  bsp_clicks_per_microsecond = 100;

  #if 1
  while ( j != 1 ) {
    int i;
    printk (".");
    for (i=0; i<1000; i++);
  }
  #endif

  /*
   * init PCI Bios interface...
   */
  pci_init_retval = pci_initialize();
  if (pci_init_retval != PCIB_ERR_SUCCESS) {
      printk("PCI bus: could not initialize PCI BIOS interface\n");
  }

  BSP_i8259s_init();

}
Ejemplo n.º 16
0
/*
 *  bsp_start()
 *
 *  Board-specific initialization code. Called from the generic boot_card()
 *  function defined in rtems/c/src/lib/libbsp/shared/main.c. That function
 *  does some of the board independent initialization. It is called from the
 *  MBX8xx entry point _start() defined in
 *  rtems/c/src/lib/libbsp/powerpc/mbx8xx/startup/start.S
 *
 *  _start() has set up a stack, has zeroed the .bss section, has turned off
 *  interrupts, and placed the processor in the supervisor mode. boot_card()
 *  has left the processor in that state when bsp_start() was called.
 *
 *  RUNS WITH ADDRESS TRANSLATION AND CACHING TURNED OFF!
 *  ASSUMES THAT THE VIRTUAL ADDRESSES WILL BE IDENTICAL TO THE PHYSICAL
 *  ADDRESSES. Software-controlled address translation would be required
 *  otherwise.
 *
 *  Input parameters: NONE
 *
 *  Output parameters: NONE
 *
 *  Return values: NONE
 */
void bsp_start(void)
{
  ppc_cpu_id_t myCpu;
  ppc_cpu_revision_t myCpuRevision;

  /*
   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
   * store the result in global variables so that it can be used latter...
   */
  myCpu 	= get_ppc_cpu_type();
  myCpuRevision = get_ppc_cpu_revision();

  mmu_init();

  /*
   * Enable instruction and data caches. Do not force writethrough mode.
   */
#if NVRAM_CONFIGURE == 1
  if ( nvram->cache_mode & 0x02 )
    rtems_cache_enable_instruction();
  if ( nvram->cache_mode & 0x01 )
    rtems_cache_enable_data();
#else
#if BSP_INSTRUCTION_CACHE_ENABLED
  rtems_cache_enable_instruction();
#endif
#if BSP_DATA_CACHE_ENABLED
  rtems_cache_enable_data();
#endif
#endif

  /* Initialize exception handler */
  ppc_exc_initialize(
    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    (uintptr_t) IntrStack_start,
    (uintptr_t) intrStack - (uintptr_t) IntrStack_start
  );

  /* Initalize interrupt support */
  bsp_interrupt_initialize();

  /*
   *  initialize the device driver parameters
   */

#if    ( defined(mbx860_001b) || \
         defined(mbx860_002b) || \
         defined(mbx860_003b) || \
         defined(mbx860_003b) || \
         defined(mbx860_004b) || \
         defined(mbx860_005b) || \
         defined(mbx860_006b) || \
         defined(mbx821_001b) || \
         defined(mbx821_002b) || \
         defined(mbx821_003b) || \
         defined(mbx821_004b) || \
         defined(mbx821_005b) || \
         defined(mbx821_006b))
  bsp_clicks_per_usec = 0;  /* for 32768Hz extclk */
#else
  bsp_clicks_per_usec = 1;  /* for 4MHz extclk */
#endif

  bsp_serial_per_sec = 10000000;
  bsp_serial_external_clock = true;
  bsp_serial_xon_xoff = false;
  bsp_serial_cts_rts = true;
  bsp_serial_rate = 9600;
#if ( defined(mbx821_001) || defined(mbx821_001b) || defined(mbx860_001b) )
  bsp_clock_speed = 50000000;
  bsp_timer_average_overhead = 3;
  bsp_timer_least_valid = 3;
#else
  bsp_clock_speed = 40000000;
  bsp_timer_average_overhead = 3;
  bsp_timer_least_valid = 3;
#endif

  m8xx.scc2.sccm=0;
  m8xx.scc2p.rbase=0;
  m8xx.scc2p.tbase=0;
  m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 );

#ifdef SHOW_MORE_INIT_SETTINGS
  printk("Exit from bspstart\n");
#endif

}
Ejemplo n.º 17
0
void bsp_start(void)
{
  bsp_interrupt_initialize();
}
Ejemplo n.º 18
0
void bsp_start( void)
{
  rtems_status_code sc = RTEMS_SUCCESSFUL;
  unsigned long i = 0;

  ppc_cpu_id_t myCpu;
  ppc_cpu_revision_t myCpuRevision;

  uintptr_t interrupt_stack_start = (uintptr_t) bsp_interrupt_stack_start;
  uintptr_t interrupt_stack_size = (uintptr_t) bsp_interrupt_stack_size;

  /*
   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
   * store the result in global variables so that it can be used latter...
   */
  myCpu = get_ppc_cpu_type();
  myCpuRevision = get_ppc_cpu_revision();

  /* Basic CPU initialization */
  cpu_init();

  /*
   * Enable instruction and data caches. Do not force writethrough mode.
   */

#ifdef BSP_INSTRUCTION_CACHE_ENABLED
  rtems_cache_enable_instruction();
#endif

#ifdef BSP_DATA_CACHE_ENABLED
  rtems_cache_enable_data();
#endif

  /*
   * This is evaluated during runtime, so it should be ok to set it
   * before we initialize the drivers.
   */

  /* Initialize some device driver parameters */

#ifdef HAS_UBOOT
  BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq;
#else /* HAS_UBOOT */
  BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
#endif /* HAS_UBOOT */
  bsp_time_base_frequency = BSP_bus_frequency / 4;
  bsp_clicks_per_usec = bsp_time_base_frequency / 1000000;

  /* Initialize some console parameters */
  for (i = 0; i < Console_Configuration_Count; ++i) {
    Console_Configuration_Ports [i].ulClock = BSP_bus_frequency;

    #ifdef HAS_UBOOT
      Console_Configuration_Ports [i].pDeviceParams =
        (void *) bsp_uboot_board_info.bi_baudrate;
    #endif
  }

  /* Initialize exception handler */
#ifndef BSP_DATA_CACHE_ENABLED
  ppc_exc_cache_wb_check = 0;
#endif
  sc = ppc_exc_initialize(
    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    interrupt_stack_start,
    interrupt_stack_size
  );
  if (sc != RTEMS_SUCCESSFUL) {
    BSP_panic("cannot initialize exceptions");
  }

  /* Install default handler for the decrementer exception */
  sc = ppc_exc_set_handler( ASM_DEC_VECTOR, mpc83xx_decrementer_exception_handler);
  if (sc != RTEMS_SUCCESSFUL) {
    BSP_panic("cannot install decrementer exception handler");
  }

  /* Initalize interrupt support */
  sc = bsp_interrupt_initialize();
  if (sc != RTEMS_SUCCESSFUL) {
    BSP_panic("cannot intitialize interrupts\n");
  }

#ifdef SHOW_MORE_INIT_SETTINGS
  printk("Exit from bspstart\n");
#endif
}
Ejemplo n.º 19
0
void bsp_start(void)
{
  unsigned long i = 0;

  /*
   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
   * store the result in global variables so that it can be used latter...
   */
  get_ppc_cpu_type();
  get_ppc_cpu_revision();

  /* Initialize some device driver parameters */
  #ifdef HAS_UBOOT
    BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq
      / QORIQ_BUS_CLOCK_DIVIDER;
    bsp_clicks_per_usec = BSP_bus_frequency / 8000000;
    rtems_counter_initialize_converter(
      #ifdef __PPC_CPU_E6500__
        bsp_uboot_board_info.bi_intfreq
      #else
        BSP_bus_frequency / 8
      #endif
    );
  #endif /* HAS_UBOOT */

  /* Initialize some console parameters */
  for (i = 0; i < console_device_count; ++i) {
    const console_device *dev = &console_device_table[i];
    const rtems_termios_device_handler *ns16550 =
      #ifdef BSP_USE_UART_INTERRUPTS
        &ns16550_handler_interrupt;
      #else
        &ns16550_handler_polled;
      #endif

    if (dev->handler == ns16550) {
      ns16550_context *ctx = (ns16550_context *) dev->context;

      ctx->clock = BSP_bus_frequency;

      #ifdef HAS_UBOOT
        #ifdef U_BOOT_GENERIC_BOARD_INFO
          ctx->initial_baud = 115200;
        #else
          ctx->initial_baud = bsp_uboot_board_info.bi_baudrate;
        #endif
      #endif
    }
  }

  /* Initialize exception handler */
  ppc_exc_initialize_with_vector_base(
    (uintptr_t) bsp_section_work_begin,
    rtems_configuration_get_interrupt_stack_size(),
    bsp_exc_vector_base
  );

  /* Now it is possible to make the code execute only */
  qoriq_mmu_change_perm(
    FSL_EIS_MAS3_SR | FSL_EIS_MAS3_SX,
    FSL_EIS_MAS3_SX,
    FSL_EIS_MAS3_SR
  );

  /* Initalize interrupt support */
  bsp_interrupt_initialize();

  rtems_cache_coherent_add_area(
    bsp_section_nocacheheap_begin,
    (uintptr_t) bsp_section_nocacheheap_size
  );

  /* Disable boot page translation */
#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT)
  qoriq.lcc.bstar &= ~LCC_BSTAR_EN;
#else
  qoriq.lcc.bptr &= ~BPTR_EN;
#endif
}
Ejemplo n.º 20
0
void bsp_start( void)
{
  rtems_status_code sc = RTEMS_SUCCESSFUL;
  ppc_cpu_id_t myCpu;
  ppc_cpu_revision_t myCpuRevision;

  uintptr_t interrupt_stack_start = (uintptr_t) bsp_interrupt_stack_start;
  uintptr_t interrupt_stack_size = (uintptr_t) bsp_interrupt_stack_size;

  /*
   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
   * store the result in global variables so that it can be used latter...
   */
  myCpu = get_ppc_cpu_type();
  myCpuRevision = get_ppc_cpu_revision();

  /* Basic CPU initialization */
  cpu_init();

  /*
   * Enable instruction and data caches. Do not force writethrough mode.
   */

#if INSTRUCTION_CACHE_ENABLE
  rtems_cache_enable_instruction();
#endif

#if DATA_CACHE_ENABLE
  rtems_cache_enable_data();
#endif

  /*
   * This is evaluated during runtime, so it should be ok to set it
   * before we initialize the drivers.
   */

  /* Initialize some device driver parameters */
  /*
   * get the (internal) bus frequency
   * NOTE: the external bus may be clocked at a lower speed
   * but this does not concern the internal units like PIT,
   * DEC, baudrate generator etc)
   */
  if (RTEMS_SUCCESSFUL !=
      bsp_tqm_get_cib_uint32("cu",
			     &BSP_bus_frequency)) {
    BSP_panic("Cannot determine BUS frequency\n");
  }

  bsp_clicks_per_usec = BSP_bus_frequency/1000000/16;
  bsp_timer_least_valid = 3;
  bsp_timer_average_overhead = 3;

  /* Initialize exception handler */
  sc = ppc_exc_initialize(
    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    interrupt_stack_start,
    interrupt_stack_size
  );
  if (sc != RTEMS_SUCCESSFUL) {
    BSP_panic("cannot initialize exceptions");
  }

  /* Initalize interrupt support */
  sc = bsp_interrupt_initialize();
  if (sc != RTEMS_SUCCESSFUL) {
    BSP_panic("cannot intitialize interrupts");
  }

#ifdef SHOW_MORE_INIT_SETTINGS
  printk("Exit from bspstart\n");
#endif
}
Ejemplo n.º 21
0
void bsp_start(void)
{
  stm32f4_gpio_set_config_array(&stm32f4_start_config_gpio [0]);

  bsp_interrupt_initialize();
}
Ejemplo n.º 22
0
void bsp_start( void)
{
  rtems_status_code sc = RTEMS_SUCCESSFUL;
  unsigned long i = 0;

  /*
   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
   * store the result in global variables so that it can be used latter...
   */
  get_ppc_cpu_type();
  get_ppc_cpu_revision();

  /* Basic CPU initialization */
  cpu_init();

  /*
   * Enable instruction and data caches. Do not force writethrough mode.
   */

#ifdef BSP_INSTRUCTION_CACHE_ENABLED
  rtems_cache_enable_instruction();
#endif

#ifdef BSP_DATA_CACHE_ENABLED
  rtems_cache_enable_data();
#endif

  /*
   * This is evaluated during runtime, so it should be ok to set it
   * before we initialize the drivers.
   */

  /* Initialize some device driver parameters */

#ifdef HAS_UBOOT
  BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq;
#else /* HAS_UBOOT */
  BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
#endif /* HAS_UBOOT */
  bsp_time_base_frequency = BSP_bus_frequency / 4;
  bsp_clicks_per_usec = bsp_time_base_frequency / 1000000;
  rtems_counter_initialize_converter(bsp_time_base_frequency);

  /* Initialize some console parameters */
  for (i = 0; i < console_device_count; ++i) {
    ns16550_context *ctx = (ns16550_context *) console_device_table[i].context;

    ctx->clock = BSP_bus_frequency;

    #ifdef HAS_UBOOT
      ctx->initial_baud = bsp_uboot_board_info.bi_baudrate;
    #endif
  }

  /* Initialize exception handler */
#ifndef BSP_DATA_CACHE_ENABLED
  ppc_exc_cache_wb_check = 0;
#endif
  ppc_exc_initialize(
    (uintptr_t) bsp_section_work_begin,
    rtems_configuration_get_interrupt_stack_size()
  );

  /* Install default handler for the decrementer exception */
  sc = ppc_exc_set_handler( ASM_DEC_VECTOR, mpc83xx_decrementer_exception_handler);
  if (sc != RTEMS_SUCCESSFUL) {
    rtems_panic("cannot install decrementer exception handler");
  }

  /* Initalize interrupt support */
  bsp_interrupt_initialize();

#ifdef SHOW_MORE_INIT_SETTINGS
  printk("Exit from bspstart\n");
#endif
}
Ejemplo n.º 23
0
void bsp_start(void)
{
  rtems_status_code sc = RTEMS_SUCCESSFUL;
  ppc_cpu_id_t myCpu;
  ppc_cpu_revision_t myCpuRevision;

  /* Set MPC8260ADS board LEDS and Uart enable lines */
  _BSP_GPLED0_off();
  _BSP_GPLED1_off();
  _BSP_Uart1_enable();
  _BSP_Uart2_enable();

  /*
   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
   * store the result in global variables so that it can be used latter...
   */
  myCpu 	= get_ppc_cpu_type();
  myCpuRevision = get_ppc_cpu_revision();

  cpu_init();

/*
  mmu_init();
*/

  /* Initialize exception handler */
  /* FIXME: Interrupt stack begin and size */
  sc = ppc_exc_initialize(
    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    (uintptr_t) IntrStack_start,
    (uintptr_t) intrStack - (uintptr_t) IntrStack_start
  );
  if (sc != RTEMS_SUCCESSFUL) {
    BSP_panic("cannot intitialize exceptions");
  }

  /* Initalize interrupt support */
  sc = bsp_interrupt_initialize();
  if (sc != RTEMS_SUCCESSFUL) {
    BSP_panic("cannot intitialize interrupts");
  }


/*
  mmu_init();
*/

  /*
   * Enable instruction and data caches. Do not force writethrough mode.
   */
#if INSTRUCTION_CACHE_ENABLE
  rtems_cache_enable_instruction();
#endif
#if DATA_CACHE_ENABLE
  rtems_cache_enable_data();
#endif

  /*
   *  initialize the device driver parameters
   */
  bsp_clicks_per_usec 	   = 10;  /* for 40MHz extclk */
  bsp_serial_per_sec  	   = 40000000;
  bsp_serial_external_clock  = 0;
  bsp_serial_xon_xoff 	   = 0;
  bsp_serial_cts_rts 	   = 0;
  bsp_serial_rate 	   = 9600;
  bsp_timer_average_overhead = 3;
  bsp_timer_least_valid 	   = 3;
  bsp_clock_speed 	   = 40000000;

#ifdef REV_0_2
  /* set up some board specific registers */
  m8260.siumcr &= 0xF3FFFFFF;		/* set TBEN ** BUG FIX ** */
  m8260.siumcr |= 0x08000000;
#endif

  /* use BRG1 to generate 32kHz timebase */
/*
  m8260.brgc1 = M8260_BRG_EN + (uint32_t)(((uint16_t)((40016384)/(32768)) - 1) << 1) + 0;
*/

#ifdef SHOW_MORE_INIT_SETTINGS
  printk("Exit from bspstart\n");
#endif

}
Ejemplo n.º 24
0
void  rtems_irq_mngt_init(void)
{
    int 			i;
    interrupt_gate_descriptor* 	idt_entry_tbl;
    unsigned int                limit;
    rtems_interrupt_level       level;

    i386_get_info_from_IDTR(&idt_entry_tbl, &limit);

    /* Convert into number of entries */
    limit = (limit + 1)/sizeof(interrupt_gate_descriptor);

    if(limit != IDT_SIZE) {
       printk("IDT table size mismatch !!! System locked\n");
       while(1);
    }

    rtems_interrupt_disable(level);

    /*
     * Init the complete IDT vector table with defaultRawIrq value
     */
    for (i = 0; i < IDT_SIZE ; i++) {
      idtHdl[i] 	 = defaultRawIrq;
      idtHdl[i].idtIndex = i;
    }

    raw_initial_config.idtSize = IDT_SIZE;
    raw_initial_config.defaultRawEntry = defaultRawIrq;
    raw_initial_config.rawIrqHdlTbl = idtHdl;

    if (!i386_init_idt (&raw_initial_config)) {
      /*
       * put something here that will show the failure...
       */
      printk("Unable to initialize IDT!!! System locked\n");
      while (1);
    }
    /*
     * Patch the entry that will be used by RTEMS for interrupt management
     * with RTEMS prologue.
     */
    for (i = 0; i < BSP_IRQ_LINES_NUMBER; i++) {
      create_interrupt_gate_descriptor(&idtEntry, rtemsIrq[i]);
      idt_entry_tbl[i + BSP_ASM_IRQ_VECTOR_BASE] = idtEntry;
    }
    /*
     * At this point we have completed the initialization of IDT
     * with raw handlers.  We must now initialize the higher level
     * interrupt management.
     */

    /*
     * Init initial Interrupt management config
     */
    bsp_interrupt_initialize();

    /*
     * #define DEBUG
     */
#ifdef DEBUG
    {
      /*
       * following adresses should be the same
       */
      unsigned tmp;

      printk("idt_entry_tbl =  %x Interrupt_descriptor_table addr = %x\n",
	     idt_entry_tbl, &Interrupt_descriptor_table);
      tmp = (unsigned) get_hdl_from_vector (BSP_ASM_IRQ_VECTOR_BASE + BSP_PERIODIC_TIMER);
      printk("clock isr address from idt = %x should be %x\n",
	     tmp, (unsigned) rtems_irq_prologue_0);
    }
    printk("i8259s_cache = %x\n", * (unsigned short*) &i8259s_cache);
    BSP_wait_polled_input();
#endif
}
Ejemplo n.º 25
0
void bsp_start(void)
{
  ppc_cpu_id_t myCpu;
  ppc_cpu_revision_t myCpuRevision;

  /*
   * Get CPU identification dynamically. Note that the get_ppc_cpu_type()
   * function store the result in global variables so that it can be used
   * later...
   */
  myCpu         = get_ppc_cpu_type();
  myCpuRevision = get_ppc_cpu_revision();

  #if defined(HAS_UBOOT) && defined(SHOW_MORE_INIT_SETTINGS)
    {
      void dumpUBootBDInfo( bd_t * );
      dumpUBootBDInfo( &bsp_uboot_board_info );
    }
  #endif

  cpu_init();

  if(get_ppc_cpu_revision() >= 0x2014) {
    /* Special settings for MPC5200B (B variant) */
    uint32_t xlb_cfg = mpc5200.config;

    /* XXX: The Freescale documentation for BSDIS seems to be wrong */
    xlb_cfg |= XLB_CFG_BSDIS;

    xlb_cfg &= ~XLB_CFG_PLDIS;

    mpc5200.config = xlb_cfg;
  }

  bsp_time_base_frequency = XLB_CLOCK / 4;
  bsp_clicks_per_usec    = (XLB_CLOCK/4000000);

  /* Initialize exception handler */
  ppc_exc_cache_wb_check = 0;
  ppc_exc_initialize(
    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
    (uintptr_t) bsp_interrupt_stack_start,
    (uintptr_t) bsp_interrupt_stack_size
  );
  ppc_exc_set_handler(ASM_ALIGN_VECTOR, ppc_exc_alignment_handler);

  /* Initalize interrupt support */
  bsp_interrupt_initialize();

  /*
   *  If the BSP was built with IRQ benchmarking enabled,
   *  then intialize it.
   */
  #if (BENCHMARK_IRQ_PROCESSING == 1)
    BSP_IRQ_Benchmarking_Reset();
  #endif

  #ifdef SHOW_MORE_INIT_SETTINGS
    printk("Exit from bspstart\n");
  #endif
}
Ejemplo n.º 26
0
void bsp_start(void)
{
  init_main_osc();
  init_gpio();
  bsp_interrupt_initialize();
}
Ejemplo n.º 27
0
void bsp_start( void )
{
  bsp_interrupt_initialize();
  altera_cyclone_v_nocache_init_heap();
}