static int __devinit imx_keypad_probe(struct platform_device *pdev) { const struct matrix_keymap_data *keymap_data = pdev->dev.platform_data; struct imx_keypad *keypad; struct input_dev *input_dev; struct resource *res; int irq, error, i; if (keymap_data == NULL) { dev_err(&pdev->dev, "no keymap defined\n"); return -EINVAL; } irq = platform_get_irq(pdev, 0); if (irq < 0) { dev_err(&pdev->dev, "no irq defined in platform data\n"); return -EINVAL; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res == NULL) { dev_err(&pdev->dev, "no I/O memory defined in platform data\n"); return -EINVAL; } res = request_mem_region(res->start, resource_size(res), pdev->name); if (res == NULL) { dev_err(&pdev->dev, "failed to request I/O memory\n"); return -EBUSY; } input_dev = input_allocate_device(); if (!input_dev) { dev_err(&pdev->dev, "failed to allocate the input device\n"); error = -ENOMEM; goto failed_rel_mem; } keypad = kzalloc(sizeof(struct imx_keypad), GFP_KERNEL); if (!keypad) { dev_err(&pdev->dev, "not enough memory for driver data\n"); error = -ENOMEM; goto failed_free_input; } keypad->input_dev = input_dev; keypad->irq = irq; keypad->stable_count = 0; setup_timer(&keypad->check_matrix_timer, imx_keypad_check_for_events, (unsigned long) keypad); keypad->mmio_base = ioremap(res->start, resource_size(res)); if (keypad->mmio_base == NULL) { dev_err(&pdev->dev, "failed to remap I/O memory\n"); error = -ENOMEM; goto failed_free_priv; } keypad->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(keypad->clk)) { dev_err(&pdev->dev, "failed to get keypad clock\n"); error = PTR_ERR(keypad->clk); goto failed_unmap; } /* Search for rows and cols enabled */ for (i = 0; i < keymap_data->keymap_size; i++) { keypad->rows_en_mask |= 1 << KEY_ROW(keymap_data->keymap[i]); keypad->cols_en_mask |= 1 << KEY_COL(keymap_data->keymap[i]); } if (keypad->rows_en_mask > ((1 << MAX_MATRIX_KEY_ROWS) - 1) || keypad->cols_en_mask > ((1 << MAX_MATRIX_KEY_COLS) - 1)) { dev_err(&pdev->dev, "invalid key data (too many rows or colums)\n"); error = -EINVAL; goto failed_clock_put; } dev_dbg(&pdev->dev, "enabled rows mask: %x\n", keypad->rows_en_mask); dev_dbg(&pdev->dev, "enabled cols mask: %x\n", keypad->cols_en_mask); /* Init the Input device */ input_dev->name = pdev->name; input_dev->id.bustype = BUS_HOST; input_dev->dev.parent = &pdev->dev; input_dev->open = imx_keypad_open; input_dev->close = imx_keypad_close; error = matrix_keypad_build_keymap(keymap_data, NULL, MAX_MATRIX_KEY_ROWS, MAX_MATRIX_KEY_COLS, keypad->keycodes, input_dev); if (error) { dev_err(&pdev->dev, "failed to build keymap\n"); goto failed_clock_put; } __set_bit(EV_REP, input_dev->evbit); input_set_capability(input_dev, EV_MSC, MSC_SCAN); input_set_drvdata(input_dev, keypad); /* Ensure that the keypad will stay dormant until opened */ imx_keypad_inhibit(keypad); error = request_irq(irq, imx_keypad_irq_handler, 0, pdev->name, keypad); if (error) { dev_err(&pdev->dev, "failed to request IRQ\n"); goto failed_clock_put; } /* Register the input device */ error = input_register_device(input_dev); if (error) { dev_err(&pdev->dev, "failed to register input device\n"); goto failed_free_irq; } platform_set_drvdata(pdev, keypad); device_init_wakeup(&pdev->dev, 1); return 0; failed_free_irq: free_irq(irq, pdev); failed_clock_put: clk_put(keypad->clk); failed_unmap: iounmap(keypad->mmio_base); failed_free_priv: kfree(keypad); failed_free_input: input_free_device(input_dev); failed_rel_mem: release_mem_region(res->start, resource_size(res)); return error; }
void __init_or_cpufreq s5pv210_setup_clocks(void) { struct clk *xtal_clk; unsigned long vpllsrc; unsigned long armclk; unsigned long hclk_msys; unsigned long hclk_dsys; unsigned long hclk_psys; unsigned long pclk_msys; unsigned long pclk_dsys; unsigned long pclk_psys; unsigned long apll; unsigned long mpll; unsigned long epll; unsigned long vpll; unsigned int ptr; u32 clkdiv0, clkdiv1; /* Set functions for clk_fout_epll */ clk_fout_epll.enable = s5p_epll_enable; clk_fout_epll.ops = &s5pv210_epll_ops; printk(KERN_DEBUG "%s: registering clocks\n", __func__); clkdiv0 = __raw_readl(S5P_CLK_DIV0); clkdiv1 = __raw_readl(S5P_CLK_DIV1); printk(KERN_DEBUG "%s: clkdiv0 = %08x, clkdiv1 = %08x\n", __func__, clkdiv0, clkdiv1); xtal_clk = clk_get(NULL, "xtal"); BUG_ON(IS_ERR(xtal_clk)); xtal = clk_get_rate(xtal_clk); clk_put(xtal_clk); printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); apll = s5p_get_pll45xx(xtal, __raw_readl(S5P_APLL_CON), pll_4508); mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); epll = s5p_get_pll46xx(xtal, __raw_readl(S5P_EPLL_CON), __raw_readl(S5P_EPLL_CON1), pll_4600); vpllsrc = clk_get_rate(&clk_vpllsrc.clk); vpll = s5p_get_pll45xx(vpllsrc, __raw_readl(S5P_VPLL_CON), pll_4502); clk_fout_apll.ops = &clk_fout_apll_ops; clk_fout_mpll.rate = mpll; clk_fout_epll.rate = epll; clk_fout_vpll.rate = vpll; printk(KERN_INFO "S5PV210: PLL settings, A=%ld, M=%ld, E=%ld V=%ld", apll, mpll, epll, vpll); armclk = clk_get_rate(&clk_armclk.clk); hclk_msys = clk_get_rate(&clk_hclk_msys.clk); hclk_dsys = clk_get_rate(&clk_hclk_dsys.clk); hclk_psys = clk_get_rate(&clk_hclk_psys.clk); pclk_msys = clk_get_rate(&clk_pclk_msys.clk); pclk_dsys = clk_get_rate(&clk_pclk_dsys.clk); pclk_psys = clk_get_rate(&clk_pclk_psys.clk); printk(KERN_INFO "S5PV210: ARMCLK=%ld, HCLKM=%ld, HCLKD=%ld\n" "HCLKP=%ld, PCLKM=%ld, PCLKD=%ld, PCLKP=%ld\n", armclk, hclk_msys, hclk_dsys, hclk_psys, pclk_msys, pclk_dsys, pclk_psys); clk_f.rate = armclk; clk_h.rate = hclk_psys; clk_p.rate = pclk_psys; for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) s3c_set_clksrc(&clksrcs[ptr], true); }
static int __devinit s5p_ehci_probe(struct platform_device *pdev) { struct s5p_ehci_platdata *pdata; struct s5p_ehci_hcd *s5p_ehci; struct usb_hcd *hcd; struct ehci_hcd *ehci; struct resource *res; int irq; int err; pdata = pdev->dev.platform_data; if (!pdata) { dev_err(&pdev->dev, "No platform data defined\n"); return -EINVAL; } s5p_ehci = kzalloc(sizeof(struct s5p_ehci_hcd), GFP_KERNEL); if (!s5p_ehci) return -ENOMEM; s5p_ehci->dev = &pdev->dev; hcd = usb_create_hcd(&s5p_ehci_hc_driver, &pdev->dev, dev_name(&pdev->dev)); if (!hcd) { dev_err(&pdev->dev, "Unable to create HCD\n"); err = -ENOMEM; goto fail_hcd; } s5p_ehci->hcd = hcd; s5p_ehci->clk = clk_get(&pdev->dev, "usbhost"); if (IS_ERR(s5p_ehci->clk)) { dev_err(&pdev->dev, "Failed to get usbhost clock\n"); err = PTR_ERR(s5p_ehci->clk); goto fail_clk; } err = clk_enable(s5p_ehci->clk); if (err) goto fail_clken; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&pdev->dev, "Failed to get I/O memory\n"); err = -ENXIO; goto fail_io; } hcd->rsrc_start = res->start; hcd->rsrc_len = resource_size(res); hcd->regs = ioremap(res->start, resource_size(res)); if (!hcd->regs) { dev_err(&pdev->dev, "Failed to remap I/O memory\n"); err = -ENOMEM; goto fail_io; } irq = platform_get_irq(pdev, 0); if (!irq) { dev_err(&pdev->dev, "Failed to get IRQ\n"); err = -ENODEV; goto fail; } platform_set_drvdata(pdev, s5p_ehci); s5p_ehci_phy_init(pdev); ehci = hcd_to_ehci(hcd); ehci->caps = hcd->regs; ehci->regs = hcd->regs + HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase)); dbg_hcs_params(ehci, "reset"); dbg_hcc_params(ehci, "reset"); /* cache this readonly data; minimize chip reads */ ehci->hcs_params = readl(&ehci->caps->hcs_params); err = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED); if (err) { dev_err(&pdev->dev, "Failed to add USB HCD\n"); goto fail; } create_ehci_sys_file(ehci); s5p_ehci->power_on = 1; #ifdef CONFIG_USB_SUSPEND pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); #endif #if defined(CONFIG_LINK_DEVICE_HSIC) || defined(CONFIG_LINK_DEVICE_USB) /* for cp enumeration */ pm_runtime_forbid(&pdev->dev); /*HSIC IPC control the ACTIVE_STATE*/ if (pdata && pdata->noti_host_states) pdata->noti_host_states(pdev, S5P_HOST_ON); #endif return 0; fail: iounmap(hcd->regs); fail_io: clk_disable(s5p_ehci->clk); fail_clken: clk_put(s5p_ehci->clk); fail_clk: usb_put_hcd(hcd); fail_hcd: kfree(s5p_ehci); return err; }
static int snddev_icodec_open_rx(struct snddev_icodec_state *icodec) { int trc; int afe_channel_mode; union afe_port_config afe_config; struct snddev_icodec_drv_state *drv = &snddev_icodec_drv; wake_lock(&drv->rx_idlelock); if (drv->snddev_vreg) { if (!strcmp(icodec->data->name, "headset_stereo_rx")) vreg_mode_vote(drv->snddev_vreg, 1, SNDDEV_LOW_POWER_MODE); else vreg_mode_vote(drv->snddev_vreg, 1, SNDDEV_HIGH_POWER_MODE); } msm_snddev_rx_mclk_request(); drv->rx_osrclk = clk_get(0, "i2s_spkr_osr_clk"); if (IS_ERR(drv->rx_osrclk)) pr_err("%s master clock Error\n", __func__); trc = clk_set_rate(drv->rx_osrclk, SNDDEV_ICODEC_CLK_RATE(icodec->sample_rate)); //(+)dragonball printk("SNDDEV_ICODEC_CLK_RATE(icodec->sample_rate)=>%d",icodec->sample_rate); if (IS_ERR_VALUE(trc)) { pr_err("ERROR setting m clock1\n"); goto error_invalid_freq; } clk_enable(drv->rx_osrclk); drv->rx_bitclk = clk_get(0, "i2s_spkr_bit_clk"); if (IS_ERR(drv->rx_bitclk)) pr_err("%s clock Error\n", __func__); /* Master clock = Sample Rate * OSR rate bit clock * OSR Rate bit clock = bit/sample * channel master * clock / bit clock = divider value = 8 */ if (msm_codec_i2s_slave_mode) { pr_info("%s: configuring bit clock for slave mode\n", __func__); trc = clk_set_rate(drv->rx_bitclk, 0); } else trc = clk_set_rate(drv->rx_bitclk, 8); if (IS_ERR_VALUE(trc)) { pr_err("ERROR setting m clock1\n"); goto error_adie; } clk_enable(drv->rx_bitclk); if (icodec->data->voltage_on) icodec->data->voltage_on(); /* Configure ADIE */ trc = adie_codec_open(icodec->data->profile, &icodec->adie_path); if (IS_ERR_VALUE(trc)) pr_err("%s: adie codec open failed\n", __func__); else adie_codec_setpath(icodec->adie_path, icodec->sample_rate, 256); /* OSR default to 256, can be changed for power optimization * If OSR is to be changed, need clock API for setting the divider */ //(+)dragonball printk("adie_codec_open::profile=>%s,adie_path=>%s ",icodec->data->profile,icodec->adie_path ); switch (icodec->data->channel_mode) { case 2: afe_channel_mode = MSM_AFE_STEREO; break; case 1: default: afe_channel_mode = MSM_AFE_MONO; break; } afe_config.mi2s.channel = afe_channel_mode; afe_config.mi2s.bitwidth = 16; afe_config.mi2s.line = 1; if (msm_codec_i2s_slave_mode) afe_config.mi2s.ws = 0; else afe_config.mi2s.ws = 1; trc = afe_open(icodec->data->copp_id, &afe_config, icodec->sample_rate); if (IS_ERR_VALUE(trc)) pr_err("%s: afe open failed, trc = %d\n", __func__, trc); /* Enable ADIE */ if (icodec->adie_path) { adie_codec_proceed_stage(icodec->adie_path, ADIE_CODEC_DIGITAL_READY); adie_codec_proceed_stage(icodec->adie_path, ADIE_CODEC_DIGITAL_ANALOG_READY); } if (msm_codec_i2s_slave_mode) adie_codec_set_master_mode(icodec->adie_path, 1); else adie_codec_set_master_mode(icodec->adie_path, 0); /* Enable power amplifier */ if (icodec->data->pamp_on) { if (icodec->data->pamp_on()) { pr_err("%s: Error turning on rx power\n", __func__); goto error_pamp; } } icodec->enabled = 1; wake_unlock(&drv->rx_idlelock); return 0; error_pamp: error_adie: clk_disable(drv->rx_osrclk); error_invalid_freq: pr_err("%s: encounter error\n", __func__); wake_unlock(&drv->rx_idlelock); return -ENODEV; }
static PVRSRV_ERROR AcquireGPTimer(SYS_SPECIFIC_DATA *psSysSpecData) { #if defined(PVR_OMAP4_TIMING_PRCM) struct clk *psCLK; IMG_INT res; struct clk *sys_ck; IMG_INT rate; #endif PVRSRV_ERROR eError; IMG_CPU_PHYADDR sTimerRegPhysBase; IMG_HANDLE hTimerEnable; IMG_UINT32 *pui32TimerEnable; PVR_ASSERT(psSysSpecData->sTimerRegPhysBase.uiAddr == 0); #if defined(PVR_OMAP4_TIMING_PRCM) psCLK = clk_get(NULL, "gpt11_fck"); if (IS_ERR(psCLK)) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 functional clock")); goto ExitError; } psSysSpecData->psGPT11_FCK = psCLK; psCLK = clk_get(NULL, "gpt11_ick"); if (IS_ERR(psCLK)) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get GPTIMER11 interface clock")); goto ExitError; } psSysSpecData->psGPT11_ICK = psCLK; sys_ck = clk_get(NULL, "sys_clkin_ck"); if (IS_ERR(sys_ck)) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't get System clock")); goto ExitError; } if(clk_get_parent(psSysSpecData->psGPT11_FCK) != sys_ck) { PVR_TRACE(("Setting GPTIMER11 parent to System Clock")); res = clk_set_parent(psSysSpecData->psGPT11_FCK, sys_ck); if (res < 0) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't set GPTIMER11 parent clock (%d)", res)); goto ExitError; } } rate = clk_get_rate(psSysSpecData->psGPT11_FCK); PVR_TRACE(("GPTIMER11 clock is %dMHz", HZ_TO_MHZ(rate))); res = clk_enable(psSysSpecData->psGPT11_FCK); if (res < 0) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 functional clock (%d)", res)); goto ExitError; } res = clk_enable(psSysSpecData->psGPT11_ICK); if (res < 0) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: Couldn't enable GPTIMER11 interface clock (%d)", res)); goto ExitDisableGPT11FCK; } #endif sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_TSICR_SYS_PHYS_BASE; pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase, 4, PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, &hTimerEnable); if (pui32TimerEnable == IMG_NULL) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed")); goto ExitDisableGPT11ICK; } if(!(*pui32TimerEnable & 4)) { PVR_TRACE(("Setting GPTIMER11 mode to posted (currently is non-posted)")); *pui32TimerEnable |= 4; } OSUnMapPhysToLin(pui32TimerEnable, 4, PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, hTimerEnable); sTimerRegPhysBase.uiAddr = SYS_OMAP4430_GP11TIMER_ENABLE_SYS_PHYS_BASE; pui32TimerEnable = OSMapPhysToLin(sTimerRegPhysBase, 4, PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, &hTimerEnable); if (pui32TimerEnable == IMG_NULL) { PVR_DPF((PVR_DBG_ERROR, "EnableSystemClocks: OSMapPhysToLin failed")); goto ExitDisableGPT11ICK; } *pui32TimerEnable = 3; OSUnMapPhysToLin(pui32TimerEnable, 4, PVRSRV_HAP_KERNEL_ONLY|PVRSRV_HAP_UNCACHED, hTimerEnable); psSysSpecData->sTimerRegPhysBase = sTimerRegPhysBase; eError = PVRSRV_OK; goto Exit; ExitDisableGPT11ICK: #if defined(PVR_OMAP4_TIMING_PRCM) clk_disable(psSysSpecData->psGPT11_ICK); ExitDisableGPT11FCK: clk_disable(psSysSpecData->psGPT11_FCK); ExitError: #endif eError = PVRSRV_ERROR_CLOCK_REQUEST_FAILED; Exit: return eError; }
static int msm_ehci_init_clocks(struct msm_hcd *mhcd, u32 init) { int ret = 0; if (!init) goto put_clocks; /* 60MHz alt_core_clk is for LINK to be used during PHY RESET */ mhcd->alt_core_clk = clk_get(mhcd->dev, "alt_core_clk"); if (IS_ERR(mhcd->alt_core_clk)) dev_dbg(mhcd->dev, "failed to get alt_core_clk\n"); else clk_set_rate(mhcd->alt_core_clk, 60000000); /* iface_clk is required for data transfers */ mhcd->iface_clk = clk_get(mhcd->dev, "iface_clk"); if (IS_ERR(mhcd->iface_clk)) { dev_err(mhcd->dev, "failed to get iface_clk\n"); ret = PTR_ERR(mhcd->iface_clk); goto put_alt_core_clk; } /* Link's protocol engine is based on pclk which must * be running >55Mhz and frequency should also not change. * Hence, vote for maximum clk frequency on its source */ mhcd->core_clk = clk_get(mhcd->dev, "core_clk"); if (IS_ERR(mhcd->core_clk)) { dev_err(mhcd->dev, "failed to get core_clk\n"); ret = PTR_ERR(mhcd->core_clk); goto put_iface_clk; } clk_set_rate(mhcd->core_clk, INT_MAX); mhcd->phy_sleep_clk = clk_get(mhcd->dev, "sleep_clk"); if (IS_ERR(mhcd->phy_sleep_clk)) dev_dbg(mhcd->dev, "failed to get sleep_clk\n"); else clk_prepare_enable(mhcd->phy_sleep_clk); clk_prepare_enable(mhcd->core_clk); clk_prepare_enable(mhcd->iface_clk); return 0; put_clocks: if (!atomic_read(&mhcd->in_lpm)) { clk_disable_unprepare(mhcd->iface_clk); clk_disable_unprepare(mhcd->core_clk); } clk_put(mhcd->core_clk); if (!IS_ERR(mhcd->phy_sleep_clk)) { clk_disable_unprepare(mhcd->phy_sleep_clk); clk_put(mhcd->phy_sleep_clk); } put_iface_clk: clk_put(mhcd->iface_clk); put_alt_core_clk: if (!IS_ERR(mhcd->alt_core_clk)) clk_put(mhcd->alt_core_clk); return ret; }
static int omap_i2c_init(struct omap_i2c_dev *dev) { u16 psc = 0, scll = 0, sclh = 0, buf = 0; u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0; unsigned long fclk_rate = 12000000; unsigned long timeout; unsigned long internal_clk = 0; struct clk *fclk; if (dev->rev >= OMAP_I2C_OMAP1_REV_2) { /* Disable I2C controller before soft reset */ omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & ~(OMAP_I2C_CON_EN)); omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK); /* For some reason we need to set the EN bit before the * reset done bit gets set. */ timeout = jiffies + OMAP_I2C_TIMEOUT; omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & SYSS_RESETDONE_MASK)) { if (time_after(jiffies, timeout)) { dev_warn(dev->dev, "timeout waiting " "for controller reset\n"); return -ETIMEDOUT; } msleep(1); } /* SYSC register is cleared by the reset; rewrite it */ if (dev->rev == OMAP_I2C_REV_ON_2430) { omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_AUTOIDLE_MASK); } else if (dev->rev >= OMAP_I2C_REV_ON_3430) { dev->syscstate = SYSC_AUTOIDLE_MASK; dev->syscstate |= SYSC_ENAWAKEUP_MASK; dev->syscstate |= (SYSC_IDLEMODE_SMART << __ffs(SYSC_SIDLEMODE_MASK)); dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK << __ffs(SYSC_CLOCKACTIVITY_MASK)); omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate); /* * Enabling all wakup sources to stop I2C freezing on * WFI instruction. * REVISIT: Some wkup sources might not be needed. */ dev->westate = OMAP_I2C_WE_ALL; omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate); } } omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0); if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) { /* * The I2C functional clock is the armxor_ck, so there's * no need to get "armxor_ck" separately. Now, if OMAP2420 * always returns 12MHz for the functional clock, we can * do this bit unconditionally. */ fclk = clk_get(dev->dev, "fck"); fclk_rate = clk_get_rate(fclk); clk_put(fclk); /* TRM for 5912 says the I2C clock must be prescaled to be * between 7 - 12 MHz. The XOR input clock is typically * 12, 13 or 19.2 MHz. So we should have code that produces: * * XOR MHz Divider Prescaler * 12 1 0 * 13 2 1 * 19.2 2 1 */ if (fclk_rate > 12000000) psc = fclk_rate / 12000000; } if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) { /* * HSI2C controller internal clk rate should be 19.2 Mhz for * HS and for all modes on 2430. On 34xx we can use lower rate * to get longer filter period for better noise suppression. * The filter is iclk (fclk for HS) period. */ if (dev->speed > 400 || dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK) internal_clk = 19200; else if (dev->speed > 100) internal_clk = 9600; else internal_clk = 4000; fclk = clk_get(dev->dev, "fck"); fclk_rate = clk_get_rate(fclk) / 1000; clk_put(fclk); /* Compute prescaler divisor */ psc = fclk_rate / internal_clk; psc = psc - 1; /* If configured for High Speed */ if (dev->speed > 400) { unsigned long scl; /* For first phase of HS mode */ scl = internal_clk / 400; fsscll = scl - (scl / 3) - 7; fssclh = (scl / 3) - 5; /* For second phase of HS mode */ scl = fclk_rate / dev->speed; hsscll = scl - (scl / 3) - 7; hssclh = (scl / 3) - 5; } else if (dev->speed > 100) { unsigned long scl; /* Fast mode */ scl = internal_clk / dev->speed; fsscll = scl - (scl / 3) - 7; fssclh = (scl / 3) - 5; } else { /* Standard mode */ fsscll = internal_clk / (dev->speed * 2) - 7; fssclh = internal_clk / (dev->speed * 2) - 5; } scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll; sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh; } else { /* Program desired operating rate */ fclk_rate /= (psc + 1) * 1000; if (psc > 2) psc = 2; scll = fclk_rate / (dev->speed * 2) - 7 + psc; sclh = fclk_rate / (dev->speed * 2) - 7 + psc; } /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */ omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc); /* SCL low and high time values */ omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll); omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh); if (dev->fifo_size) { /* Note: setup required fifo size - 1. RTRSH and XTRSH */ buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR | (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR; omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf); } /* Take the I2C module out of reset: */ omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN); dev->errata = 0; if (dev->flags & OMAP_I2C_FLAG_APPLY_ERRATA_I207) dev->errata |= I2C_OMAP_ERRATA_I207; /* Enable interrupts */ dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY | OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK | OMAP_I2C_IE_AL) | ((dev->fifo_size) ? (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0); omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate); if (dev->flags & OMAP_I2C_FLAG_RESET_REGS_POSTIDLE) { dev->pscstate = psc; dev->scllstate = scll; dev->sclhstate = sclh; dev->bufstate = buf; } return 0; }
static int __init devices_setup(void) { u16 sw = __raw_readw(SW4140); /* select camera, monitor */ struct clk *clk; u16 fpga_out; /* register board specific self-refresh code */ sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF | SUSP_SH_RSTANDBY, &ms7724se_sdram_enter_start, &ms7724se_sdram_enter_end, &ms7724se_sdram_leave_start, &ms7724se_sdram_leave_end); /* Reset Release */ fpga_out = __raw_readw(FPGA_OUT); /* bit4: NTSC_PDN, bit5: NTSC_RESET */ fpga_out &= ~((1 << 1) | /* LAN */ (1 << 4) | /* AK8813 PDN */ (1 << 5) | /* AK8813 RESET */ (1 << 6) | /* VIDEO DAC */ (1 << 7) | /* AK4643 */ (1 << 8) | /* IrDA */ (1 << 12) | /* USB0 */ (1 << 14)); /* RMII */ __raw_writew(fpga_out | (1 << 4), FPGA_OUT); udelay(10); /* AK8813 RESET */ __raw_writew(fpga_out | (1 << 5), FPGA_OUT); udelay(10); __raw_writew(fpga_out, FPGA_OUT); /* turn on USB clocks, use external clock */ __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB); /* Let LED9 show STATUS2 */ gpio_request(GPIO_FN_STATUS2, NULL); /* Lit LED10 show STATUS0 */ gpio_request(GPIO_FN_STATUS0, NULL); /* Lit LED11 show PDSTATUS */ gpio_request(GPIO_FN_PDSTATUS, NULL); /* enable USB0 port */ __raw_writew(0x0600, 0xa40501d4); /* enable USB1 port */ __raw_writew(0x0600, 0xa4050192); /* enable IRQ 0,1,2 */ gpio_request(GPIO_FN_INTC_IRQ0, NULL); gpio_request(GPIO_FN_INTC_IRQ1, NULL); gpio_request(GPIO_FN_INTC_IRQ2, NULL); /* enable SCIFA3 */ gpio_request(GPIO_FN_SCIF3_I_SCK, NULL); gpio_request(GPIO_FN_SCIF3_I_RXD, NULL); gpio_request(GPIO_FN_SCIF3_I_TXD, NULL); gpio_request(GPIO_FN_SCIF3_I_CTS, NULL); gpio_request(GPIO_FN_SCIF3_I_RTS, NULL); /* enable LCDC */ gpio_request(GPIO_FN_LCDD23, NULL); gpio_request(GPIO_FN_LCDD22, NULL); gpio_request(GPIO_FN_LCDD21, NULL); gpio_request(GPIO_FN_LCDD20, NULL); gpio_request(GPIO_FN_LCDD19, NULL); gpio_request(GPIO_FN_LCDD18, NULL); gpio_request(GPIO_FN_LCDD17, NULL); gpio_request(GPIO_FN_LCDD16, NULL); gpio_request(GPIO_FN_LCDD15, NULL); gpio_request(GPIO_FN_LCDD14, NULL); gpio_request(GPIO_FN_LCDD13, NULL); gpio_request(GPIO_FN_LCDD12, NULL); gpio_request(GPIO_FN_LCDD11, NULL); gpio_request(GPIO_FN_LCDD10, NULL); gpio_request(GPIO_FN_LCDD9, NULL); gpio_request(GPIO_FN_LCDD8, NULL); gpio_request(GPIO_FN_LCDD7, NULL); gpio_request(GPIO_FN_LCDD6, NULL); gpio_request(GPIO_FN_LCDD5, NULL); gpio_request(GPIO_FN_LCDD4, NULL); gpio_request(GPIO_FN_LCDD3, NULL); gpio_request(GPIO_FN_LCDD2, NULL); gpio_request(GPIO_FN_LCDD1, NULL); gpio_request(GPIO_FN_LCDD0, NULL); gpio_request(GPIO_FN_LCDDISP, NULL); gpio_request(GPIO_FN_LCDHSYN, NULL); gpio_request(GPIO_FN_LCDDCK, NULL); gpio_request(GPIO_FN_LCDVSYN, NULL); gpio_request(GPIO_FN_LCDDON, NULL); gpio_request(GPIO_FN_LCDVEPWC, NULL); gpio_request(GPIO_FN_LCDVCPWC, NULL); gpio_request(GPIO_FN_LCDRD, NULL); gpio_request(GPIO_FN_LCDLCLK, NULL); __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA); /* enable CEU0 */ gpio_request(GPIO_FN_VIO0_D15, NULL); gpio_request(GPIO_FN_VIO0_D14, NULL); gpio_request(GPIO_FN_VIO0_D13, NULL); gpio_request(GPIO_FN_VIO0_D12, NULL); gpio_request(GPIO_FN_VIO0_D11, NULL); gpio_request(GPIO_FN_VIO0_D10, NULL); gpio_request(GPIO_FN_VIO0_D9, NULL); gpio_request(GPIO_FN_VIO0_D8, NULL); gpio_request(GPIO_FN_VIO0_D7, NULL); gpio_request(GPIO_FN_VIO0_D6, NULL); gpio_request(GPIO_FN_VIO0_D5, NULL); gpio_request(GPIO_FN_VIO0_D4, NULL); gpio_request(GPIO_FN_VIO0_D3, NULL); gpio_request(GPIO_FN_VIO0_D2, NULL); gpio_request(GPIO_FN_VIO0_D1, NULL); gpio_request(GPIO_FN_VIO0_D0, NULL); gpio_request(GPIO_FN_VIO0_VD, NULL); gpio_request(GPIO_FN_VIO0_CLK, NULL); gpio_request(GPIO_FN_VIO0_FLD, NULL); gpio_request(GPIO_FN_VIO0_HD, NULL); platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20); /* enable CEU1 */ gpio_request(GPIO_FN_VIO1_D7, NULL); gpio_request(GPIO_FN_VIO1_D6, NULL); gpio_request(GPIO_FN_VIO1_D5, NULL); gpio_request(GPIO_FN_VIO1_D4, NULL); gpio_request(GPIO_FN_VIO1_D3, NULL); gpio_request(GPIO_FN_VIO1_D2, NULL); gpio_request(GPIO_FN_VIO1_D1, NULL); gpio_request(GPIO_FN_VIO1_D0, NULL); gpio_request(GPIO_FN_VIO1_FLD, NULL); gpio_request(GPIO_FN_VIO1_HD, NULL); gpio_request(GPIO_FN_VIO1_VD, NULL); gpio_request(GPIO_FN_VIO1_CLK, NULL); platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20); /* KEYSC */ gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); gpio_request(GPIO_FN_KEYIN4, NULL); gpio_request(GPIO_FN_KEYIN3, NULL); gpio_request(GPIO_FN_KEYIN2, NULL); gpio_request(GPIO_FN_KEYIN1, NULL); gpio_request(GPIO_FN_KEYIN0, NULL); gpio_request(GPIO_FN_KEYOUT3, NULL); gpio_request(GPIO_FN_KEYOUT2, NULL); gpio_request(GPIO_FN_KEYOUT1, NULL); gpio_request(GPIO_FN_KEYOUT0, NULL); /* enable FSI */ gpio_request(GPIO_FN_FSIMCKA, NULL); gpio_request(GPIO_FN_FSIIASD, NULL); gpio_request(GPIO_FN_FSIOASD, NULL); gpio_request(GPIO_FN_FSIIABCK, NULL); gpio_request(GPIO_FN_FSIIALRCK, NULL); gpio_request(GPIO_FN_FSIOABCK, NULL); gpio_request(GPIO_FN_FSIOALRCK, NULL); gpio_request(GPIO_FN_CLKAUDIOAO, NULL); /* set SPU2 clock to 83.4 MHz */ clk = clk_get(NULL, "spu_clk"); if (!IS_ERR(clk)) { clk_set_rate(clk, clk_round_rate(clk, 83333333)); clk_put(clk); } /* change parent of FSI A */ clk = clk_get(NULL, "fsia_clk"); if (!IS_ERR(clk)) { /* 48kHz dummy clock was used to make sure 1/1 divide */ clk_set_rate(&sh7724_fsimcka_clk, 48000); clk_set_parent(clk, &sh7724_fsimcka_clk); clk_set_rate(clk, 48000); clk_put(clk); } /* SDHI0 connected to cn7 */ gpio_request(GPIO_FN_SDHI0CD, NULL); gpio_request(GPIO_FN_SDHI0WP, NULL); gpio_request(GPIO_FN_SDHI0D3, NULL); gpio_request(GPIO_FN_SDHI0D2, NULL); gpio_request(GPIO_FN_SDHI0D1, NULL); gpio_request(GPIO_FN_SDHI0D0, NULL); gpio_request(GPIO_FN_SDHI0CMD, NULL); gpio_request(GPIO_FN_SDHI0CLK, NULL); /* SDHI1 connected to cn8 */ gpio_request(GPIO_FN_SDHI1CD, NULL); gpio_request(GPIO_FN_SDHI1WP, NULL); gpio_request(GPIO_FN_SDHI1D3, NULL); gpio_request(GPIO_FN_SDHI1D2, NULL); gpio_request(GPIO_FN_SDHI1D1, NULL); gpio_request(GPIO_FN_SDHI1D0, NULL); gpio_request(GPIO_FN_SDHI1CMD, NULL); gpio_request(GPIO_FN_SDHI1CLK, NULL); /* enable IrDA */ gpio_request(GPIO_FN_IRDA_OUT, NULL); gpio_request(GPIO_FN_IRDA_IN, NULL); /* * enable SH-Eth * * please remove J33 pin from your board !! * * ms7724 board should not use GPIO_FN_LNKSTA pin * So, This time PTX5 is set to input pin */ gpio_request(GPIO_FN_RMII_RXD0, NULL); gpio_request(GPIO_FN_RMII_RXD1, NULL); gpio_request(GPIO_FN_RMII_TXD0, NULL); gpio_request(GPIO_FN_RMII_TXD1, NULL); gpio_request(GPIO_FN_RMII_REF_CLK, NULL); gpio_request(GPIO_FN_RMII_TX_EN, NULL); gpio_request(GPIO_FN_RMII_RX_ER, NULL); gpio_request(GPIO_FN_RMII_CRS_DV, NULL); gpio_request(GPIO_FN_MDIO, NULL); gpio_request(GPIO_FN_MDC, NULL); gpio_request(GPIO_PTX5, NULL); gpio_direction_input(GPIO_PTX5); sh_eth_init(); if (sw & SW41_B) { /* 720p */ lcdc_info.ch[0].lcd_cfg = lcdc_720p_modes; lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_720p_modes); } else { /* VGA */ lcdc_info.ch[0].lcd_cfg = lcdc_vga_modes; lcdc_info.ch[0].num_cfg = ARRAY_SIZE(lcdc_vga_modes); } if (sw & SW41_A) { /* Digital monitor */ lcdc_info.ch[0].interface_type = RGB18; lcdc_info.ch[0].flags = 0; } else { /* Analog monitor */ lcdc_info.ch[0].interface_type = RGB24; lcdc_info.ch[0].flags = LCDC_FLAGS_DWPOL; } /* VOU */ gpio_request(GPIO_FN_DV_D15, NULL); gpio_request(GPIO_FN_DV_D14, NULL); gpio_request(GPIO_FN_DV_D13, NULL); gpio_request(GPIO_FN_DV_D12, NULL); gpio_request(GPIO_FN_DV_D11, NULL); gpio_request(GPIO_FN_DV_D10, NULL); gpio_request(GPIO_FN_DV_D9, NULL); gpio_request(GPIO_FN_DV_D8, NULL); gpio_request(GPIO_FN_DV_CLKI, NULL); gpio_request(GPIO_FN_DV_CLK, NULL); gpio_request(GPIO_FN_DV_VSYNC, NULL); gpio_request(GPIO_FN_DV_HSYNC, NULL); return platform_add_devices(ms7724se_devices, ARRAY_SIZE(ms7724se_devices)); }
/* * Probe for the device */ static int __init at91_mci_probe(struct platform_device *pdev) { struct mmc_host *mmc; struct at91mci_host *host; struct resource *res; int ret; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENXIO; if (!request_mem_region(res->start, resource_size(res), DRIVER_NAME)) return -EBUSY; mmc = mmc_alloc_host(sizeof(struct at91mci_host), &pdev->dev); if (!mmc) { ret = -ENOMEM; dev_dbg(&pdev->dev, "couldn't allocate mmc host\n"); goto fail6; } mmc->ops = &at91_mci_ops; mmc->f_min = 375000; mmc->f_max = 25000000; mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; mmc->caps = 0; mmc->max_blk_size = MCI_MAXBLKSIZE; mmc->max_blk_count = MCI_BLKATONCE; mmc->max_req_size = MCI_BUFSIZE; mmc->max_segs = MCI_BLKATONCE; mmc->max_seg_size = MCI_BUFSIZE; host = mmc_priv(mmc); host->mmc = mmc; host->bus_mode = 0; host->board = pdev->dev.platform_data; if (host->board->wire4) { if (at91mci_is_mci1rev2xx()) mmc->caps |= MMC_CAP_4_BIT_DATA; else dev_warn(&pdev->dev, "4 wire bus mode not supported" " - using 1 wire\n"); } host->buffer = dma_alloc_coherent(&pdev->dev, MCI_BUFSIZE, &host->physical_address, GFP_KERNEL); if (!host->buffer) { ret = -ENOMEM; dev_err(&pdev->dev, "Can't allocate transmit buffer\n"); goto fail5; } /* Add SDIO capability when available */ if (at91mci_is_mci1rev2xx()) { /* at91mci MCI1 rev2xx sdio interrupt erratum */ if (host->board->wire4 || !host->board->slot_b) mmc->caps |= MMC_CAP_SDIO_IRQ; } /* * Reserve GPIOs ... board init code makes sure these pins are set * up as GPIOs with the right direction (input, except for vcc) */ if (gpio_is_valid(host->board->det_pin)) { ret = gpio_request(host->board->det_pin, "mmc_detect"); if (ret < 0) { dev_dbg(&pdev->dev, "couldn't claim card detect pin\n"); goto fail4b; } } if (gpio_is_valid(host->board->wp_pin)) { ret = gpio_request(host->board->wp_pin, "mmc_wp"); if (ret < 0) { dev_dbg(&pdev->dev, "couldn't claim wp sense pin\n"); goto fail4; } } if (gpio_is_valid(host->board->vcc_pin)) { ret = gpio_request(host->board->vcc_pin, "mmc_vcc"); if (ret < 0) { dev_dbg(&pdev->dev, "couldn't claim vcc switch pin\n"); goto fail3; } } /* * Get Clock */ host->mci_clk = clk_get(&pdev->dev, "mci_clk"); if (IS_ERR(host->mci_clk)) { ret = -ENODEV; dev_dbg(&pdev->dev, "no mci_clk?\n"); goto fail2; } /* * Map I/O region */ host->baseaddr = ioremap(res->start, resource_size(res)); if (!host->baseaddr) { ret = -ENOMEM; goto fail1; } /* * Reset hardware */ clk_enable(host->mci_clk); /* Enable the peripheral clock */ at91_mci_disable(host); at91_mci_enable(host); /* * Allocate the MCI interrupt */ host->irq = platform_get_irq(pdev, 0); ret = request_irq(host->irq, at91_mci_irq, IRQF_SHARED, mmc_hostname(mmc), host); if (ret) { dev_dbg(&pdev->dev, "request MCI interrupt failed\n"); goto fail0; } setup_timer(&host->timer, at91_timeout_timer, (unsigned long)host); platform_set_drvdata(pdev, mmc); /* * Add host to MMC layer */ if (gpio_is_valid(host->board->det_pin)) { host->present = !gpio_get_value(host->board->det_pin); } else host->present = -1; mmc_add_host(mmc); /* * monitor card insertion/removal if we can */ if (gpio_is_valid(host->board->det_pin)) { ret = request_irq(gpio_to_irq(host->board->det_pin), at91_mmc_det_irq, 0, mmc_hostname(mmc), host); if (ret) dev_warn(&pdev->dev, "request MMC detect irq failed\n"); else device_init_wakeup(&pdev->dev, 1); } pr_debug("Added MCI driver\n"); return 0; fail0: clk_disable(host->mci_clk); iounmap(host->baseaddr); fail1: clk_put(host->mci_clk); fail2: if (gpio_is_valid(host->board->vcc_pin)) gpio_free(host->board->vcc_pin); fail3: if (gpio_is_valid(host->board->wp_pin)) gpio_free(host->board->wp_pin); fail4: if (gpio_is_valid(host->board->det_pin)) gpio_free(host->board->det_pin); fail4b: if (host->buffer) dma_free_coherent(&pdev->dev, MCI_BUFSIZE, host->buffer, host->physical_address); fail5: mmc_free_host(mmc); fail6: release_mem_region(res->start, resource_size(res)); dev_err(&pdev->dev, "probe failed, err %d\n", ret); return ret; }
static int __init brf6150_init(void) { struct brf6150_info *info; int irq, err; info = kmalloc(sizeof(struct brf6150_info), GFP_KERNEL); if (!info) return -ENOMEM; memset(info, 0, sizeof(struct brf6150_info)); brf6150_device.dev.driver_data = info; init_completion(&info->init_completion); init_completion(&info->fw_completion); info->pm_enabled = 0; info->rx_pm_enabled = 0; info->tx_pm_enabled = 0; info->garbage_bytes = 0; tasklet_init(&info->tx_task, brf6150_tx_tasklet, (unsigned long)info); spin_lock_init(&info->lock); skb_queue_head_init(&info->txq); init_timer(&info->pm_timer); info->pm_timer.function = brf6150_pm_timer; info->pm_timer.data = (unsigned long)info; exit_info = NULL; info->btinfo = omap_get_config(OMAP_TAG_NOKIA_BT, struct omap_bluetooth_config); if (info->btinfo == NULL) return -1; NBT_DBG("RESET gpio: %d\n", info->btinfo->reset_gpio); NBT_DBG("BTWU gpio: %d\n", info->btinfo->bt_wakeup_gpio); NBT_DBG("HOSTWU gpio: %d\n", info->btinfo->host_wakeup_gpio); NBT_DBG("Uart: %d\n", info->btinfo->bt_uart); NBT_DBG("sysclk: %d\n", info->btinfo->bt_sysclk); err = omap_request_gpio(info->btinfo->reset_gpio); if (err < 0) { printk(KERN_WARNING "Cannot get GPIO line %d", info->btinfo->reset_gpio); kfree(info); return err; } err = omap_request_gpio(info->btinfo->bt_wakeup_gpio); if (err < 0) { printk(KERN_WARNING "Cannot get GPIO line 0x%d", info->btinfo->bt_wakeup_gpio); omap_free_gpio(info->btinfo->reset_gpio); kfree(info); return err; } err = omap_request_gpio(info->btinfo->host_wakeup_gpio); if (err < 0) { printk(KERN_WARNING "Cannot get GPIO line %d", info->btinfo->host_wakeup_gpio); omap_free_gpio(info->btinfo->reset_gpio); omap_free_gpio(info->btinfo->bt_wakeup_gpio); kfree(info); return err; } omap_set_gpio_direction(info->btinfo->reset_gpio, 0); omap_set_gpio_direction(info->btinfo->bt_wakeup_gpio, 0); omap_set_gpio_direction(info->btinfo->host_wakeup_gpio, 1); set_irq_type(OMAP_GPIO_IRQ(info->btinfo->host_wakeup_gpio), IRQT_NOEDGE); switch (info->btinfo->bt_uart) { case 1: irq = INT_UART1; info->uart_ck = clk_get(NULL, "uart1_ck"); info->uart_base = io_p2v((unsigned long)OMAP_UART1_BASE); break; case 2: irq = INT_UART2; info->uart_ck = clk_get(NULL, "uart2_ck"); info->uart_base = io_p2v((unsigned long)OMAP_UART2_BASE); break; case 3: irq = INT_UART3; info->uart_ck = clk_get(NULL, "uart3_ck"); info->uart_base = io_p2v((unsigned long)OMAP_UART3_BASE); break; default: printk(KERN_ERR "No uart defined\n"); goto cleanup; } info->irq = irq; err = request_irq(irq, brf6150_interrupt, 0, "brf6150", (void *)info); if (err < 0) { printk(KERN_ERR "brf6150: unable to get IRQ %d\n", irq); goto cleanup; } err = request_irq(OMAP_GPIO_IRQ(info->btinfo->host_wakeup_gpio), brf6150_wakeup_interrupt, 0, "brf6150_wkup", (void *)info); if (err < 0) { printk(KERN_ERR "brf6150: unable to get wakeup IRQ %d\n", OMAP_GPIO_IRQ(info->btinfo->host_wakeup_gpio)); free_irq(irq, (void *)info); goto cleanup; } /* Register with LDM */ if (platform_device_register(&brf6150_device)) { printk(KERN_ERR "failed to register brf6150 device\n"); err = -ENODEV; goto cleanup_irq; } /* Register the driver with LDM */ if (driver_register(&brf6150_driver)) { printk(KERN_WARNING "failed to register brf6150 driver\n"); platform_device_unregister(&brf6150_device); err = -ENODEV; goto cleanup_irq; } if (brf6150_register_hdev(info) < 0) { printk(KERN_WARNING "failed to register brf6150 hci device\n"); platform_device_unregister(&brf6150_device); driver_unregister(&brf6150_driver); goto cleanup_irq; } exit_info = info; return 0; cleanup_irq: free_irq(irq, (void *)info); free_irq(OMAP_GPIO_IRQ(info->btinfo->host_wakeup_gpio), (void *)info); cleanup: omap_free_gpio(info->btinfo->reset_gpio); omap_free_gpio(info->btinfo->bt_wakeup_gpio); omap_free_gpio(info->btinfo->host_wakeup_gpio); kfree(info); return err; }
static int __init arch_setup(void) { struct clk *clk; /* register board specific self-refresh code */ sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF | SUSP_SH_RSTANDBY, &ecovec24_sdram_enter_start, &ecovec24_sdram_enter_end, &ecovec24_sdram_leave_start, &ecovec24_sdram_leave_end); /* enable STATUS0, STATUS2 and PDSTATUS */ gpio_request(GPIO_FN_STATUS0, NULL); gpio_request(GPIO_FN_STATUS2, NULL); gpio_request(GPIO_FN_PDSTATUS, NULL); /* enable SCIFA0 */ gpio_request(GPIO_FN_SCIF0_TXD, NULL); gpio_request(GPIO_FN_SCIF0_RXD, NULL); /* enable debug LED */ gpio_request(GPIO_PTG0, NULL); gpio_request(GPIO_PTG1, NULL); gpio_request(GPIO_PTG2, NULL); gpio_request(GPIO_PTG3, NULL); gpio_direction_output(GPIO_PTG0, 0); gpio_direction_output(GPIO_PTG1, 0); gpio_direction_output(GPIO_PTG2, 0); gpio_direction_output(GPIO_PTG3, 0); __raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA); /* enable SH-Eth */ gpio_request(GPIO_PTA1, NULL); gpio_direction_output(GPIO_PTA1, 1); mdelay(20); gpio_request(GPIO_FN_RMII_RXD0, NULL); gpio_request(GPIO_FN_RMII_RXD1, NULL); gpio_request(GPIO_FN_RMII_TXD0, NULL); gpio_request(GPIO_FN_RMII_TXD1, NULL); gpio_request(GPIO_FN_RMII_REF_CLK, NULL); gpio_request(GPIO_FN_RMII_TX_EN, NULL); gpio_request(GPIO_FN_RMII_RX_ER, NULL); gpio_request(GPIO_FN_RMII_CRS_DV, NULL); gpio_request(GPIO_FN_MDIO, NULL); gpio_request(GPIO_FN_MDC, NULL); gpio_request(GPIO_FN_LNKSTA, NULL); /* enable USB */ __raw_writew(0x0000, 0xA4D80000); __raw_writew(0x0000, 0xA4D90000); gpio_request(GPIO_PTB3, NULL); gpio_request(GPIO_PTB4, NULL); gpio_request(GPIO_PTB5, NULL); gpio_direction_input(GPIO_PTB3); gpio_direction_output(GPIO_PTB4, 0); gpio_direction_output(GPIO_PTB5, 0); __raw_writew(0x0600, 0xa40501d4); __raw_writew(0x0600, 0xa4050192); if (gpio_get_value(GPIO_PTB3)) { printk(KERN_INFO "USB1 function is selected\n"); usb1_common_device.name = "r8a66597_udc"; } else { printk(KERN_INFO "USB1 host is selected\n"); usb1_common_device.name = "r8a66597_hcd"; } /* enable LCDC */ gpio_request(GPIO_FN_LCDD23, NULL); gpio_request(GPIO_FN_LCDD22, NULL); gpio_request(GPIO_FN_LCDD21, NULL); gpio_request(GPIO_FN_LCDD20, NULL); gpio_request(GPIO_FN_LCDD19, NULL); gpio_request(GPIO_FN_LCDD18, NULL); gpio_request(GPIO_FN_LCDD17, NULL); gpio_request(GPIO_FN_LCDD16, NULL); gpio_request(GPIO_FN_LCDD15, NULL); gpio_request(GPIO_FN_LCDD14, NULL); gpio_request(GPIO_FN_LCDD13, NULL); gpio_request(GPIO_FN_LCDD12, NULL); gpio_request(GPIO_FN_LCDD11, NULL); gpio_request(GPIO_FN_LCDD10, NULL); gpio_request(GPIO_FN_LCDD9, NULL); gpio_request(GPIO_FN_LCDD8, NULL); gpio_request(GPIO_FN_LCDD7, NULL); gpio_request(GPIO_FN_LCDD6, NULL); gpio_request(GPIO_FN_LCDD5, NULL); gpio_request(GPIO_FN_LCDD4, NULL); gpio_request(GPIO_FN_LCDD3, NULL); gpio_request(GPIO_FN_LCDD2, NULL); gpio_request(GPIO_FN_LCDD1, NULL); gpio_request(GPIO_FN_LCDD0, NULL); gpio_request(GPIO_FN_LCDDISP, NULL); gpio_request(GPIO_FN_LCDHSYN, NULL); gpio_request(GPIO_FN_LCDDCK, NULL); gpio_request(GPIO_FN_LCDVSYN, NULL); gpio_request(GPIO_FN_LCDDON, NULL); gpio_request(GPIO_FN_LCDLCLK, NULL); __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA); gpio_request(GPIO_PTE6, NULL); gpio_request(GPIO_PTU1, NULL); gpio_request(GPIO_PTR1, NULL); gpio_request(GPIO_PTA2, NULL); gpio_direction_input(GPIO_PTE6); gpio_direction_output(GPIO_PTU1, 0); gpio_direction_output(GPIO_PTR1, 0); gpio_direction_output(GPIO_PTA2, 0); /* I/O buffer drive ability is high */ __raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA); if (gpio_get_value(GPIO_PTE6)) { /* DVI */ lcdc_info.clock_source = LCDC_CLK_EXTERNAL; lcdc_info.ch[0].clock_divider = 1, lcdc_info.ch[0].lcd_cfg.name = "DVI"; lcdc_info.ch[0].lcd_cfg.xres = 1280; lcdc_info.ch[0].lcd_cfg.yres = 720; lcdc_info.ch[0].lcd_cfg.left_margin = 220; lcdc_info.ch[0].lcd_cfg.right_margin = 110; lcdc_info.ch[0].lcd_cfg.hsync_len = 40; lcdc_info.ch[0].lcd_cfg.upper_margin = 20; lcdc_info.ch[0].lcd_cfg.lower_margin = 5; lcdc_info.ch[0].lcd_cfg.vsync_len = 5; gpio_set_value(GPIO_PTA2, 1); gpio_set_value(GPIO_PTU1, 1); } else { /* Panel */ lcdc_info.clock_source = LCDC_CLK_PERIPHERAL; lcdc_info.ch[0].clock_divider = 2, lcdc_info.ch[0].lcd_cfg.name = "Panel"; lcdc_info.ch[0].lcd_cfg.xres = 800; lcdc_info.ch[0].lcd_cfg.yres = 480; lcdc_info.ch[0].lcd_cfg.left_margin = 220; lcdc_info.ch[0].lcd_cfg.right_margin = 110; lcdc_info.ch[0].lcd_cfg.hsync_len = 70; lcdc_info.ch[0].lcd_cfg.upper_margin = 20; lcdc_info.ch[0].lcd_cfg.lower_margin = 5; lcdc_info.ch[0].lcd_cfg.vsync_len = 5; gpio_set_value(GPIO_PTR1, 1); /* FIXME * * LCDDON control is needed for Panel, * but current sh_mobile_lcdc driver doesn't control it. * It is temporary correspondence */ gpio_request(GPIO_PTF4, NULL); gpio_direction_output(GPIO_PTF4, 1); /* enable TouchScreen */ i2c_register_board_info(0, &ts_i2c_clients, 1); set_irq_type(IRQ0, IRQ_TYPE_LEVEL_LOW); } /* enable CEU0 */ gpio_request(GPIO_FN_VIO0_D15, NULL); gpio_request(GPIO_FN_VIO0_D14, NULL); gpio_request(GPIO_FN_VIO0_D13, NULL); gpio_request(GPIO_FN_VIO0_D12, NULL); gpio_request(GPIO_FN_VIO0_D11, NULL); gpio_request(GPIO_FN_VIO0_D10, NULL); gpio_request(GPIO_FN_VIO0_D9, NULL); gpio_request(GPIO_FN_VIO0_D8, NULL); gpio_request(GPIO_FN_VIO0_D7, NULL); gpio_request(GPIO_FN_VIO0_D6, NULL); gpio_request(GPIO_FN_VIO0_D5, NULL); gpio_request(GPIO_FN_VIO0_D4, NULL); gpio_request(GPIO_FN_VIO0_D3, NULL); gpio_request(GPIO_FN_VIO0_D2, NULL); gpio_request(GPIO_FN_VIO0_D1, NULL); gpio_request(GPIO_FN_VIO0_D0, NULL); gpio_request(GPIO_FN_VIO0_VD, NULL); gpio_request(GPIO_FN_VIO0_CLK, NULL); gpio_request(GPIO_FN_VIO0_FLD, NULL); gpio_request(GPIO_FN_VIO0_HD, NULL); platform_resource_setup_memory(&ceu0_device, "ceu0", 4 << 20); /* enable CEU1 */ gpio_request(GPIO_FN_VIO1_D7, NULL); gpio_request(GPIO_FN_VIO1_D6, NULL); gpio_request(GPIO_FN_VIO1_D5, NULL); gpio_request(GPIO_FN_VIO1_D4, NULL); gpio_request(GPIO_FN_VIO1_D3, NULL); gpio_request(GPIO_FN_VIO1_D2, NULL); gpio_request(GPIO_FN_VIO1_D1, NULL); gpio_request(GPIO_FN_VIO1_D0, NULL); gpio_request(GPIO_FN_VIO1_FLD, NULL); gpio_request(GPIO_FN_VIO1_HD, NULL); gpio_request(GPIO_FN_VIO1_VD, NULL); gpio_request(GPIO_FN_VIO1_CLK, NULL); platform_resource_setup_memory(&ceu1_device, "ceu1", 4 << 20); /* enable KEYSC */ gpio_request(GPIO_FN_KEYOUT5_IN5, NULL); gpio_request(GPIO_FN_KEYOUT4_IN6, NULL); gpio_request(GPIO_FN_KEYOUT3, NULL); gpio_request(GPIO_FN_KEYOUT2, NULL); gpio_request(GPIO_FN_KEYOUT1, NULL); gpio_request(GPIO_FN_KEYOUT0, NULL); gpio_request(GPIO_FN_KEYIN0, NULL); /* enable user debug switch */ gpio_request(GPIO_PTR0, NULL); gpio_request(GPIO_PTR4, NULL); gpio_request(GPIO_PTR5, NULL); gpio_request(GPIO_PTR6, NULL); gpio_direction_input(GPIO_PTR0); gpio_direction_input(GPIO_PTR4); gpio_direction_input(GPIO_PTR5); gpio_direction_input(GPIO_PTR6); #ifdef CONFIG_MFD_SH_MOBILE_SDHI /* enable SDHI0 on CN11 (needs DS2.4 set to ON) */ gpio_request(GPIO_FN_SDHI0CD, NULL); gpio_request(GPIO_FN_SDHI0WP, NULL); gpio_request(GPIO_FN_SDHI0CMD, NULL); gpio_request(GPIO_FN_SDHI0CLK, NULL); gpio_request(GPIO_FN_SDHI0D3, NULL); gpio_request(GPIO_FN_SDHI0D2, NULL); gpio_request(GPIO_FN_SDHI0D1, NULL); gpio_request(GPIO_FN_SDHI0D0, NULL); gpio_request(GPIO_PTB6, NULL); gpio_direction_output(GPIO_PTB6, 0); #if !defined(CONFIG_MMC_SH_MMCIF) /* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */ gpio_request(GPIO_FN_SDHI1CD, NULL); gpio_request(GPIO_FN_SDHI1WP, NULL); gpio_request(GPIO_FN_SDHI1CMD, NULL); gpio_request(GPIO_FN_SDHI1CLK, NULL); gpio_request(GPIO_FN_SDHI1D3, NULL); gpio_request(GPIO_FN_SDHI1D2, NULL); gpio_request(GPIO_FN_SDHI1D1, NULL); gpio_request(GPIO_FN_SDHI1D0, NULL); gpio_request(GPIO_PTB7, NULL); gpio_direction_output(GPIO_PTB7, 0); /* I/O buffer drive ability is high for SDHI1 */ __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA); #endif /* CONFIG_MMC_SH_MMCIF */ #else /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */ gpio_request(GPIO_FN_MSIOF0_TXD, NULL); gpio_request(GPIO_FN_MSIOF0_RXD, NULL); gpio_request(GPIO_FN_MSIOF0_TSCK, NULL); gpio_request(GPIO_PTM4, NULL); /* software CS control of TSYNC pin */ gpio_direction_output(GPIO_PTM4, 1); /* active low CS */ gpio_request(GPIO_PTB6, NULL); /* 3.3V power control */ gpio_direction_output(GPIO_PTB6, 0); /* disable power by default */ gpio_request(GPIO_PTY6, NULL); /* write protect */ gpio_direction_input(GPIO_PTY6); gpio_request(GPIO_PTY7, NULL); /* card detect */ gpio_direction_input(GPIO_PTY7); spi_register_board_info(spi_bus, ARRAY_SIZE(spi_bus)); #endif /* enable Video */ gpio_request(GPIO_PTU2, NULL); gpio_direction_output(GPIO_PTU2, 1); /* enable Camera */ gpio_request(GPIO_PTA3, NULL); gpio_request(GPIO_PTA4, NULL); gpio_direction_output(GPIO_PTA3, 0); gpio_direction_output(GPIO_PTA4, 0); /* enable FSI */ gpio_request(GPIO_FN_FSIMCKB, NULL); gpio_request(GPIO_FN_FSIIBSD, NULL); gpio_request(GPIO_FN_FSIOBSD, NULL); gpio_request(GPIO_FN_FSIIBBCK, NULL); gpio_request(GPIO_FN_FSIIBLRCK, NULL); gpio_request(GPIO_FN_FSIOBBCK, NULL); gpio_request(GPIO_FN_FSIOBLRCK, NULL); gpio_request(GPIO_FN_CLKAUDIOBO, NULL); /* set SPU2 clock to 83.4 MHz */ clk = clk_get(NULL, "spu_clk"); if (!IS_ERR(clk)) { clk_set_rate(clk, clk_round_rate(clk, 83333333)); clk_put(clk); } /* change parent of FSI B */ clk = clk_get(NULL, "fsib_clk"); if (!IS_ERR(clk)) { clk_register(&fsimckb_clk); clk_set_parent(clk, &fsimckb_clk); clk_set_rate(clk, 11000); clk_set_rate(&fsimckb_clk, 11000); clk_put(clk); } gpio_request(GPIO_PTU0, NULL); gpio_direction_output(GPIO_PTU0, 0); mdelay(20); /* enable motion sensor */ gpio_request(GPIO_FN_INTC_IRQ1, NULL); gpio_direction_input(GPIO_FN_INTC_IRQ1); /* set VPU clock to 166 MHz */ clk = clk_get(NULL, "vpu_clk"); if (!IS_ERR(clk)) { clk_set_rate(clk, clk_round_rate(clk, 166000000)); clk_put(clk); } /* enable IrDA */ gpio_request(GPIO_FN_IRDA_OUT, NULL); gpio_request(GPIO_FN_IRDA_IN, NULL); gpio_request(GPIO_PTU5, NULL); gpio_direction_output(GPIO_PTU5, 0); #if defined(CONFIG_MMC_SH_MMCIF) /* enable MMCIF (needs DS2.6,7 set to OFF,ON) */ gpio_request(GPIO_FN_MMC_D7, NULL); gpio_request(GPIO_FN_MMC_D6, NULL); gpio_request(GPIO_FN_MMC_D5, NULL); gpio_request(GPIO_FN_MMC_D4, NULL); gpio_request(GPIO_FN_MMC_D3, NULL); gpio_request(GPIO_FN_MMC_D2, NULL); gpio_request(GPIO_FN_MMC_D1, NULL); gpio_request(GPIO_FN_MMC_D0, NULL); gpio_request(GPIO_FN_MMC_CLK, NULL); gpio_request(GPIO_FN_MMC_CMD, NULL); gpio_request(GPIO_PTB7, NULL); gpio_direction_output(GPIO_PTB7, 0); /* I/O buffer drive ability is high for MMCIF */ __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA); #endif /* enable I2C device */ i2c_register_board_info(0, i2c0_devices, ARRAY_SIZE(i2c0_devices)); i2c_register_board_info(1, i2c1_devices, ARRAY_SIZE(i2c1_devices)); /* VOU */ gpio_request(GPIO_FN_DV_D15, NULL); gpio_request(GPIO_FN_DV_D14, NULL); gpio_request(GPIO_FN_DV_D13, NULL); gpio_request(GPIO_FN_DV_D12, NULL); gpio_request(GPIO_FN_DV_D11, NULL); gpio_request(GPIO_FN_DV_D10, NULL); gpio_request(GPIO_FN_DV_D9, NULL); gpio_request(GPIO_FN_DV_D8, NULL); gpio_request(GPIO_FN_DV_CLKI, NULL); gpio_request(GPIO_FN_DV_CLK, NULL); gpio_request(GPIO_FN_DV_VSYNC, NULL); gpio_request(GPIO_FN_DV_HSYNC, NULL); /* AK8813 power / reset sequence */ gpio_request(GPIO_PTG4, NULL); gpio_request(GPIO_PTU3, NULL); /* Reset */ gpio_direction_output(GPIO_PTG4, 0); /* Power down */ gpio_direction_output(GPIO_PTU3, 1); udelay(10); /* Power up, reset */ gpio_set_value(GPIO_PTU3, 0); udelay(10); /* Remove reset */ gpio_set_value(GPIO_PTG4, 1); return platform_add_devices(ecovec_devices, ARRAY_SIZE(ecovec_devices)); }
static int __init s3c2410ts_probe(struct platform_device *pdev) { int rc; struct s3c2410_ts_mach_info *info; struct input_dev *input_dev; int ret = 0; dev_info(&pdev->dev, "Starting\n"); info = (struct s3c2410_ts_mach_info *)pdev->dev.platform_data; if (!info) { dev_err(&pdev->dev, "Hm... too bad: no platform data for ts\n"); return -EINVAL; } #ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG printk(DEBUG_LVL "Entering s3c2410ts_init\n"); #endif adc_clock = clk_get(NULL, "adc"); if (!adc_clock) { dev_err(&pdev->dev, "failed to get adc clock source\n"); return -ENOENT; } clk_enable(adc_clock); #ifdef CONFIG_TOUCHSCREEN_S3C2410_DEBUG printk(DEBUG_LVL "got and enabled clock\n"); #endif base_addr = ioremap(S3C2410_PA_ADC,0x20); if (base_addr == NULL) { dev_err(&pdev->dev, "Failed to remap register block\n"); ret = -ENOMEM; goto bail0; } /* If we acutally are a S3C2410: Configure GPIOs */ if (!strcmp(pdev->name, "s3c2410-ts")) s3c2410_ts_connect(); if ((info->presc & 0xff) > 0) writel(S3C2410_ADCCON_PRSCEN | S3C2410_ADCCON_PRSCVL(info->presc&0xFF), base_addr + S3C2410_ADCCON); else writel(0, base_addr+S3C2410_ADCCON); /* Initialise registers */ if ((info->delay & 0xffff) > 0) writel(info->delay & 0xffff, base_addr + S3C2410_ADCDLY); writel(WAIT4INT(0), base_addr + S3C2410_ADCTSC); /* Initialise input stuff */ memset(&ts, 0, sizeof(struct s3c2410ts)); input_dev = input_allocate_device(); if (!input_dev) { dev_err(&pdev->dev, "Unable to allocate the input device\n"); ret = -ENOMEM; goto bail1; } ts.dev = input_dev; ts.dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); ts.dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); input_set_abs_params(ts.dev, ABS_X, 0, 0x3FF, 0, 0); input_set_abs_params(ts.dev, ABS_Y, 0, 0x3FF, 0, 0); input_set_abs_params(ts.dev, ABS_PRESSURE, 0, 1, 0, 0); ts.dev->name = s3c2410ts_name; ts.dev->id.bustype = BUS_RS232; ts.dev->id.vendor = 0xDEAD; ts.dev->id.product = 0xBEEF; ts.dev->id.version = S3C2410TSVERSION; ts.state = TS_STATE_STANDBY; ts.event_fifo = kfifo_alloc(TS_EVENT_FIFO_SIZE, GFP_KERNEL, NULL); if (IS_ERR(ts.event_fifo)) { ret = -EIO; goto bail2; } /* create the filter chain set up for the 2 coordinates we produce */ ts.chain = ts_filter_chain_create(pdev, info->filter_config, 2); if (IS_ERR(ts.chain)) goto bail2; ts_filter_chain_clear(ts.chain); /* Get irqs */ if (request_irq(IRQ_ADC, stylus_action, IRQF_SAMPLE_RANDOM, "s3c2410_action", ts.dev)) { dev_err(&pdev->dev, "Could not allocate ts IRQ_ADC !\n"); iounmap(base_addr); ret = -EIO; goto bail3; } if (request_irq(IRQ_TC, stylus_updown, IRQF_SAMPLE_RANDOM, "s3c2410_action", ts.dev)) { dev_err(&pdev->dev, "Could not allocate ts IRQ_TC !\n"); free_irq(IRQ_ADC, ts.dev); iounmap(base_addr); ret = -EIO; goto bail4; } dev_info(&pdev->dev, "Successfully loaded\n"); /* All went ok, so register to the input system */ rc = input_register_device(ts.dev); if (rc) { ret = -EIO; goto bail5; } return 0; bail5: free_irq(IRQ_TC, ts.dev); free_irq(IRQ_ADC, ts.dev); clk_disable(adc_clock); iounmap(base_addr); disable_irq(IRQ_TC); bail4: disable_irq(IRQ_ADC); bail3: ts_filter_chain_destroy(ts.chain); kfifo_free(ts.event_fifo); bail2: input_unregister_device(ts.dev); bail1: iounmap(base_addr); bail0: return ret; }
static int rfkill_gpio_probe(struct platform_device *pdev) { struct rfkill_gpio_data *rfkill; struct rfkill_gpio_platform_data *pdata = pdev->dev.platform_data; int ret = 0; int len = 0; if (!pdata) { pr_warn("%s: No platform data specified\n", __func__); return -EINVAL; } /* */ if (!pdata->name || (!gpio_is_valid(pdata->reset_gpio) && !gpio_is_valid(pdata->shutdown_gpio))) { pr_warn("%s: invalid platform data\n", __func__); return -EINVAL; } rfkill = kzalloc(sizeof(*rfkill), GFP_KERNEL); if (!rfkill) return -ENOMEM; if (pdata->gpio_runtime_setup) { ret = pdata->gpio_runtime_setup(pdev); if (ret) { pr_warn("%s: can't set up gpio\n", __func__); goto fail_alloc; } } rfkill->pdata = pdata; len = strlen(pdata->name); rfkill->reset_name = kzalloc(len + 7, GFP_KERNEL); if (!rfkill->reset_name) { ret = -ENOMEM; goto fail_alloc; } rfkill->shutdown_name = kzalloc(len + 10, GFP_KERNEL); if (!rfkill->shutdown_name) { ret = -ENOMEM; goto fail_reset_name; } snprintf(rfkill->reset_name, len + 6 , "%s_reset", pdata->name); snprintf(rfkill->shutdown_name, len + 9, "%s_shutdown", pdata->name); if (pdata->power_clk_name) { rfkill->pwr_clk = clk_get(&pdev->dev, pdata->power_clk_name); if (IS_ERR(rfkill->pwr_clk)) { pr_warn("%s: can't find pwr_clk.\n", __func__); goto fail_shutdown_name; } } if (gpio_is_valid(pdata->reset_gpio)) { ret = gpio_request(pdata->reset_gpio, rfkill->reset_name); if (ret) { pr_warn("%s: failed to get reset gpio.\n", __func__); goto fail_clock; } } if (gpio_is_valid(pdata->shutdown_gpio)) { ret = gpio_request(pdata->shutdown_gpio, rfkill->shutdown_name); if (ret) { pr_warn("%s: failed to get shutdown gpio.\n", __func__); goto fail_reset; } } rfkill->rfkill_dev = rfkill_alloc(pdata->name, &pdev->dev, pdata->type, &rfkill_gpio_ops, rfkill); if (!rfkill->rfkill_dev) goto fail_shutdown; ret = rfkill_register(rfkill->rfkill_dev); if (ret < 0) goto fail_rfkill; platform_set_drvdata(pdev, rfkill); dev_info(&pdev->dev, "%s device registered.\n", pdata->name); return 0; fail_rfkill: rfkill_destroy(rfkill->rfkill_dev); fail_shutdown: if (gpio_is_valid(pdata->shutdown_gpio)) gpio_free(pdata->shutdown_gpio); fail_reset: if (gpio_is_valid(pdata->reset_gpio)) gpio_free(pdata->reset_gpio); fail_clock: if (rfkill->pwr_clk) clk_put(rfkill->pwr_clk); fail_shutdown_name: kfree(rfkill->shutdown_name); fail_reset_name: kfree(rfkill->reset_name); fail_alloc: kfree(rfkill); return ret; }
static int cpm_uart_init_port(struct device_node *np, struct uart_cpm_port *pinfo) { const u32 *data; void __iomem *mem, *pram; int len; int ret; int i; data = of_get_property(np, "clock", NULL); if (data) { struct clk *clk = clk_get(NULL, (const char*)data); if (!IS_ERR(clk)) pinfo->clk = clk; } if (!pinfo->clk) { data = of_get_property(np, "fsl,cpm-brg", &len); if (!data || len != 4) { printk(KERN_ERR "CPM UART %s has no/invalid " "fsl,cpm-brg property.\n", np->name); return -EINVAL; } pinfo->brg = *data; } data = of_get_property(np, "fsl,cpm-command", &len); if (!data || len != 4) { printk(KERN_ERR "CPM UART %s has no/invalid " "fsl,cpm-command property.\n", np->name); return -EINVAL; } pinfo->command = *data; mem = of_iomap(np, 0); if (!mem) return -ENOMEM; if (of_device_is_compatible(np, "fsl,cpm1-scc-uart") || of_device_is_compatible(np, "fsl,cpm2-scc-uart")) { pinfo->sccp = mem; pinfo->sccup = pram = cpm_uart_map_pram(pinfo, np); } else if (of_device_is_compatible(np, "fsl,cpm1-smc-uart") || of_device_is_compatible(np, "fsl,cpm2-smc-uart")) { pinfo->flags |= FLAG_SMC; pinfo->smcp = mem; pinfo->smcup = pram = cpm_uart_map_pram(pinfo, np); } else { ret = -ENODEV; goto out_mem; } if (!pram) { ret = -ENOMEM; goto out_mem; } pinfo->tx_nrfifos = TX_NUM_FIFO; pinfo->tx_fifosize = TX_BUF_SIZE; pinfo->rx_nrfifos = RX_NUM_FIFO; pinfo->rx_fifosize = RX_BUF_SIZE; pinfo->port.uartclk = ppc_proc_freq; pinfo->port.mapbase = (unsigned long)mem; pinfo->port.type = PORT_CPM; pinfo->port.ops = &cpm_uart_pops, pinfo->port.iotype = UPIO_MEM; pinfo->port.fifosize = pinfo->tx_nrfifos * pinfo->tx_fifosize; spin_lock_init(&pinfo->port.lock); pinfo->port.irq = of_irq_to_resource(np, 0, NULL); if (pinfo->port.irq == NO_IRQ) { ret = -EINVAL; goto out_pram; } for (i = 0; i < NUM_GPIOS; i++) { int gpio; pinfo->gpios[i] = -1; gpio = of_get_gpio(np, i); if (gpio_is_valid(gpio)) { ret = gpio_request(gpio, "cpm_uart"); if (ret) { pr_err("can't request gpio #%d: %d\n", i, ret); continue; } if (i == GPIO_RTS || i == GPIO_DTR) ret = gpio_direction_output(gpio, 0); else ret = gpio_direction_input(gpio); if (ret) { pr_err("can't set direction for gpio #%d: %d\n", i, ret); gpio_free(gpio); continue; } pinfo->gpios[i] = gpio; } } #ifdef CONFIG_PPC_EARLY_DEBUG_CPM udbg_putc = NULL; #endif return cpm_uart_request_port(&pinfo->port); out_pram: cpm_uart_unmap_pram(pinfo, pram); out_mem: iounmap(mem); return ret; }
int gpu_clks_get(void) { struct platform_device *pdev; pdev = gpsPVRLDMDev; if (vpll_clock == NULL) { vpll_clock = clk_get(&pdev->dev, "mout_vpll"); if (IS_ERR(vpll_clock)) { PVR_DPF((PVR_DBG_ERROR, "failed to find vpll clock")); return -1; } } if (vpll_src == NULL) { vpll_src = clk_get(&pdev->dev, "vpll_src"); if (IS_ERR(vpll_src)) { PVR_DPF((PVR_DBG_ERROR, "failed to find vpll_src")); return -1; } } if (fout_vpll_clock == NULL) { fout_vpll_clock = clk_get(&pdev->dev, "fout_vpll"); if (IS_ERR(fout_vpll_clock)) { PVR_DPF((PVR_DBG_ERROR, "failed to find vpll clock")); return -1; } } if (sgx_core == NULL) { sgx_core = clk_get(&pdev->dev, "sgx_core"); if (IS_ERR(sgx_core)) { PVR_DPF((PVR_DBG_ERROR, "failed to find sgx_core clock")); return -1; } } if (sgx_hyd == NULL) { sgx_hyd = clk_get(&pdev->dev, "sgx_hyd"); if (IS_ERR(sgx_hyd)) { PVR_DPF((PVR_DBG_ERROR, "failed to find sgx_hyd clock")); return -1; } } if (mout_g3d == NULL) { mout_g3d = clk_get(&pdev->dev, "mout_g3d"); if (IS_ERR(mout_g3d)) { PVR_DPF((PVR_DBG_ERROR, "failed to find mout_g3d clock")); return -1; } } if (g3d_clock_core_sub == NULL) { g3d_clock_core_sub = clk_get(&pdev->dev, "sclk_g3d_core_sub"); if (IS_ERR(g3d_clock_core_sub)) { PVR_DPF((PVR_DBG_ERROR, "failed to find g3d core sub clock")); return -1; } } if (g3d_clock_hydra_sub == NULL) { g3d_clock_hydra_sub = clk_get(&pdev->dev, "sclk_g3d_hydra_sub"); if (IS_ERR(g3d_clock_hydra_sub)) { PVR_DPF((PVR_DBG_ERROR, "failed to find g3d hydra sub clock")); return -1; } } if (g3d_clock_core == NULL) { g3d_clock_core = clk_get(&pdev->dev, "sclk_g3d_core"); if (IS_ERR(g3d_clock_core)) { PVR_DPF((PVR_DBG_ERROR, "failed to find g3d core clock")); return -1; } } if (g3d_clock_hydra == NULL) { g3d_clock_hydra = clk_get(&pdev->dev, "sclk_g3d_hydra"); if (IS_ERR(g3d_clock_hydra)) { PVR_DPF((PVR_DBG_ERROR, "failed to find g3d hydra clock")); return -1; } } #if defined(CONFIG_EXYNOS5410_BTS) sgx_bts_base = ioremap(EXYNOS5_PA_BTS_G3D0, PAGE_SIZE); #endif return 0; }
static int lcdc_probe(struct platform_device *pdev) { struct msm_fb_data_type *mfd; struct fb_info *fbi; struct platform_device *mdp_dev = NULL; struct msm_fb_panel_data *pdata = NULL; int rc; struct clk *ebi1_clk = NULL; if (pdev->id == 0) { lcdc_pdata = pdev->dev.platform_data; pixel_mdp_clk = clk_get(&pdev->dev, "mdp_clk"); if (IS_ERR(pixel_mdp_clk)) { pr_err("Couldnt find pixel_mdp_clk\n"); return -EINVAL; } pixel_lcdc_clk = clk_get(&pdev->dev, "lcdc_clk"); if (IS_ERR(pixel_lcdc_clk)) { pr_err("Couldnt find pixel_lcdc_clk\n"); return -EINVAL; } #ifndef CONFIG_MSM_BUS_SCALING ebi1_clk = clk_get(&pdev->dev, "mem_clk"); if (IS_ERR(ebi1_clk)) return PTR_ERR(ebi1_clk); #endif return 0; } mfd = platform_get_drvdata(pdev); mfd->ebi1_clk = ebi1_clk; if (!mfd) return -ENODEV; if (mfd->key != MFD_KEY) return -EINVAL; if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST) return -ENOMEM; mdp_dev = platform_device_alloc("mdp", pdev->id); if (!mdp_dev) return -ENOMEM; cont_splash_clk_ctrl(1); /* * link to the latest pdev */ mfd->pdev = mdp_dev; mfd->dest = DISPLAY_LCDC; /* * alloc panel device data */ if (platform_device_add_data (mdp_dev, pdev->dev.platform_data, sizeof(struct msm_fb_panel_data))) { pr_err("lcdc_probe: platform_device_add_data failed!\n"); platform_device_put(mdp_dev); return -ENOMEM; } /* * data chain */ pdata = (struct msm_fb_panel_data *)mdp_dev->dev.platform_data; pdata->on = lcdc_on; pdata->off = lcdc_off; pdata->next = pdev; /* * get/set panel specific fb info */ mfd->panel_info = pdata->panel_info; if (mfd->index == 0) mfd->fb_imgType = MSMFB_DEFAULT_TYPE; else mfd->fb_imgType = MDP_RGB_565; fbi = mfd->fbi; fbi->var.pixclock = clk_round_rate(pixel_mdp_clk, mfd->panel_info.clk_rate); fbi->var.left_margin = mfd->panel_info.lcdc.h_back_porch; fbi->var.right_margin = mfd->panel_info.lcdc.h_front_porch; fbi->var.upper_margin = mfd->panel_info.lcdc.v_back_porch; fbi->var.lower_margin = mfd->panel_info.lcdc.v_front_porch; fbi->var.hsync_len = mfd->panel_info.lcdc.h_pulse_width; fbi->var.vsync_len = mfd->panel_info.lcdc.v_pulse_width; /* * set driver data */ platform_set_drvdata(mdp_dev, mfd); /* * register in mdp driver */ rc = platform_device_add(mdp_dev); if (rc) goto lcdc_probe_err; pdev_list[pdev_list_cnt++] = pdev; return 0; lcdc_probe_err: platform_device_put(mdp_dev); return rc; }
static int sprd_rtc_probe(struct platform_device *plat_dev) { int err = -ENODEV; struct resource *irq; rtc_data = kzalloc(sizeof(*rtc_data), GFP_KERNEL); if(IS_ERR(rtc_data)){ err = PTR_ERR(rtc_data); return err; }; /*ensure the rtc interrupt don't be send to Adie when there's no *rtc alarm int occur. */ sci_adi_raw_write(ANA_RTC_SPG_UPD, SPRD_RTC_LOCK); /* disable all interrupt */ sci_adi_clr(ANA_RTC_INT_EN, RTC_INT_ALL_MSK); /* enable rtc device */ rtc_data->clk = clk_get(&plat_dev->dev, "ext_32k"); if (IS_ERR(rtc_data->clk)) { err = PTR_ERR(rtc_data->clk); goto kfree_data; } err = clk_enable(rtc_data->clk); if (err < 0) goto put_clk; CLEAR_RTC_INT(RTC_INT_ALL_MSK); rtc_data->rtc = rtc_device_register("sprd_rtc", &plat_dev->dev, &sprd_rtc_ops, THIS_MODULE); if (IS_ERR(rtc_data->rtc)) { err = PTR_ERR(rtc_data->rtc); goto disable_clk; } irq = platform_get_resource(plat_dev, IORESOURCE_IRQ, 0); if(unlikely(!irq)) { dev_err(&plat_dev->dev, "no irq resource specified\n"); goto unregister_rtc; } rtc_data->irq_no = irq->start; platform_set_drvdata(plat_dev, rtc_data); err = request_irq(rtc_data->irq_no, rtc_interrupt_handler, 0, "sprd_rtc", rtc_data->rtc); if(err){ printk(KERN_ERR "RTC regist irq error\n"); goto unregister_rtc; } sprd_creat_caliberate_attr(rtc_data->rtc->dev); sprd_rtc_hwrst_set(1); sprd_rtc_set_bit_spg_counter(SPG_CNT_8SECS_RESET, 1); sprd_rtc_check_power_down(&plat_dev->dev); sprd_rtc_open(&plat_dev->dev);//test return 0; unregister_rtc: rtc_device_unregister(rtc_data->rtc); disable_clk: clk_disable(rtc_data->clk); put_clk: clk_put(rtc_data->clk); kfree_data: kfree(rtc_data); return err; }
mali_bool mali_clk_get(mali_bool bis_vpll) { if (bis_vpll == MALI_TRUE) { if (ext_xtal_clock == NULL) { ext_xtal_clock = clk_get(NULL,EXTXTALCLK_NAME); if (IS_ERR(ext_xtal_clock)) { MALI_PRINT( ("MALI Error : failed to get source ext_xtal_clock\n")); return MALI_FALSE; } clk_enable(ext_xtal_clock); } if (vpll_src_clock == NULL) { vpll_src_clock = clk_get(NULL,VPLLSRCCLK_NAME); if (IS_ERR(vpll_src_clock)) { MALI_PRINT( ("MALI Error : failed to get source vpll_src_clock\n")); return MALI_FALSE; } clk_enable(vpll_src_clock); } if (fout_vpll_clock == NULL) { fout_vpll_clock = clk_get(NULL,FOUTVPLLCLK_NAME); if (IS_ERR(fout_vpll_clock)) { MALI_PRINT( ("MALI Error : failed to get source fout_vpll_clock\n")); return MALI_FALSE; } clk_enable(fout_vpll_clock); } if (sclk_vpll_clock == NULL) { sclk_vpll_clock = clk_get(NULL,SCLVPLLCLK_NAME); if (IS_ERR(sclk_vpll_clock)) { MALI_PRINT( ("MALI Error : failed to get source sclk_vpll_clock\n")); return MALI_FALSE; } clk_enable(sclk_vpll_clock); } if (mali_parent_clock == NULL) { mali_parent_clock = clk_get(NULL, GPUMOUT1CLK_NAME); if (IS_ERR(mali_parent_clock)) { MALI_PRINT( ( "MALI Error : failed to get source mali parent clock\n")); return MALI_FALSE; } clk_enable(mali_parent_clock); } } else // mpll { if (mpll_clock == NULL) { mpll_clock = clk_get(NULL,MPLLCLK_NAME); if (IS_ERR(mpll_clock)) { MALI_PRINT( ("MALI Error : failed to get source mpll clock\n")); return MALI_FALSE; } } if (mali_parent_clock == NULL) { mali_parent_clock = clk_get(NULL, GPUMOUT0CLK_NAME); if (IS_ERR(mali_parent_clock)) { MALI_PRINT( ( "MALI Error : failed to get source mali parent clock\n")); return MALI_FALSE; } } } // mali clock get always. if (mali_clock == NULL) { mali_clock = clk_get(NULL, GPUCLK_NAME); if (IS_ERR(mali_clock)) { MALI_PRINT( ("MALI Error : failed to get source mali clock\n")); return MALI_FALSE; } } return MALI_TRUE; }
static int __devinit ehci_msm2_probe(struct platform_device *pdev) { struct usb_hcd *hcd; struct resource *res; struct msm_hcd *mhcd; const struct msm_usb_host_platform_data *pdata; char pdev_name[PDEV_NAME_LEN]; int ret; int res_gpio; dev_info(&pdev->dev, "ehci_msm2 probe\n"); /* If there is no WAN device present, we don't need to start the EHCI stack */ if(!wan_present()) return -ENODEV; if (pdev->dev.of_node) { dev_dbg(&pdev->dev, "device tree enabled\n"); pdev->dev.platform_data = ehci_msm2_dt_to_pdata(pdev); } if (!pdev->dev.platform_data) dev_dbg(&pdev->dev, "No platform data given\n"); if (!pdev->dev.dma_mask) pdev->dev.dma_mask = &ehci_msm_dma_mask; if (!pdev->dev.coherent_dma_mask) pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); hcd = usb_create_hcd(&msm_hc2_driver, &pdev->dev, dev_name(&pdev->dev)); if (!hcd) { dev_err(&pdev->dev, "Unable to create HCD\n"); return -ENOMEM; } hcd_to_bus(hcd)->skip_resume = true; hcd->irq = platform_get_irq(pdev, 0); if (hcd->irq < 0) { dev_err(&pdev->dev, "Unable to get IRQ resource\n"); ret = hcd->irq; goto put_hcd; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&pdev->dev, "Unable to get memory resource\n"); ret = -ENODEV; goto put_hcd; } hcd->rsrc_start = res->start; hcd->rsrc_len = resource_size(res); hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); if (!hcd->regs) { dev_err(&pdev->dev, "ioremap failed\n"); ret = -ENOMEM; goto put_hcd; } mhcd = hcd_to_mhcd(hcd); mhcd->dev = &pdev->dev; spin_lock_init(&mhcd->wakeup_lock); mhcd->async_irq = platform_get_irq_byname(pdev, "async_irq"); if (mhcd->async_irq < 0) { dev_dbg(&pdev->dev, "platform_get_irq for async_int failed\n"); mhcd->async_irq = 0; } else { ret = request_irq(mhcd->async_irq, msm_async_irq, IRQF_TRIGGER_RISING, "msm_ehci_host", mhcd); if (ret) { dev_err(&pdev->dev, "request irq failed (ASYNC INT)\n"); goto unmap; } disable_irq(mhcd->async_irq); } snprintf(pdev_name, PDEV_NAME_LEN, "%s.%d", pdev->name, pdev->id); mhcd->xo_clk = clk_get(&pdev->dev, "xo"); if (!IS_ERR(mhcd->xo_clk)) { ret = clk_prepare_enable(mhcd->xo_clk); } else { mhcd->xo_handle = msm_xo_get(MSM_XO_TCXO_D0, pdev_name); if (IS_ERR(mhcd->xo_handle)) { dev_err(&pdev->dev, "%s fail to get handle for X0 D0\n", __func__); ret = PTR_ERR(mhcd->xo_handle); goto free_async_irq; } else { ret = msm_xo_mode_vote(mhcd->xo_handle, MSM_XO_MODE_ON); } } if (ret) { dev_err(&pdev->dev, "%s failed to vote for TCXO %d\n", __func__, ret); goto free_xo_handle; } if (pdev->dev.of_node) { res_gpio = of_get_named_gpio(pdev->dev.of_node, "usb2,resume-gpio", 0); if (res_gpio < 0){ res_gpio = 0; goto devote_xo_handle; } mhcd->resume_gpio = res_gpio; gpio_request(mhcd->resume_gpio, "USB2_RESUME"); } else { res = platform_get_resource_byname(pdev, IORESOURCE_IO, "resume_gpio"); if (res) { dev_dbg(&pdev->dev, "resume_gpio:%d\n", res->start); mhcd->resume_gpio = res->start; } } if(pdev->dev.of_node){ res_gpio = of_get_named_gpio(pdev->dev.of_node, "usb2,wakeup-gpio", 0); if (res_gpio < 0){ res_gpio = 0; goto devote_xo_handle; } mhcd->wakeup_gpio = res_gpio; } else { res = platform_get_resource_byname(pdev, IORESOURCE_IO, "wakeup_gpio"); if (res) { dev_dbg(&pdev->dev, "wakeup gpio:%d\n", res->start); mhcd->wakeup_gpio = res->start; } } if (pdev->dev.of_node) mhcd->wakeup_irq = gpio_to_irq(mhcd->wakeup_gpio); else mhcd->wakeup_irq = platform_get_irq_byname(pdev, "wakeup_irq"); if (mhcd->wakeup_irq > 0) { dev_dbg(&pdev->dev, "wakeup irq:%d\n", res->start); irq_set_status_flags(mhcd->wakeup_irq, IRQ_NOAUTOEN); ret = request_irq(mhcd->wakeup_irq, msm_hsusb_wakeup_irq, IRQF_TRIGGER_HIGH, "msm_hsusb_wakeup", mhcd); if (ret) { dev_err(&pdev->dev, "request_irq(%d) failed:%d\n", mhcd->wakeup_irq, ret); mhcd->wakeup_irq = 0; } } else { mhcd->wakeup_irq = 0; } spin_lock_init(&mhcd->wakeup_lock); ret = msm_ehci_init_clocks(mhcd, 1); if (ret) { dev_err(&pdev->dev, "unable to initialize clocks\n"); ret = -ENODEV; goto devote_xo_handle; } ret = msm_ehci_init_vddcx(mhcd, 1); if (ret) { dev_err(&pdev->dev, "unable to initialize VDDCX\n"); ret = -ENODEV; goto deinit_clocks; } ret = msm_ehci_config_vddcx(mhcd, 1); if (ret) { dev_err(&pdev->dev, "hsusb vddcx configuration failed\n"); goto deinit_vddcx; } ret = msm_ehci_ldo_init(mhcd, 1); if (ret) { dev_err(&pdev->dev, "hsusb vreg configuration failed\n"); goto deinit_vddcx; } ret = msm_ehci_ldo_enable(mhcd, 1); if (ret) { dev_err(&pdev->dev, "hsusb vreg enable failed\n"); goto deinit_ldo; } ret = msm_ehci_init_vbus(mhcd, 1); if (ret) { dev_err(&pdev->dev, "unable to get vbus\n"); goto disable_ldo; } pdata = mhcd->dev->platform_data; if (pdata && pdata->use_sec_phy) mhcd->usb_phy_ctrl_reg = USB_PHY_CTRL2; else mhcd->usb_phy_ctrl_reg = USB_PHY_CTRL; ret = msm_hsusb_reset(mhcd); if (ret) { dev_err(&pdev->dev, "hsusb PHY initialization failed\n"); goto vbus_deinit; } if( pdata && pdata->phy_sof_workaround) { /* defer bus suspend until RH suspend */ mhcd->ehci.susp_sof_bug = 1; mhcd->ehci.resume_sof_bug = 1; } ret = usb_add_hcd(hcd, hcd->irq, IRQF_SHARED); if (ret) { dev_err(&pdev->dev, "unable to register HCD\n"); goto vbus_deinit; } if (pdata && (!pdata->dock_connect_irq || !irq_read_line(pdata->dock_connect_irq))) msm_ehci_vbus_power(mhcd, 1); device_init_wakeup(&pdev->dev, 1); wake_lock_init(&mhcd->wlock, WAKE_LOCK_SUSPEND, dev_name(&pdev->dev)); wake_lock(&mhcd->wlock); INIT_WORK(&mhcd->phy_susp_fail_work, msm_ehci_phy_susp_fail_work); /* * This pdev->dev is assigned parent of root-hub by USB core, * hence, runtime framework automatically calls this driver's * runtime APIs based on root-hub's state. */ /* configure pmic_gpio_irq for D+ change */ if (pdata && pdata->pmic_gpio_dp_irq) mhcd->pmic_gpio_dp_irq = pdata->pmic_gpio_dp_irq; if (mhcd->pmic_gpio_dp_irq) { ret = request_threaded_irq(mhcd->pmic_gpio_dp_irq, NULL, msm_ehci_host_wakeup_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, "msm_ehci_host_wakeup", mhcd); if (!ret) { disable_irq_nosync(mhcd->pmic_gpio_dp_irq); } else { dev_err(&pdev->dev, "request_irq(%d) failed: %d\n", mhcd->pmic_gpio_dp_irq, ret); mhcd->pmic_gpio_dp_irq = 0; } } if (pdata && pdata->pd_rework_installed) mhcd->flags |= ALLOW_EHCI_RETENTION; pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); return 0; vbus_deinit: msm_ehci_init_vbus(mhcd, 0); disable_ldo: msm_ehci_ldo_enable(mhcd, 0); deinit_ldo: msm_ehci_ldo_init(mhcd, 0); deinit_vddcx: msm_ehci_init_vddcx(mhcd, 0); deinit_clocks: msm_ehci_init_clocks(mhcd, 0); devote_xo_handle: if (!IS_ERR(mhcd->xo_clk)) clk_disable_unprepare(mhcd->xo_clk); else msm_xo_mode_vote(mhcd->xo_handle, MSM_XO_MODE_OFF); if(mhcd->wakeup_irq) free_irq(mhcd->wakeup_irq, mhcd); if(mhcd->resume_gpio) gpio_free(mhcd->resume_gpio); free_xo_handle: if (!IS_ERR(mhcd->xo_clk)) clk_put(mhcd->xo_clk); else msm_xo_put(mhcd->xo_handle); free_async_irq: if (mhcd->async_irq) free_irq(mhcd->async_irq, mhcd); unmap: iounmap(hcd->regs); put_hcd: usb_put_hcd(hcd); return ret; }
static int tvenc_probe(struct platform_device *pdev) { struct msm_fb_data_type *mfd; struct platform_device *mdp_dev = NULL; struct msm_fb_panel_data *pdata = NULL; int rc; if (pdev->id == 0) { tvenc_base = ioremap(pdev->resource[0].start, pdev->resource[0].end - pdev->resource[0].start + 1); if (!tvenc_base) { pr_err("tvenc_base ioremap failed!\n"); return -ENOMEM; } tvenc_pdata = pdev->dev.platform_data; tvenc_resource_initialized = 1; return 0; } if (!tvenc_resource_initialized) return -EPERM; mfd = platform_get_drvdata(pdev); if (!mfd) return -ENODEV; if (mfd->key != MFD_KEY) return -EINVAL; if (pdev_list_cnt >= MSM_FB_MAX_DEV_LIST) return -ENOMEM; if (tvenc_base == NULL) return -ENOMEM; mdp_dev = platform_device_alloc("mdp", pdev->id); if (!mdp_dev) return -ENOMEM; /* * link to the latest pdev */ mfd->pdev = mdp_dev; mfd->dest = DISPLAY_TV; /* * alloc panel device data */ if (platform_device_add_data (mdp_dev, pdev->dev.platform_data, sizeof(struct msm_fb_panel_data))) { pr_err("tvenc_probe: platform_device_add_data failed!\n"); platform_device_put(mdp_dev); return -ENOMEM; } /* * data chain */ pdata = mdp_dev->dev.platform_data; pdata->on = tvenc_on; pdata->off = tvenc_off; pdata->next = pdev; /* * get/set panel specific fb info */ mfd->panel_info = pdata->panel_info; #ifdef CONFIG_FB_MSM_MDP40 mfd->fb_imgType = MDP_RGB_565; /* base layer */ #else mfd->fb_imgType = MDP_YCRYCB_H2V1; #endif #ifdef CONFIG_MSM_BUS_SCALING if (!tvenc_bus_scale_handle && tvenc_pdata && tvenc_pdata->bus_scale_table) { tvenc_bus_scale_handle = msm_bus_scale_register_client( tvenc_pdata->bus_scale_table); if (!tvenc_bus_scale_handle) { printk(KERN_ERR "%s not able to get bus scale\n", __func__); } } #else mfd->ebi1_clk = clk_get(NULL, "ebi1_tv_clk"); if (IS_ERR(mfd->ebi1_clk)) { rc = PTR_ERR(mfd->ebi1_clk); goto tvenc_probe_err; } clk_set_rate(mfd->ebi1_clk, MSM_SYSTEM_BUS_RATE); #endif /* * set driver data */ platform_set_drvdata(mdp_dev, mfd); /* * register in mdp driver */ rc = platform_device_add(mdp_dev); if (rc) goto tvenc_probe_err; pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); pdev_list[pdev_list_cnt++] = pdev; return 0; tvenc_probe_err: #ifdef CONFIG_MSM_BUS_SCALING if (tvenc_pdata && tvenc_pdata->bus_scale_table && tvenc_bus_scale_handle > 0) msm_bus_scale_unregister_client(tvenc_bus_scale_handle); #endif platform_device_put(mdp_dev); return rc; }
/*! * Board specific initialization. */ static void __init mxc_board_init(void) { mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); mxc_ipu_data.csi_clk[0] = clk_get(NULL, "ssi_ext1_clk"); /* *ssi_ext1_clk was enbled in arch/arm/mach-mx5/clock.c, and it was kept *open to provide clock for audio codec on i.Mx53 Quickstart, but MX53 *SMD board have no needs to do that, so we close it here */ clk_disable(mxc_ipu_data.csi_clk[0]); mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); clk_put(mxc_spdif_data.spdif_core_clk); mxcsdhc1_device.resource[2].start = gpio_to_irq(MX53_SMD_SD1_CD); mxcsdhc1_device.resource[2].end = gpio_to_irq(MX53_SMD_SD1_CD); mxc_cpu_common_init(); mx53_smd_io_init(); /* power off by sending shutdown command to da9053*/ pm_power_off = da9053_power_off; mxc_register_device(&mxc_dma_device, NULL); mxc_register_device(&mxc_wdt_device, NULL); mxc_register_device(&mxcspi1_device, &mxcspi1_data); mxc_register_device(&mxci2c_devices[0], &mxci2c_data); mxc_register_device(&mxci2c_devices[1], &mxci2c_data); mxc_register_device(&mxci2c_devices[2], &mxci2c_data); mx53_smd_init_da9052(); mxc_register_device(&mxc_rtc_device, NULL); mxc_register_device(&mxc_ipu_device, &mxc_ipu_data); mxc_register_device(&mxc_ldb_device, &ldb_data); mxc_register_device(&mxc_tve_device, &tve_data); if (!mxc_fuse_get_vpu_status()) mxc_register_device(&mxcvpu_device, &mxc_vpu_data); if (!mxc_fuse_get_gpu_status()) mxc_register_device(&gpu_device, &gpu_data); mxc_register_device(&mxcscc_device, NULL); mxc_register_device(&pm_device, &smd_pm_data); mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); mxc_register_device(&busfreq_device, &bus_freq_data); mxc_register_device(&mxc_iim_device, &iim_data); mxc_register_device(&mxc_pwm2_device, NULL); mxc_register_device(&mxc_pwm1_backlight_device, &mxc_pwm_backlight_data); /* Register mmc3(eMMC) first, make it's device number be 0 to * avoid device number change by hotplug in SD(mmc1) card */ mxc_register_device(&mxcsdhc3_device, &mmc3_data); mxc_register_device(&mxcsdhc1_device, &mmc1_data); mxc_register_device(&mxcsdhc2_device, &mmc2_data); mxc_register_device(&mxc_ssi1_device, NULL); mxc_register_device(&mxc_ssi2_device, NULL); mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data); mxc_register_device(&mxc_android_pmem_device, &android_pmem_data); mxc_register_device(&mxc_android_pmem_gpu_device, &android_pmem_gpu_data); mxc_register_device(&usb_mass_storage_device, &mass_storage_data); mxc_register_device(&usb_rndis_device, &rndis_data); mxc_register_device(&android_usb_device, &android_usb_data); mxc_register_device(&ahci_fsl_device, &sata_data); /* AHCI SATA PWR EN(DCDC_5V, DCDC_3V3_BB) on SATA bus */ gpio_request(MX53_SMD_SATA_PWR_EN, "sata-pwr-en"); gpio_direction_output(MX53_SMD_SATA_PWR_EN, 1); mxc_register_device(&mxc_fec_device, &fec_data); mxc_register_device(&mxc_ptp_device, NULL); /* ASRC is only available for MX53 TO2.0 */ if (mx53_revision() >= IMX_CHIP_REVISION_2_0) { mxc_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk"); clk_put(mxc_asrc_data.asrc_core_clk); mxc_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk"); clk_put(mxc_asrc_data.asrc_audio_clk); mxc_register_device(&mxc_asrc_device, &mxc_asrc_data); } spi_device_init(); i2c_register_board_info(0, mxc_i2c0_board_info, ARRAY_SIZE(mxc_i2c0_board_info)); i2c_register_board_info(1, mxc_i2c1_board_info, ARRAY_SIZE(mxc_i2c1_board_info)); i2c_register_board_info(2, mxc_i2c2_board_info, ARRAY_SIZE(mxc_i2c2_board_info)); sgtl5000_data.ext_ram_clk = clk_get(NULL, "emi_fast_clk"); clk_put(sgtl5000_data.ext_ram_clk); mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); spdif_audio_data.ext_ram_clk = clk_get(NULL, "emi_fast_clk"); clk_put(spdif_audio_data.ext_ram_clk); mxc_register_device(&mxc_spdif_audio_device, &spdif_audio_data); mx5_set_otghost_vbus_func(mx53_gpio_usbotg_driver_vbus); mx5_usb_dr_init(); mx5_usbh1_init(); mxc_register_device(&mxc_v4l2_device, NULL); mxc_register_device(&mxc_v4l2out_device, NULL); mxc_register_device(&mxc_bt_rfkill, &mxc_bt_rfkill_data); smd_add_device_buttons(); smd_add_device_battery(); pm_i2c_init(I2C1_BASE_ADDR - MX53_OFFSET); }
static int sossi_init(struct omapfb_device *fbdev) { u32 l, k; struct clk *fck; struct clk *dpll1out_ck; int r; sossi.base = ioremap(OMAP_SOSSI_BASE, SZ_1K); if (!sossi.base) { dev_err(fbdev->dev, "can't ioremap SoSSI\n"); return -ENOMEM; } sossi.fbdev = fbdev; spin_lock_init(&sossi.lock); dpll1out_ck = clk_get(fbdev->dev, "ck_dpll1out"); if (IS_ERR(dpll1out_ck)) { dev_err(fbdev->dev, "can't get DPLL1OUT clock\n"); return PTR_ERR(dpll1out_ck); } /* * We need the parent clock rate, which we might divide further * depending on the timing requirements of the controller. See * _set_timings. */ sossi.fck_hz = clk_get_rate(dpll1out_ck); clk_put(dpll1out_ck); fck = clk_get(fbdev->dev, "ck_sossi"); if (IS_ERR(fck)) { dev_err(fbdev->dev, "can't get SoSSI functional clock\n"); return PTR_ERR(fck); } sossi.fck = fck; /* Reset and enable the SoSSI module */ l = omap_readl(MOD_CONF_CTRL_1); l |= CONF_SOSSI_RESET_R; omap_writel(l, MOD_CONF_CTRL_1); l &= ~CONF_SOSSI_RESET_R; omap_writel(l, MOD_CONF_CTRL_1); clk_enable(sossi.fck); l = omap_readl(ARM_IDLECT2); l &= ~(1 << 8); /* DMACK_REQ */ omap_writel(l, ARM_IDLECT2); l = sossi_read_reg(SOSSI_INIT2_REG); /* Enable and reset the SoSSI block */ l |= (1 << 0) | (1 << 1); sossi_write_reg(SOSSI_INIT2_REG, l); /* Take SoSSI out of reset */ l &= ~(1 << 1); sossi_write_reg(SOSSI_INIT2_REG, l); sossi_write_reg(SOSSI_ID_REG, 0); l = sossi_read_reg(SOSSI_ID_REG); k = sossi_read_reg(SOSSI_ID_REG); if (l != 0x55555555 || k != 0xaaaaaaaa) { dev_err(fbdev->dev, "invalid SoSSI sync pattern: %08x, %08x\n", l, k); r = -ENODEV; goto err; } if ((r = omap_lcdc_set_dma_callback(sossi_dma_callback, NULL)) < 0) { dev_err(fbdev->dev, "can't get LCDC IRQ\n"); r = -ENODEV; goto err; } l = sossi_read_reg(SOSSI_ID_REG); /* Component code */ l = sossi_read_reg(SOSSI_ID_REG); dev_info(fbdev->dev, "SoSSI version %d.%d initialized\n", l >> 16, l & 0xffff); l = sossi_read_reg(SOSSI_INIT1_REG); l |= (1 << 19); /* DMA_MODE */ l &= ~(1 << 31); /* REORDERING */ sossi_write_reg(SOSSI_INIT1_REG, l); if ((r = request_irq(INT_1610_SoSSI_MATCH, sossi_match_irq, IRQ_TYPE_EDGE_FALLING, "sossi_match", sossi.fbdev->dev)) < 0) { dev_err(sossi.fbdev->dev, "can't get SoSSI match IRQ\n"); goto err; } clk_disable(sossi.fck); return 0; err: clk_disable(sossi.fck); clk_put(sossi.fck); return r; }
static int snddev_icodec_open_tx(struct snddev_icodec_state *icodec) { int trc; int afe_channel_mode; union afe_port_config afe_config; struct snddev_icodec_drv_state *drv = &snddev_icodec_drv;; wake_lock(&drv->tx_idlelock); if (drv->snddev_vreg) vreg_mode_vote(drv->snddev_vreg, 1, SNDDEV_HIGH_POWER_MODE); /* Reuse pamp_on for TX platform-specific setup */ if (icodec->data->pamp_on) { if (icodec->data->pamp_on()) { pr_err("%s: Error turning on tx power\n", __func__); goto error_pamp; } } msm_snddev_tx_mclk_request(); drv->tx_osrclk = clk_get(0, "i2s_mic_osr_clk"); if (IS_ERR(drv->tx_osrclk)) pr_err("%s master clock Error\n", __func__); trc = clk_set_rate(drv->tx_osrclk, SNDDEV_ICODEC_CLK_RATE(icodec->sample_rate)); if (IS_ERR_VALUE(trc)) { pr_err("ERROR setting m clock1\n"); goto error_invalid_freq; } clk_enable(drv->tx_osrclk); drv->tx_bitclk = clk_get(0, "i2s_mic_bit_clk"); if (IS_ERR(drv->tx_bitclk)) pr_err("%s clock Error\n", __func__); /* Master clock = Sample Rate * OSR rate bit clock * OSR Rate bit clock = bit/sample * channel master * clock / bit clock = divider value = 8 */ if (msm_codec_i2s_slave_mode) { pr_info("%s: configuring bit clock for slave mode\n", __func__); trc = clk_set_rate(drv->tx_bitclk, 0); } else trc = clk_set_rate(drv->tx_bitclk, 8); clk_enable(drv->tx_bitclk); /* Enable ADIE */ trc = adie_codec_open(icodec->data->profile, &icodec->adie_path); if (IS_ERR_VALUE(trc)) pr_err("%s: adie codec open failed\n", __func__); else adie_codec_setpath(icodec->adie_path, icodec->sample_rate, 256); switch (icodec->data->channel_mode) { case 2: afe_channel_mode = MSM_AFE_STEREO; break; case 1: default: afe_channel_mode = MSM_AFE_MONO; break; } afe_config.mi2s.channel = afe_channel_mode; afe_config.mi2s.bitwidth = 16; afe_config.mi2s.line = 1; if (msm_codec_i2s_slave_mode) afe_config.mi2s.ws = 0; else afe_config.mi2s.ws = 1; trc = afe_open(icodec->data->copp_id, &afe_config, icodec->sample_rate); if (icodec->adie_path) { adie_codec_proceed_stage(icodec->adie_path, ADIE_CODEC_DIGITAL_READY); adie_codec_proceed_stage(icodec->adie_path, ADIE_CODEC_DIGITAL_ANALOG_READY); } if (msm_codec_i2s_slave_mode) adie_codec_set_master_mode(icodec->adie_path, 1); else adie_codec_set_master_mode(icodec->adie_path, 0); icodec->enabled = 1; wake_unlock(&drv->tx_idlelock); return 0; error_invalid_freq: if (icodec->data->pamp_off) icodec->data->pamp_off(); pr_err("%s: encounter error\n", __func__); error_pamp: wake_unlock(&drv->tx_idlelock); return -ENODEV; }
void __init_or_cpufreq exynos5_setup_clocks(void) { struct clk *xtal_clk; unsigned long apll; unsigned long bpll; unsigned long cpll; unsigned long mpll; unsigned long epll; unsigned long vpll; unsigned long vpllsrc; unsigned long xtal; unsigned long armclk; unsigned long mout_cdrex; unsigned long aclk_400; unsigned long aclk_333; unsigned long aclk_266; unsigned long aclk_200; unsigned long aclk_166; unsigned long aclk_66; unsigned int ptr; printk(KERN_DEBUG "%s: registering clocks\n", __func__); xtal_clk = clk_get(NULL, "xtal"); BUG_ON(IS_ERR(xtal_clk)); xtal = clk_get_rate(xtal_clk); xtal_rate = xtal; clk_put(xtal_clk); printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0)); bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0)); cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0)); mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0)); epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0), __raw_readl(EXYNOS5_EPLL_CON1)); vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk); vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0), __raw_readl(EXYNOS5_VPLL_CON1)); clk_fout_apll.ops = &exynos5_fout_apll_ops; clk_fout_bpll.rate = bpll; clk_fout_bpll_div2.rate = bpll >> 1; clk_fout_cpll.rate = cpll; clk_fout_mpll.rate = mpll; clk_fout_mpll_div2.rate = mpll >> 1; clk_fout_epll.rate = epll; clk_fout_vpll.rate = vpll; printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n" "M=%ld, E=%ld V=%ld", apll, bpll, cpll, mpll, epll, vpll); armclk = clk_get_rate(&exynos5_clk_armclk); mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk); aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk); aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk); aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk); aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk); aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk); aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk); printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n" "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n" "ACLK166=%ld, ACLK66=%ld\n", armclk, mout_cdrex, aclk_400, aclk_333, aclk_266, aclk_200, aclk_166, aclk_66); clk_fout_epll.ops = &exynos5_epll_ops; if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll)) printk(KERN_ERR "Unable to set parent %s of clock %s.\n", clk_fout_epll.name, exynos5_clk_mout_epll.clk.name); clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000); clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000); clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000); clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000); for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++) s3c_set_clksrc(&exynos5_clksrcs[ptr], true); }
/** * usbhs_omap_probe - initialize TI-based HCDs * * Allocates basic resources for this USB host controller. */ static int __devinit usbhs_omap_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct usbhs_omap_platform_data *pdata = dev->platform_data; struct usbhs_hcd_omap *omap; struct resource *res; int ret = 0; int i; if (!pdata) { dev_err(dev, "Missing platform data\n"); ret = -ENOMEM; goto end_probe; } omap = kzalloc(sizeof(*omap), GFP_KERNEL); if (!omap) { dev_err(dev, "Memory allocation failed\n"); ret = -ENOMEM; goto end_probe; } spin_lock_init(&omap->lock); for (i = 0; i < OMAP3_HS_USB_PORTS; i++) omap->platdata.port_mode[i] = pdata->port_mode[i]; omap->platdata.ehci_data = pdata->ehci_data; omap->platdata.ohci_data = pdata->ohci_data; omap->usbhost_ick = clk_get(dev, "usbhost_ick"); if (IS_ERR(omap->usbhost_ick)) { ret = PTR_ERR(omap->usbhost_ick); dev_err(dev, "usbhost_ick failed error:%d\n", ret); goto err_end; } omap->usbhost_hs_fck = clk_get(dev, "hs_fck"); if (IS_ERR(omap->usbhost_hs_fck)) { ret = PTR_ERR(omap->usbhost_hs_fck); dev_err(dev, "usbhost_hs_fck failed error:%d\n", ret); goto err_usbhost_ick; } omap->usbhost_fs_fck = clk_get(dev, "fs_fck"); if (IS_ERR(omap->usbhost_fs_fck)) { ret = PTR_ERR(omap->usbhost_fs_fck); dev_err(dev, "usbhost_fs_fck failed error:%d\n", ret); goto err_usbhost_hs_fck; } omap->usbtll_fck = clk_get(dev, "usbtll_fck"); if (IS_ERR(omap->usbtll_fck)) { ret = PTR_ERR(omap->usbtll_fck); dev_err(dev, "usbtll_fck failed error:%d\n", ret); goto err_usbhost_fs_fck; } omap->usbtll_ick = clk_get(dev, "usbtll_ick"); if (IS_ERR(omap->usbtll_ick)) { ret = PTR_ERR(omap->usbtll_ick); dev_err(dev, "usbtll_ick failed error:%d\n", ret); goto err_usbtll_fck; } omap->utmi_p1_fck = clk_get(dev, "utmi_p1_gfclk"); if (IS_ERR(omap->utmi_p1_fck)) { ret = PTR_ERR(omap->utmi_p1_fck); dev_err(dev, "utmi_p1_gfclk failed error:%d\n", ret); goto err_usbtll_ick; } omap->xclk60mhsp1_ck = clk_get(dev, "xclk60mhsp1_ck"); if (IS_ERR(omap->xclk60mhsp1_ck)) { ret = PTR_ERR(omap->xclk60mhsp1_ck); dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret); goto err_utmi_p1_fck; } omap->utmi_p2_fck = clk_get(dev, "utmi_p2_gfclk"); if (IS_ERR(omap->utmi_p2_fck)) { ret = PTR_ERR(omap->utmi_p2_fck); dev_err(dev, "utmi_p2_gfclk failed error:%d\n", ret); goto err_xclk60mhsp1_ck; } omap->xclk60mhsp2_ck = clk_get(dev, "xclk60mhsp2_ck"); if (IS_ERR(omap->xclk60mhsp2_ck)) { ret = PTR_ERR(omap->xclk60mhsp2_ck); dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret); goto err_utmi_p2_fck; } omap->usbhost_p1_fck = clk_get(dev, "usb_host_hs_utmi_p1_clk"); if (IS_ERR(omap->usbhost_p1_fck)) { ret = PTR_ERR(omap->usbhost_p1_fck); dev_err(dev, "usbhost_p1_fck failed error:%d\n", ret); goto err_xclk60mhsp2_ck; } omap->usbtll_p1_fck = clk_get(dev, "usb_tll_hs_usb_ch0_clk"); if (IS_ERR(omap->usbtll_p1_fck)) { ret = PTR_ERR(omap->usbtll_p1_fck); dev_err(dev, "usbtll_p1_fck failed error:%d\n", ret); goto err_usbhost_p1_fck; } omap->usbhost_p2_fck = clk_get(dev, "usb_host_hs_utmi_p2_clk"); if (IS_ERR(omap->usbhost_p2_fck)) { ret = PTR_ERR(omap->usbhost_p2_fck); dev_err(dev, "usbhost_p2_fck failed error:%d\n", ret); goto err_usbtll_p1_fck; } omap->usbtll_p2_fck = clk_get(dev, "usb_tll_hs_usb_ch1_clk"); if (IS_ERR(omap->usbtll_p2_fck)) { ret = PTR_ERR(omap->usbtll_p2_fck); dev_err(dev, "usbtll_p2_fck failed error:%d\n", ret); goto err_usbhost_p2_fck; } omap->init_60m_fclk = clk_get(dev, "init_60m_fclk"); if (IS_ERR(omap->init_60m_fclk)) { ret = PTR_ERR(omap->init_60m_fclk); dev_err(dev, "init_60m_fclk failed error:%d\n", ret); goto err_usbtll_p2_fck; } res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "uhh"); if (!res) { dev_err(dev, "UHH EHCI get resource failed\n"); ret = -ENODEV; goto err_init_60m_fclk; } omap->uhh_base = ioremap(res->start, resource_size(res)); if (!omap->uhh_base) { dev_err(dev, "UHH ioremap failed\n"); ret = -ENOMEM; goto err_init_60m_fclk; } res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "tll"); if (!res) { dev_err(dev, "UHH EHCI get resource failed\n"); ret = -ENODEV; goto err_tll; } omap->tll_base = ioremap(res->start, resource_size(res)); if (!omap->tll_base) { dev_err(dev, "TLL ioremap failed\n"); ret = -ENOMEM; goto err_tll; } platform_set_drvdata(pdev, omap); ret = omap_usbhs_alloc_children(pdev); if (ret) { dev_err(dev, "omap_usbhs_alloc_children failed\n"); goto err_alloc; } goto end_probe; err_alloc: iounmap(omap->tll_base); err_tll: iounmap(omap->uhh_base); err_init_60m_fclk: clk_put(omap->init_60m_fclk); err_usbtll_p2_fck: clk_put(omap->usbtll_p2_fck); err_usbhost_p2_fck: clk_put(omap->usbhost_p2_fck); err_usbtll_p1_fck: clk_put(omap->usbtll_p1_fck); err_usbhost_p1_fck: clk_put(omap->usbhost_p1_fck); err_xclk60mhsp2_ck: clk_put(omap->xclk60mhsp2_ck); err_utmi_p2_fck: clk_put(omap->utmi_p2_fck); err_xclk60mhsp1_ck: clk_put(omap->xclk60mhsp1_ck); err_utmi_p1_fck: clk_put(omap->utmi_p1_fck); err_usbtll_ick: clk_put(omap->usbtll_ick); err_usbtll_fck: clk_put(omap->usbtll_fck); err_usbhost_fs_fck: clk_put(omap->usbhost_fs_fck); err_usbhost_hs_fck: clk_put(omap->usbhost_hs_fck); err_usbhost_ick: clk_put(omap->usbhost_ick); err_end: kfree(omap); end_probe: return ret; }
static u32 res_trk_enable_videocore(void) { mutex_lock(&resource_context.lock); if (!resource_context.rail_enabled) { int rc = -1; rc = regulator_enable(resource_context.regulator); if (rc) { VCDRES_MSG_ERROR("%s(): regulator_enable failed %d\n", __func__, rc); goto bail_out; } VCDRES_MSG_LOW("%s(): regulator enable Success %d\n", __func__, rc); resource_context.pclk = clk_get(resource_context.device, "iface_clk"); if (IS_ERR(resource_context.pclk)) { VCDRES_MSG_ERROR("%s(): iface_clk get failed\n" , __func__); goto disable_regulator; } resource_context.hclk = clk_get(resource_context.device, "core_clk"); if (IS_ERR(resource_context.hclk)) { VCDRES_MSG_ERROR("%s(): core_clk get failed\n" , __func__); goto release_pclk; } resource_context.hclk_div2 = clk_get(resource_context.device, "core_div2_clk"); if (IS_ERR(resource_context.hclk_div2)) { VCDRES_MSG_ERROR("%s(): core_div2_clk get failed\n" , __func__); goto release_hclk_pclk; } if (clk_set_rate(resource_context.hclk, mfc_clk_freq_table[0])) { VCDRES_MSG_ERROR("\n pwr_rail_enable:" " set clk rate failed\n"); goto release_all_clks; } if (clk_enable(resource_context.pclk)) { VCDRES_MSG_ERROR("vidc pclk Enable failed\n"); goto release_all_clks; } if (clk_enable(resource_context.hclk)) { VCDRES_MSG_ERROR("vidc hclk Enable failed\n"); goto disable_pclk; } if (clk_enable(resource_context.hclk_div2)) { VCDRES_MSG_ERROR("vidc hclk_div2 Enable failed\n"); goto disable_hclk_pclk; } rc = clk_reset(resource_context.pclk, CLK_RESET_DEASSERT); if (rc) { VCDRES_MSG_ERROR("\n clk_reset failed %d\n", rc); goto disable_and_release_all_clks; } msleep(20); clk_disable(resource_context.pclk); clk_disable(resource_context.hclk); clk_disable(resource_context.hclk_div2); } resource_context.rail_enabled = 1; mutex_unlock(&resource_context.lock); return true; disable_and_release_all_clks: clk_disable(resource_context.hclk_div2); disable_hclk_pclk: clk_disable(resource_context.hclk); disable_pclk: clk_disable(resource_context.pclk); release_all_clks: clk_put(resource_context.hclk_div2); resource_context.hclk_div2 = NULL; release_hclk_pclk: clk_put(resource_context.hclk); resource_context.hclk = NULL; release_pclk: clk_put(resource_context.pclk); resource_context.pclk = NULL; disable_regulator: regulator_disable(resource_context.regulator); bail_out: mutex_unlock(&resource_context.lock); return false; }
static int __init sh_rtc_probe(struct platform_device *pdev) { struct sh_rtc *rtc; struct resource *res; struct rtc_time r; char clk_name[6]; int clk_id, ret; rtc = kzalloc(sizeof(struct sh_rtc), GFP_KERNEL); if (unlikely(!rtc)) return -ENOMEM; spin_lock_init(&rtc->lock); /* get periodic/carry/alarm irqs */ ret = platform_get_irq(pdev, 0); if (unlikely(ret <= 0)) { ret = -ENOENT; dev_err(&pdev->dev, "No IRQ resource\n"); goto err_badres; } rtc->periodic_irq = ret; rtc->carry_irq = platform_get_irq(pdev, 1); rtc->alarm_irq = platform_get_irq(pdev, 2); res = platform_get_resource(pdev, IORESOURCE_IO, 0); if (unlikely(res == NULL)) { ret = -ENOENT; dev_err(&pdev->dev, "No IO resource\n"); goto err_badres; } rtc->regsize = resource_size(res); rtc->res = request_mem_region(res->start, rtc->regsize, pdev->name); if (unlikely(!rtc->res)) { ret = -EBUSY; goto err_badres; } rtc->regbase = ioremap_nocache(rtc->res->start, rtc->regsize); if (unlikely(!rtc->regbase)) { ret = -EINVAL; goto err_badmap; } clk_id = pdev->id; /* With a single device, the clock id is still "rtc0" */ if (clk_id < 0) clk_id = 0; snprintf(clk_name, sizeof(clk_name), "rtc%d", clk_id); rtc->clk = clk_get(&pdev->dev, clk_name); if (IS_ERR(rtc->clk)) { /* * No error handling for rtc->clk intentionally, not all * platforms will have a unique clock for the RTC, and * the clk API can handle the struct clk pointer being * NULL. */ rtc->clk = NULL; } clk_enable(rtc->clk); rtc->capabilities = RTC_DEF_CAPABILITIES; if (pdev->dev.platform_data) { struct sh_rtc_platform_info *pinfo = pdev->dev.platform_data; /* * Some CPUs have special capabilities in addition to the * default set. Add those in here. */ rtc->capabilities |= pinfo->capabilities; } if (rtc->carry_irq <= 0) { /* register shared periodic/carry/alarm irq */ ret = request_irq(rtc->periodic_irq, sh_rtc_shared, IRQF_DISABLED, "sh-rtc", rtc); if (unlikely(ret)) { dev_err(&pdev->dev, "request IRQ failed with %d, IRQ %d\n", ret, rtc->periodic_irq); goto err_unmap; } } else { /* register periodic/carry/alarm irqs */ ret = request_irq(rtc->periodic_irq, sh_rtc_periodic, IRQF_DISABLED, "sh-rtc period", rtc); if (unlikely(ret)) { dev_err(&pdev->dev, "request period IRQ failed with %d, IRQ %d\n", ret, rtc->periodic_irq); goto err_unmap; } ret = request_irq(rtc->carry_irq, sh_rtc_interrupt, IRQF_DISABLED, "sh-rtc carry", rtc); if (unlikely(ret)) { dev_err(&pdev->dev, "request carry IRQ failed with %d, IRQ %d\n", ret, rtc->carry_irq); free_irq(rtc->periodic_irq, rtc); goto err_unmap; } ret = request_irq(rtc->alarm_irq, sh_rtc_alarm, IRQF_DISABLED, "sh-rtc alarm", rtc); if (unlikely(ret)) { dev_err(&pdev->dev, "request alarm IRQ failed with %d, IRQ %d\n", ret, rtc->alarm_irq); free_irq(rtc->carry_irq, rtc); free_irq(rtc->periodic_irq, rtc); goto err_unmap; } } platform_set_drvdata(pdev, rtc); /* everything disabled by default */ sh_rtc_irq_set_freq(&pdev->dev, 0); sh_rtc_irq_set_state(&pdev->dev, 0); sh_rtc_setaie(&pdev->dev, 0); sh_rtc_setcie(&pdev->dev, 0); rtc->rtc_dev = rtc_device_register("sh", &pdev->dev, &sh_rtc_ops, THIS_MODULE); if (IS_ERR(rtc->rtc_dev)) { ret = PTR_ERR(rtc->rtc_dev); free_irq(rtc->periodic_irq, rtc); free_irq(rtc->carry_irq, rtc); free_irq(rtc->alarm_irq, rtc); goto err_unmap; } rtc->rtc_dev->max_user_freq = 256; /* reset rtc to epoch 0 if time is invalid */ if (rtc_read_time(rtc->rtc_dev, &r) < 0) { rtc_time_to_tm(0, &r); rtc_set_time(rtc->rtc_dev, &r); } device_init_wakeup(&pdev->dev, 1); return 0; err_unmap: clk_disable(rtc->clk); clk_put(rtc->clk); iounmap(rtc->regbase); err_badmap: release_resource(rtc->res); err_badres: kfree(rtc); return ret; }
static inline void __init apollon_init_smc91x(void) { unsigned long base; unsigned int rate; struct clk *gpmc_fck; int eth_cs; int err; gpmc_fck = clk_get(NULL, "gpmc_fck"); /* Always on ENABLE_ON_INIT */ if (IS_ERR(gpmc_fck)) { WARN_ON(1); return; } clk_enable(gpmc_fck); rate = clk_get_rate(gpmc_fck); eth_cs = APOLLON_ETH_CS; /* Make sure CS1 timings are correct */ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG1, 0x00011200); if (rate >= 160000000) { gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f01); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080803); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1c0b1c0a); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); } else if (rate >= 130000000) { gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x041f1F1F); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000004C4); } else {/* rate = 100000000 */ gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG2, 0x001f1f00); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG3, 0x00080802); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG4, 0x1C091C09); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG5, 0x031A1F1F); gpmc_cs_write_reg(eth_cs, GPMC_CS_CONFIG6, 0x000003C2); } if (gpmc_cs_request(APOLLON_ETH_CS, SZ_16M, &base) < 0) { printk(KERN_ERR "Failed to request GPMC CS for smc91x\n"); goto out; } apollon_smc91x_resources[0].start = base + 0x300; apollon_smc91x_resources[0].end = base + 0x30f; udelay(100); omap_mux_init_gpio(APOLLON_ETHR_GPIO_IRQ, 0); err = gpio_request_one(APOLLON_ETHR_GPIO_IRQ, GPIOF_IN, "SMC91x irq"); if (err) { printk(KERN_ERR "Failed to request GPIO%d for smc91x IRQ\n", APOLLON_ETHR_GPIO_IRQ); gpmc_cs_free(APOLLON_ETH_CS); } out: clk_disable(gpmc_fck); clk_put(gpmc_fck); }
static int __devinit msm_rng_probe(struct platform_device *pdev) { struct resource *res; struct msm_rng_device *msm_rng_dev = NULL; void __iomem *base = NULL; int error = 0; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (res == NULL) { dev_err(&pdev->dev, "invalid address\n"); error = -EFAULT; goto err_exit; } msm_rng_dev = kzalloc(sizeof(msm_rng_dev), GFP_KERNEL); if (!msm_rng_dev) { dev_err(&pdev->dev, "cannot allocate memory\n"); error = -ENOMEM; goto err_exit; } base = ioremap(res->start, resource_size(res)); if (!base) { dev_err(&pdev->dev, "ioremap failed\n"); error = -ENOMEM; goto err_iomap; } msm_rng_dev->base = base; /* create a handle for clock control */ msm_rng_dev->prng_clk = clk_get(NULL, "prng_clk"); if (IS_ERR(msm_rng_dev->prng_clk)) { dev_err(&pdev->dev, "failed to register clock source\n"); error = -EPERM; goto err_clk_get; } /* save away pdev and register driver data */ msm_rng_dev->pdev = pdev; platform_set_drvdata(pdev, msm_rng_dev); /* register with hwrng framework */ msm_rng.priv = (unsigned long) msm_rng_dev; error = hwrng_register(&msm_rng); if (error) { dev_err(&pdev->dev, "failed to register hwrng\n"); error = -EPERM; goto err_hw_register; } return 0; err_hw_register: clk_put(msm_rng_dev->prng_clk); err_clk_get: iounmap(msm_rng_dev->base); err_iomap: kfree(msm_rng_dev); err_exit: return error; }
static int msm8930_audrx_init(struct snd_soc_pcm_runtime *rtd) { int err; struct snd_soc_codec *codec = rtd->codec; struct snd_soc_dapm_context *dapm = &codec->dapm; struct snd_soc_dai *cpu_dai = rtd->cpu_dai; pr_debug("%s()\n", __func__); snd_soc_dapm_new_controls(dapm, msm8930_dapm_widgets, ARRAY_SIZE(msm8930_dapm_widgets)); if (socinfo_get_platform_subtype() == PLATFORM_SUBTYPE_SGLTE) snd_soc_dapm_add_routes(dapm, common_audio_map_sglte, ARRAY_SIZE(common_audio_map_sglte)); else snd_soc_dapm_add_routes(dapm, common_audio_map, ARRAY_SIZE(common_audio_map)); snd_soc_dapm_enable_pin(dapm, "Ext Spk Left Pos"); snd_soc_dapm_enable_pin(dapm, "Ext Spk Left Neg"); snd_soc_dapm_sync(dapm); err = snd_soc_jack_new(codec, "Headset Jack", MSM8930_JACK_TYPES, &hs_jack); if (err) { pr_err("failed to create new jack\n"); return err; } err = snd_soc_jack_new(codec, "Button Jack", SITAR_JACK_BUTTON_MASK, &button_jack); if (err) { pr_err("failed to create new jack\n"); return err; } codec_clk = clk_get(cpu_dai->dev, "osr_clk"); /* * Switch is present only in 8930 CDP and SGLTE */ if (socinfo_get_platform_subtype() == PLATFORM_SUBTYPE_SGLTE || machine_is_msm8930_cdp()) mbhc_cfg.swap_gnd_mic = msm8930_swap_gnd_mic; if (socinfo_get_platform_subtype() == PLATFORM_SUBTYPE_SGLTE) { mbhc_cfg.gpio = GPIO_HS_DET_SGLTE; mbhc_cfg.gpio_level_insert = 0; } else mbhc_cfg.gpio = GPIO_HS_DET; /* * GPIO for headset detect is present in all devices * MTP/Fluid/CDP/SGLTE */ err = gpio_request(mbhc_cfg.gpio, "HEADSET_DETECT"); if (err) { pr_err("%s: Failed to request gpio %d\n", __func__, mbhc_cfg.gpio); return err; } mbhc_cfg.gpio_irq = gpio_to_irq(mbhc_cfg.gpio); sitar_hs_detect(codec, &mbhc_cfg); if (socinfo_get_pmic_model() != PMIC_MODEL_PM8917) { /* Initialize default PMIC speaker gain */ pm8xxx_spk_gain(DEFAULT_PMIC_SPK_GAIN); } return 0; }