static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node,
const struct cpumask *affinity, struct module *owner)
{
int cpu;
desc->irq_common_data.handler_data = NULL;
desc->irq_common_data.msi_desc = NULL;
desc->irq_data.common = &desc->irq_common_data;
desc->irq_data.irq = irq;
desc->irq_data.chip = &no_irq_chip;
desc->irq_data.chip_data = NULL;
irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS);
irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
irqd_set(&desc->irq_data, IRQD_IRQ_MASKED);
desc->handle_irq = handle_bad_irq;
desc->depth = 1;
desc->irq_count = 0;
desc->irqs_unhandled = 0;
desc->tot_count = 0;
desc->name = NULL;
desc->owner = owner;
for_each_possible_cpu(cpu)
*per_cpu_ptr(desc->kstat_irqs, cpu) = 0;
desc_smp_init(desc, node, affinity);
}
static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node,
struct module *owner)
{
int cpu;
desc->irq_data.irq = irq;
desc->irq_data.chip = &no_irq_chip;
desc->irq_data.chip_data = NULL;
desc->irq_data.handler_data = NULL;
desc->irq_data.msi_desc = NULL;
irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS);
irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
desc->handle_irq = handle_bad_irq;
desc->depth = 1;
desc->irq_count = 0;
desc->irqs_unhandled = 0;
desc->name = NULL;
desc->owner = owner;
for_each_possible_cpu(cpu)
*per_cpu_ptr(desc->kstat_irqs, cpu) = 0;
desc_smp_init(desc, node);
#ifdef CONFIG_SMP
INIT_LIST_HEAD(&desc->affinity_notify);
#endif
}
static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node)
{
desc->irq_data.irq = irq;
desc->irq_data.chip = &no_irq_chip;
desc->irq_data.chip_data = NULL;
desc->irq_data.handler_data = NULL;
desc->irq_data.msi_desc = NULL;
desc->status = IRQ_DEFAULT_INIT_FLAGS;
desc->handle_irq = handle_bad_irq;
desc->depth = 1;
desc->irq_count = 0;
desc->irqs_unhandled = 0;
desc->name = NULL;
memset(desc->kstat_irqs, 0, nr_cpu_ids * sizeof(*(desc->kstat_irqs)));
desc_smp_init(desc, node);
}
static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node)
{
int cpu;
desc->irq_data.irq = irq;
desc->irq_data.chip = &no_irq_chip;
desc->irq_data.chip_data = NULL;
desc->irq_data.handler_data = NULL;
desc->irq_data.msi_desc = NULL;
desc->status = IRQ_DEFAULT_INIT_FLAGS;
desc->handle_irq = handle_bad_irq;
desc->depth = 1;
desc->irq_count = 0;
desc->irqs_unhandled = 0;
desc->name = NULL;
for_each_possible_cpu(cpu)
*per_cpu_ptr(desc->kstat_irqs, cpu) = 0;
desc_smp_init(desc, node);
}
int __init early_irq_init(void)
{
int count, i, node = first_online_node;
struct irq_desc *desc;
init_irq_default_affinity();
printk(KERN_INFO "NR_IRQS:%d\n", NR_IRQS);
desc = irq_desc;
count = ARRAY_SIZE(irq_desc);
for (i = 0; i < count; i++) {
desc[i].irq_data.irq = i;
desc[i].irq_data.chip = &no_irq_chip;
desc[i].kstat_irqs = kstat_irqs_all[i];
alloc_masks(desc + i, GFP_KERNEL, node);
desc_smp_init(desc + i, node);
lockdep_set_class(&desc[i].lock, &irq_desc_lock_class);
}
return arch_early_irq_init();
}
// ARM10C 20141004
// irq: 0, desc: kmem_cache#28-o0, node: 0, owner: null
static void desc_set_defaults(unsigned int irq, struct irq_desc *desc, int node,
struct module *owner)
{
int cpu;
// desc->irq_data.irq: (kmem_cache#28-o0)->irq_data.irq, irq: 0
desc->irq_data.irq = irq;
// desc->irq_data.irq: (kmem_cache#28-o0)->irq_data.irq: 0
// desc->irq_data.chip: (kmem_cache#28-o0)->irq_data.chip
desc->irq_data.chip = &no_irq_chip;
// desc->irq_data.chip: (kmem_cache#28-o0)->irq_data.chip: &no_irq_chip
// desc->irq_data.chip_data: (kmem_cache#28-o0)->irq_data.chip_data
desc->irq_data.chip_data = NULL;
// desc->irq_data.chip_data: (kmem_cache#28-o0)->irq_data.chip_data: NULL
// desc->irq_data.handler_data: (kmem_cache#28-o0)->irq_data.handler_data
desc->irq_data.handler_data = NULL;
// desc->irq_data.handler_data: (kmem_cache#28-o0)->irq_data.handler_data: NULL
// desc->irq_data.msi_desc: (kmem_cache#28-o0)->irq_data.msi_desc
desc->irq_data.msi_desc = NULL;
// desc->irq_data.msi_desc: (kmem_cache#28-o0)->irq_data.msi_desc: NULL
// desc: kmem_cache#28-o0, 0xFFFFFFFF, _IRQ_DEFAULT_INIT_FLAGS: 0xc00
irq_settings_clr_and_set(desc, ~0, _IRQ_DEFAULT_INIT_FLAGS);
// irq_settings_clr_and_set에서 한일:
// desc->status_use_accessors: (kmem_cache#28-o0)->status_use_accessors: 0xc00
// &desc->irq_data: &(kmem_cache#28-o0)->irq_data, IRQD_IRQ_DISABLED: 0x10000
irqd_set(&desc->irq_data, IRQD_IRQ_DISABLED);
// irqd_set에서 한일:
// d->state_use_accessors: (&(kmem_cache#28-o0)->irq_data)->state_use_accessors: 0x10000
// desc->handle_irq: (kmem_cache#28-o0)->handle_irq
desc->handle_irq = handle_bad_irq;
// desc->handle_irq: (kmem_cache#28-o0)->handle_irq: handle_bad_irq
// desc->depth: (kmem_cache#28-o0)->depth
desc->depth = 1;
// desc->depth: (kmem_cache#28-o0)->depth: 1
// desc->irq_count: (kmem_cache#28-o0)->irq_count
desc->irq_count = 0;
// desc->irq_count: (kmem_cache#28-o0)->irq_count: 0
// desc->irqs_unhandled: (kmem_cache#28-o0)->irqs_unhandled
desc->irqs_unhandled = 0;
// desc->irqs_unhandled: (kmem_cache#28-o0)->irqs_unhandled: 0
// desc->name: (kmem_cache#28-o0)->name
desc->name = NULL;
// desc->name: (kmem_cache#28-o0)->name: NULL
// desc->owner: (kmem_cache#28-o0)->owner, owner: null
desc->owner = owner;
// desc->owner: (kmem_cache#28-o0)->owner: null
for_each_possible_cpu(cpu)
// for ((cpu) = -1; (cpu) = cpumask_next((cpu), (cpu_possible_mask)), (cpu) < nr_cpu_ids; )
// desc->kstat_irqs: (kmem_cache#28-o0)->kstat_irqs, cpu: 0
*per_cpu_ptr(desc->kstat_irqs, cpu) = 0;
// [pcp0] (kmem_cache#28-o0)->kstat_irqs: 0
// cpu: 1 .. 3 수행
// desc: kmem_cache#28-o0, node: 0
desc_smp_init(desc, node);
// desc_smp_init에서 한일:
// desc->irq_data.node: (kmem_cache#28-o0)->irq_data.node: 0
// desc->irq_data.affinity: (kmem_cache#28-o0)->irq_data.affinity.bits[0]: 0xF
}