Ejemplo n.º 1
0
static void __init mx27ads_board_init(void)
{
	mxc_gpio_setup_multiple_pins(mx27ads_pins, ARRAY_SIZE(mx27ads_pins),
			"mx27ads");

	imx27_add_imx_uart0(&uart_pdata);
	imx27_add_imx_uart1(&uart_pdata);
	imx27_add_imx_uart2(&uart_pdata);
	imx27_add_imx_uart3(&uart_pdata);
	imx27_add_imx_uart4(&uart_pdata);
	imx27_add_imx_uart5(&uart_pdata);
	imx27_add_mxc_nand(&mx27ads_nand_board_info);

	/* only the i2c master 1 is used on this CPU card */
	i2c_register_board_info(1, mx27ads_i2c_devices,
				ARRAY_SIZE(mx27ads_i2c_devices));
	imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
	imx27_add_imx_fb(&mx27ads_fb_data);
	imx27_add_mxc_mmc(0, &sdhc1_pdata);
	imx27_add_mxc_mmc(1, &sdhc2_pdata);

	imx27_add_fec(NULL);
	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
	imx27_add_mxc_w1(NULL);
}
Ejemplo n.º 2
0
static void __init visstrim_m10_board_init(void)
{
	int ret;

	imx27_soc_init();

	ret = mxc_gpio_setup_multiple_pins(visstrim_m10_pins,
			ARRAY_SIZE(visstrim_m10_pins), "VISSTRIM_M10");
	if (ret)
		pr_err("Failed to setup pins (%d)\n", ret);

	imx27_add_imx_ssi(0, &visstrim_m10_ssi_pdata);
	imx27_add_imx_uart0(&uart_pdata);

	i2c_register_board_info(0, visstrim_m10_i2c_devices,
				ARRAY_SIZE(visstrim_m10_i2c_devices));
	imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
	imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
	imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
	imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
	imx27_add_fec(NULL);
	imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
	imx_add_platform_device("mx27vis", 0, NULL, 0, NULL, 0);
}
Ejemplo n.º 3
0
static void __init mx27pdk_init(void)
{
	imx27_soc_init();

	mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
		"mx27pdk");
	mx27_3ds_sdhc1_enable_level_translator();
	imx27_add_imx_uart0(&uart_pdata);
	imx27_add_fec(NULL);
	imx27_add_imx_keypad(&mx27_3ds_keymap_data);
	imx27_add_mxc_mmc(0, &sdhc1_pdata);
	imx27_add_imx2_wdt(NULL);
	otg_phy_init();

	if (otg_mode_host) {
		otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
				ULPI_OTG_DRVVBUS_EXT);

		if (otg_pdata.otg)
			imx27_add_mxc_ehci_otg(&otg_pdata);
	}

	if (!otg_mode_host)
		imx27_add_fsl_usb2_udc(&otg_device_pdata);

	imx27_add_spi_imx1(&spi2_pdata);
	imx27_add_spi_imx0(&spi1_pdata);
	spi_register_board_info(mx27_3ds_spi_devs,
						ARRAY_SIZE(mx27_3ds_spi_devs));

	if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
		pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
	imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
	imx27_add_imx_fb(&mx27_3ds_fb_data);
}
Ejemplo n.º 4
0
static void __init pca100_init(void)
{
	int ret;

	imx27_soc_init();

	ret = mxc_gpio_setup_multiple_pins(pca100_pins,
			ARRAY_SIZE(pca100_pins), "PCA100");
	if (ret)
		printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);

	imx27_add_imx_ssi(0, &pca100_ssi_pdata);

	imx27_add_imx_uart0(&uart_pdata);

	imx27_add_mxc_mmc(1, &sdhc_pdata);

	imx27_add_mxc_nand(&pca100_nand_board_info);

	/* only the i2c master 1 is used on this CPU card */
	i2c_register_board_info(1, pca100_i2c_devices,
				ARRAY_SIZE(pca100_i2c_devices));

	imx27_add_imx_i2c(1, &pca100_i2c1_data);

	mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
	mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
	spi_register_board_info(pca100_spi_board_info,
				ARRAY_SIZE(pca100_spi_board_info));
	imx27_add_spi_imx0(&pca100_spi0_data);

	gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
	gpio_direction_output(OTG_PHY_CS_GPIO, 1);
	gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
	gpio_direction_output(USBH2_PHY_CS_GPIO, 1);

	if (otg_mode_host) {
		otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
				ULPI_OTG_DRVVBUS_EXT);

		if (otg_pdata.otg)
			imx27_add_mxc_ehci_otg(&otg_pdata);
	} else {
		gpio_set_value(OTG_PHY_CS_GPIO, 0);
		imx27_add_fsl_usb2_udc(&otg_device_pdata);
	}

	usbh2_pdata.otg = imx_otg_ulpi_create(
			ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);

	if (usbh2_pdata.otg)
		imx27_add_mxc_ehci_hs(2, &usbh2_pdata);

	imx27_add_imx_fb(&pca100_fb_data);

	imx27_add_fec(NULL);
	imx27_add_imx2_wdt();
	imx27_add_mxc_w1();
}
Ejemplo n.º 5
0
static void __init mx27lite_init(void)
{
	imx27_soc_init();

	mxc_gpio_setup_multiple_pins(mx27lite_pins, ARRAY_SIZE(mx27lite_pins),
		"imx27lite");
	imx27_add_imx_uart0(&uart_pdata);
	imx27_add_fec(NULL);
}
Ejemplo n.º 6
0
static void __init mx27ipcam_init(void)
{
	imx27_soc_init();

	mxc_gpio_setup_multiple_pins(mx27ipcam_pins, ARRAY_SIZE(mx27ipcam_pins),
		"mx27ipcam");

	imx27_add_imx_uart0(NULL);
	imx27_add_fec(NULL);
	imx27_add_imx2_wdt();
}
Ejemplo n.º 7
0
static void __init eukrea_cpuimx27_init(void)
{
	imx27_soc_init();

	mxc_gpio_setup_multiple_pins(eukrea_cpuimx27_pins,
		ARRAY_SIZE(eukrea_cpuimx27_pins), "CPUIMX27");

	imx27_add_imx_uart0(&uart_pdata);

	imx27_add_mxc_nand(&cpuimx27_nand_board_info);

	i2c_register_board_info(0, eukrea_cpuimx27_i2c_devices,
				ARRAY_SIZE(eukrea_cpuimx27_i2c_devices));

	imx27_add_imx_i2c(0, &cpuimx27_i2c1_data);

	imx27_add_fec(NULL);
	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
	imx27_add_imx2_wdt(NULL);
	imx27_add_mxc_w1(NULL);

#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
	/* SDHC2 can be used for Wifi */
	imx27_add_mxc_mmc(1, NULL);
#endif
#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
	/* in which case UART4 is also used for Bluetooth */
	imx27_add_imx_uart3(&uart_pdata);
#endif

#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
	platform_device_register(&serial_device);
#endif

	if (otg_mode_host) {
		otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
				ULPI_OTG_DRVVBUS_EXT);
		if (otg_pdata.otg)
			imx27_add_mxc_ehci_otg(&otg_pdata);
	} else {
		imx27_add_fsl_usb2_udc(&otg_device_pdata);
	}

	usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
			ULPI_OTG_DRVVBUS_EXT);
	if (usbh2_pdata.otg)
		imx27_add_mxc_ehci_hs(2, &usbh2_pdata);

#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
	eukrea_mbimx27_baseboard_init();
#endif
}
Ejemplo n.º 8
0
static void __init mx27pdk_init(void)
{
	int ret;
	imx27_soc_init();

	mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
		"mx27pdk");
	mx27_3ds_sdhc1_enable_level_translator();
	imx27_add_imx_uart0(&uart_pdata);
	imx27_add_fec(NULL);
	imx27_add_imx_keypad(&mx27_3ds_keymap_data);
	imx27_add_mxc_mmc(0, &sdhc1_pdata);
	imx27_add_imx2_wdt();
	otg_phy_init();

	if (otg_mode_host) {
		otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
				ULPI_OTG_DRVVBUS_EXT);

		if (otg_pdata.otg)
			imx27_add_mxc_ehci_otg(&otg_pdata);
	}

	if (!otg_mode_host)
		imx27_add_fsl_usb2_udc(&otg_device_pdata);

	imx27_add_spi_imx1(&spi2_pdata);
	imx27_add_spi_imx0(&spi1_pdata);
	mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT);
	spi_register_board_info(mx27_3ds_spi_devs,
						ARRAY_SIZE(mx27_3ds_spi_devs));

	if (mxc_expio_init(MX27_CS5_BASE_ADDR, IMX_GPIO_NR(3, 28)))
		pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
	imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
	platform_add_devices(devices, ARRAY_SIZE(devices));
	imx27_add_imx_fb(&mx27_3ds_fb_data);

	ret = gpio_request_array(mx27_3ds_camera_gpios,
				 ARRAY_SIZE(mx27_3ds_camera_gpios));
	if (ret) {
		pr_err("Failed to request camera gpios");
		iclink_ov2640.power = NULL;
	}

	imx27_add_mx2_camera(&mx27_3ds_cam_pdata);
	imx27_add_imx_ssi(0, &mx27_3ds_ssi_pdata);

	imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
}
Ejemplo n.º 9
0
static void __init pcm038_init(void)
{
	imx27_soc_init();

	mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
			"PCM038");

	pcm038_init_sram();

	imx27_add_imx_uart0(&uart_pdata);
	imx27_add_imx_uart1(&uart_pdata);
	imx27_add_imx_uart2(&uart_pdata);

	mxc_gpio_mode(PE16_AF_OWIRE);
	imx27_add_mxc_nand(&pcm038_nand_board_info);

	/* only the i2c master 1 is used on this CPU card */
	i2c_register_board_info(1, pcm038_i2c_devices,
				ARRAY_SIZE(pcm038_i2c_devices));

	imx27_add_imx_i2c(1, &pcm038_i2c1_data);

	/* PE18 for user-LED D40 */
	mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);

	mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);

	/* MC13783 IRQ */
	mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);

	imx27_add_spi_imx0(&pcm038_spi0_data);
	pcm038_spi_board_info[0].irq = gpio_to_irq(IMX_GPIO_NR(2, 23));
	spi_register_board_info(pcm038_spi_board_info,
				ARRAY_SIZE(pcm038_spi_board_info));

	imx27_add_mxc_ehci_hs(2, &usbh2_pdata);

	imx27_add_fec(NULL);
	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
	imx27_add_imx2_wdt();
	imx27_add_mxc_w1();

#ifdef CONFIG_MACH_PCM970_BASEBOARD
	pcm970_baseboard_init();
#endif
}
static void __init pcm038_init(void)
{
	imx27_soc_init();

	mxc_gpio_setup_multiple_pins(pcm038_pins, ARRAY_SIZE(pcm038_pins),
			"PCM038");

	pcm038_init_sram();

	imx27_add_imx_uart0(&uart_pdata);
	imx27_add_imx_uart1(&uart_pdata);
	imx27_add_imx_uart2(&uart_pdata);

	mxc_gpio_mode(PE16_AF_OWIRE);
	imx27_add_mxc_nand(&pcm038_nand_board_info);

	/*                                                */
	i2c_register_board_info(1, pcm038_i2c_devices,
				ARRAY_SIZE(pcm038_i2c_devices));

	imx27_add_imx_i2c(1, &pcm038_i2c1_data);

	/*                       */
	mxc_gpio_mode(GPIO_PORTE | 18 | GPIO_GPIO | GPIO_OUT);

	mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT);

	/*             */
	mxc_gpio_mode(GPIO_PORTB | 23 | GPIO_GPIO | GPIO_IN);

	imx27_add_spi_imx0(&pcm038_spi0_data);
	spi_register_board_info(pcm038_spi_board_info,
				ARRAY_SIZE(pcm038_spi_board_info));

	imx27_add_mxc_ehci_hs(2, &usbh2_pdata);

	imx27_add_fec(NULL);
	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
	imx27_add_imx2_wdt(NULL);
	imx27_add_mxc_w1(NULL);

#ifdef CONFIG_MACH_PCM970_BASEBOARD
	pcm970_baseboard_init();
#endif
}
Ejemplo n.º 11
0
static int eukrea_cpuimx27_late_init(void)
{
#ifdef CONFIG_I2C_LP3972
    struct i2c_client *client;
    u8 reg[1];
#endif
    console_flush();
    imx27_add_fec(&fec_info);

#ifdef CONFIG_I2C_LP3972
    client = lp3972_get_client();
    if (!client)
        return -ENODEV;
    reg[0] = 0xa0;
    i2c_write_reg(client, 0x39, reg, sizeof(reg));
#endif
    return 0;
}
Ejemplo n.º 12
0
static int mx27ads_devices_init(void)
{
	int i;
	unsigned int mode[] = {
		PD0_AIN_FEC_TXD0,
		PD1_AIN_FEC_TXD1,
		PD2_AIN_FEC_TXD2,
		PD3_AIN_FEC_TXD3,
		PD4_AOUT_FEC_RX_ER,
		PD5_AOUT_FEC_RXD1,
		PD6_AOUT_FEC_RXD2,
		PD7_AOUT_FEC_RXD3,
		PD8_AF_FEC_MDIO,
		PD9_AIN_FEC_MDC | GPIO_PUEN,
		PD10_AOUT_FEC_CRS,
		PD11_AOUT_FEC_TX_CLK,
		PD12_AOUT_FEC_RXD0,
		PD13_AOUT_FEC_RX_DV,
		PD14_AOUT_FEC_RX_CLK,
		PD15_AOUT_FEC_COL,
		PD16_AIN_FEC_TX_ER,
		PF23_AIN_FEC_TX_EN,
		PE12_PF_UART1_TXD,
		PE13_PF_UART1_RXD,
		PE14_PF_UART1_CTS,
		PE15_PF_UART1_RTS,
	};

	/* initizalize gpios */
	for (i = 0; i < ARRAY_SIZE(mode); i++)
		imx_gpio_mode(mode[i]);

	add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);

	imx27_add_fec(&fec_info);
	devfs_add_partition("nor0", 0x00000, 0x20000, DEVFS_PARTITION_FIXED, "self0");
	devfs_add_partition("nor0", 0x20000, 0x20000, DEVFS_PARTITION_FIXED, "env0");
	protect_file("/dev/env0", 1);

	armlinux_set_bootparams((void *)0xa0000100);
	armlinux_set_architecture(MACH_TYPE_MX27ADS);

	return 0;
}
Ejemplo n.º 13
0
static void __init mxt_td60_board_init(void)
{
	imx27_soc_init();

	mxc_gpio_setup_multiple_pins(mxt_td60_pins, ARRAY_SIZE(mxt_td60_pins),
			"MXT_TD60");

	imx27_add_imx_uart0(&uart_pdata);
	imx27_add_imx_uart1(&uart_pdata);
	imx27_add_imx_uart2(&uart_pdata);
	imx27_add_mxc_nand(&mxt_td60_nand_board_info);

	i2c_register_board_info(0, mxt_td60_i2c_devices,
				ARRAY_SIZE(mxt_td60_i2c_devices));

	i2c_register_board_info(1, mxt_td60_i2c2_devices,
				ARRAY_SIZE(mxt_td60_i2c2_devices));

	imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
	imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
	imx27_add_imx_fb(&mxt_td60_fb_data);
	imx27_add_mxc_mmc(0, &sdhc1_pdata);
	imx27_add_fec(NULL);
}
Ejemplo n.º 14
0
static void __init pca100_init(void)
{
	int ret;

	imx27_soc_init();

	/* SSI unit */
	mxc_audmux_v1_configure_port(MX27_AUDMUX_HPCR1_SSI0,
				  MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
				  MXC_AUDMUX_V1_PCR_TFCSEL(3) |
				  MXC_AUDMUX_V1_PCR_TCLKDIR | /* clock is output */
				  MXC_AUDMUX_V1_PCR_RXDSEL(3));
	mxc_audmux_v1_configure_port(3,
				  MXC_AUDMUX_V1_PCR_SYN | /* 4wire mode */
				  MXC_AUDMUX_V1_PCR_TFCSEL(0) |
				  MXC_AUDMUX_V1_PCR_TFSDIR |
				  MXC_AUDMUX_V1_PCR_RXDSEL(0));

	ret = mxc_gpio_setup_multiple_pins(pca100_pins,
			ARRAY_SIZE(pca100_pins), "PCA100");
	if (ret)
		printk(KERN_ERR "pca100: Failed to setup pins (%d)\n", ret);

	imx27_add_imx_ssi(0, &pca100_ssi_pdata);

	imx27_add_imx_uart0(&uart_pdata);

	imx27_add_mxc_mmc(1, &sdhc_pdata);

	imx27_add_mxc_nand(&pca100_nand_board_info);

	/* only the i2c master 1 is used on this CPU card */
	i2c_register_board_info(1, pca100_i2c_devices,
				ARRAY_SIZE(pca100_i2c_devices));

	imx27_add_imx_i2c(1, &pca100_i2c1_data);

	mxc_gpio_mode(GPIO_PORTD | 28 | GPIO_GPIO | GPIO_IN);
	mxc_gpio_mode(GPIO_PORTD | 27 | GPIO_GPIO | GPIO_IN);
	spi_register_board_info(pca100_spi_board_info,
				ARRAY_SIZE(pca100_spi_board_info));
	imx27_add_spi_imx0(&pca100_spi0_data);

	gpio_request(OTG_PHY_CS_GPIO, "usb-otg-cs");
	gpio_direction_output(OTG_PHY_CS_GPIO, 1);
	gpio_request(USBH2_PHY_CS_GPIO, "usb-host2-cs");
	gpio_direction_output(USBH2_PHY_CS_GPIO, 1);

	if (otg_mode_host) {
		otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
				ULPI_OTG_DRVVBUS_EXT);

		if (otg_pdata.otg)
			imx27_add_mxc_ehci_otg(&otg_pdata);
	} else {
		gpio_set_value(OTG_PHY_CS_GPIO, 0);
		imx27_add_fsl_usb2_udc(&otg_device_pdata);
	}

	usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
				ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);

	if (usbh2_pdata.otg)
		imx27_add_mxc_ehci_hs(2, &usbh2_pdata);

	imx27_add_imx_fb(&pca100_fb_data);

	imx27_add_fec(NULL);
	imx27_add_imx2_wdt(NULL);
	imx27_add_mxc_w1(NULL);
}
Ejemplo n.º 15
0
static int pcm038_devices_init(void)
{
	int i;
	char *envdev;

	unsigned int mode[] = {
		PD0_AIN_FEC_TXD0,
		PD1_AIN_FEC_TXD1,
		PD2_AIN_FEC_TXD2,
		PD3_AIN_FEC_TXD3,
		PD4_AOUT_FEC_RX_ER,
		PD5_AOUT_FEC_RXD1,
		PD6_AOUT_FEC_RXD2,
		PD7_AOUT_FEC_RXD3,
		PD8_AF_FEC_MDIO,
		PD9_AIN_FEC_MDC | GPIO_PUEN,
		PD10_AOUT_FEC_CRS,
		PD11_AOUT_FEC_TX_CLK,
		PD12_AOUT_FEC_RXD0,
		PD13_AOUT_FEC_RX_DV,
		PD14_AOUT_FEC_RX_CLK,
		PD15_AOUT_FEC_COL,
		PD16_AIN_FEC_TX_ER,
		PF23_AIN_FEC_TX_EN,
		PE12_PF_UART1_TXD,
		PE13_PF_UART1_RXD,
		PE14_PF_UART1_CTS,
		PE15_PF_UART1_RTS,
		PD25_PF_CSPI1_RDY,
		GPIO_PORTD | 28 | GPIO_GPIO | GPIO_OUT,
		PD29_PF_CSPI1_SCLK,
		PD30_PF_CSPI1_MISO,
		PD31_PF_CSPI1_MOSI,
		/* display */
		PA5_PF_LSCLK,
		PA6_PF_LD0,
		PA7_PF_LD1,
		PA8_PF_LD2,
		PA9_PF_LD3,
		PA10_PF_LD4,
		PA11_PF_LD5,
		PA12_PF_LD6,
		PA13_PF_LD7,
		PA14_PF_LD8,
		PA15_PF_LD9,
		PA16_PF_LD10,
		PA17_PF_LD11,
		PA18_PF_LD12,
		PA19_PF_LD13,
		PA20_PF_LD14,
		PA21_PF_LD15,
		PA22_PF_LD16,
		PA23_PF_LD17,
		PA24_PF_REV,
		PA25_PF_CLS,
		PA26_PF_PS,
		PA27_PF_SPL_SPR,
		PA28_PF_HSYNC,
		PA29_PF_VSYNC,
		PA30_PF_CONTRAST,
		PA31_PF_OE_ACD,
		/* USB host 2 */
		PA0_PF_USBH2_CLK,
		PA1_PF_USBH2_DIR,
		PA2_PF_USBH2_DATA7,
		PA3_PF_USBH2_NXT,
		PA4_PF_USBH2_STP,
		PD19_AF_USBH2_DATA4,
		PD20_AF_USBH2_DATA3,
		PD21_AF_USBH2_DATA6,
		PD22_AF_USBH2_DATA0,
		PD23_AF_USBH2_DATA2,
		PD24_AF_USBH2_DATA1,
		PD26_AF_USBH2_DATA5,
		/* I2C1 */
		PD17_PF_I2C_DATA | GPIO_PUEN,
		PD18_PF_I2C_CLK,
		/* I2C2 */
		PC5_PF_I2C2_SDA,
		PC6_PF_I2C2_SCL,
	};

	/* configure 16 bit nor flash on cs0 */
	CS0U = 0x22C2CF00;
	CS0L = 0x75000D01;
	CS0A = 0x00000900;

	/* configure SRAM on cs1 */
	CS1U = 0x0000d843;
	CS1L = 0x22252521;
	CS1A = 0x22220a00;

	/* configure SJA1000 on cs4 */
	CS4U = 0x0000DCF6;
	CS4L = 0x444A0301;
	CS4A = 0x44443302;

	/* initizalize gpios */
	for (i = 0; i < ARRAY_SIZE(mode); i++)
		imx_gpio_mode(mode[i]);

	PCCR0 |= PCCR0_CSPI1_EN;
	PCCR1 |= PCCR1_PERCLK2_EN;

	gpio_direction_output(GPIO_PORTD | 28, 0);
	gpio_set_value(GPIO_PORTD | 28, 0);

	spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
	imx27_add_spi0(&pcm038_spi_0_data);

	add_cfi_flash_device(-1, 0xC0000000, 32 * 1024 * 1024, 0);
	imx27_add_nand(&nand_info);
	imx27_add_fb(&pcm038_fb_data);

	PCCR0 |= PCCR0_I2C1_EN | PCCR0_I2C2_EN;
	imx27_add_i2c0(NULL);
	imx27_add_i2c1(NULL);

#ifdef CONFIG_USB
	pcm038_usbh_init();
	add_generic_usb_ehci_device(-1, IMX_OTG_BASE + 0x400, NULL);
#endif

	/* Register the fec device after the PLL re-initialisation
	 * as the fec depends on the (now higher) ipg clock
	 */
	imx27_add_fec(&fec_info);

	switch ((GPCR & GPCR_BOOT_MASK) >> GPCR_BOOT_SHIFT) {
	case GPCR_BOOT_8BIT_NAND_2k:
	case GPCR_BOOT_16BIT_NAND_2k:
	case GPCR_BOOT_16BIT_NAND_512:
	case GPCR_BOOT_8BIT_NAND_512:
		devfs_add_partition("nand0", 0x00000, 0x40000, PARTITION_FIXED, "self_raw");
		dev_add_bb_dev("self_raw", "self0");

		devfs_add_partition("nand0", 0x40000, 0x20000, PARTITION_FIXED, "env_raw");
		dev_add_bb_dev("env_raw", "env0");
		envdev = "NAND";
		break;
	default:
		devfs_add_partition("nor0", 0x00000, 0x40000, PARTITION_FIXED, "self0");
		devfs_add_partition("nor0", 0x40000, 0x20000, PARTITION_FIXED, "env0");
		protect_file("/dev/env0", 1);

		envdev = "NOR";
	}

	printf("Using environment in %s Flash\n", envdev);

	armlinux_set_bootparams((void *)0xa0000100);
	armlinux_set_architecture(MACH_TYPE_PCM038);

	return 0;
}
Ejemplo n.º 16
0
static int neso_devices_init(void)
{
	int i;

	unsigned int mode[] = {
		/* UART1 */
		PE12_PF_UART1_TXD,
		PE13_PF_UART1_RXD,
		PE14_PF_UART1_CTS,
		PE15_PF_UART1_RTS,
		/* FEC */
		PD0_AIN_FEC_TXD0,
		PD1_AIN_FEC_TXD1,
		PD2_AIN_FEC_TXD2,
		PD3_AIN_FEC_TXD3,
		PD4_AOUT_FEC_RX_ER,
		PD5_AOUT_FEC_RXD1,
		PD6_AOUT_FEC_RXD2,
		PD7_AOUT_FEC_RXD3,
		PD8_AF_FEC_MDIO,
		PD9_AIN_FEC_MDC,
		PD10_AOUT_FEC_CRS,
		PD11_AOUT_FEC_TX_CLK,
		PD12_AOUT_FEC_RXD0,
		PD13_AOUT_FEC_RX_DV,
		PD14_AOUT_FEC_RX_CLK,
		PD15_AOUT_FEC_COL,
		PD16_AIN_FEC_TX_ER,
		PF23_AIN_FEC_TX_EN,

		/* SSI1 connected in AC97 style */
		PC20_PF_SSI1_FS,
		PC21_PF_SSI1_RXD,
		PC22_PF_SSI1_TXD,
		PC23_PF_SSI1_CLK,

		/* LED 1 */
		(GPIO_PORTB | 15 | GPIO_GPIO | GPIO_OUT),
		/* LED 2 */
		(GPIO_PORTB | 16 | GPIO_GPIO | GPIO_OUT),
		/* CTOUCH reset */
		(GPIO_PORTB | 17 | GPIO_GPIO | GPIO_OUT),
		/* CTOUCH IRQ */
		(GPIO_PORTB | 14 | GPIO_GPIO | GPIO_IN),
		/* RTC IRQ */
		(GPIO_PORTF | 14 | GPIO_GPIO | GPIO_IN),
		/* SD change card detection */
		(GPIO_PORTF | 17 | GPIO_GPIO | GPIO_IN),
		/* SDHC1*/
		PE18_PF_SD1_D0,
		PE19_PF_SD1_D1,
		PE20_PF_SD1_D2,
		PE21_PF_SD1_D3,
		PE22_PF_SD1_CMD,
		PE23_PF_SD1_CLK,
		/* I2C1 */
		PD17_PF_I2C_DATA,
		PD18_PF_I2C_CLK,
		/* I2C2, for CTOUCH */
		PC5_PF_I2C2_SDA,
		PC6_PF_I2C2_SCL,

		/* Connected to: Both USB phys and ethernet phy FIXME 1 = RESET? */
		PE17_PF_RESET_OUT,

		/* USB host */
		(USBH2_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT),
		PA0_PF_USBH2_CLK,
		PA1_PF_USBH2_DIR,
		PA3_PF_USBH2_NXT,
		PA4_PF_USBH2_STP,
		PD22_AF_USBH2_DATA0,
		PD24_AF_USBH2_DATA1,
		PD23_AF_USBH2_DATA2,
		PD20_AF_USBH2_DATA3,
		PD19_AF_USBH2_DATA4,
		PD26_AF_USBH2_DATA5,
		PD21_AF_USBH2_DATA6,
		PA2_PF_USBH2_DATA7,

		/* USB OTG */
		(OTG_PHY_CS_GPIO | GPIO_GPIO | GPIO_OUT),
		PE24_PF_USBOTG_CLK,
		PE2_PF_USBOTG_DIR,
		PE0_PF_USBOTG_NXT,
		PE1_PF_USBOTG_STP,
		PC9_PF_USBOTG_DATA0,
		PC11_PF_USBOTG_DATA1,
		PC10_PF_USBOTG_DATA2,
		PC13_PF_USBOTG_DATA3,
		PC12_PF_USBOTG_DATA4,
		PC7_PF_USBOTG_DATA5,
		PC8_PF_USBOTG_DATA6,
		PE25_PF_USBOTG_DATA7,

		/* Display signals */
		(LCD_POWER_GPIO | GPIO_GPIO | GPIO_OUT), /* LCD power: 1 = LCD on */
		PA5_PF_LSCLK,
		PA6_PF_LD0,
		PA7_PF_LD1,
		PA8_PF_LD2,
		PA9_PF_LD3,
		PA10_PF_LD4,
		PA11_PF_LD5,
		PA12_PF_LD6,
		PA13_PF_LD7,
		PA14_PF_LD8,
		PA15_PF_LD9,
		PA16_PF_LD10,
		PA17_PF_LD11,
		PA18_PF_LD12,
		PA19_PF_LD13,
		PA20_PF_LD14,
		PA21_PF_LD15,
		PA22_PF_LD16,
		PA23_PF_LD17,
		PA31_PF_OE_ACD,	/* DE */

		/* Backlight PWM (Use as gpio) */
		(BACKLIGHT_POWER_GPIO | GPIO_GPIO | GPIO_OUT),
	};

	/* reset the chip select lines to the USB/OTG phys to avoid any hang */
	gpio_direction_output(OTG_PHY_CS_GPIO, 1);
	gpio_direction_output(USBH2_PHY_CS_GPIO, 1);

	/* initialize gpios */
	for (i = 0; i < ARRAY_SIZE(mode); i++)
		imx_gpio_mode(mode[i]);

	imx27_add_nand(&nand_info);
	imx27_add_fb(&neso_fb_data);

#ifdef CONFIG_USB
	neso_usbh_init();
	add_generic_usb_ehci_device(DEVICE_ID_DYNAMIC, MX27_USB_OTG_BASE_ADDR + 0x400, NULL);
#endif

	imx27_add_fec(&fec_info);

	devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
	dev_add_bb_dev("self_raw", "self0");

	devfs_add_partition("nand0", 0x40000, 0x80000, DEVFS_PARTITION_FIXED, "env_raw");
	dev_add_bb_dev("env_raw", "env0");

	armlinux_set_bootparams((void *)0xa0000100);
	armlinux_set_architecture(MACH_TYPE_NESO);

	return 0;
}
Ejemplo n.º 17
0
static int pca100_devices_init(void)
{
	int i;
	struct device_d *nand;

	unsigned int mode[] = {
		PD0_AIN_FEC_TXD0,
		PD1_AIN_FEC_TXD1,
		PD2_AIN_FEC_TXD2,
		PD3_AIN_FEC_TXD3,
		PD4_AOUT_FEC_RX_ER,
		PD5_AOUT_FEC_RXD1,
		PD6_AOUT_FEC_RXD2,
		PD7_AOUT_FEC_RXD3,
		PD8_AF_FEC_MDIO,
		PD9_AIN_FEC_MDC | GPIO_PUEN,
		PD10_AOUT_FEC_CRS,
		PD11_AOUT_FEC_TX_CLK,
		PD12_AOUT_FEC_RXD0,
		PD13_AOUT_FEC_RX_DV,
		PD14_AOUT_FEC_RX_CLK,
		PD15_AOUT_FEC_COL,
		PD16_AIN_FEC_TX_ER,
		PF23_AIN_FEC_TX_EN,
		PE12_PF_UART1_TXD,
		PE13_PF_UART1_RXD,
		PE14_PF_UART1_CTS,
		PE15_PF_UART1_RTS,
		PD25_PF_CSPI1_RDY,
		PD26_PF_CSPI1_SS2,
		PD27_PF_CSPI1_SS1,
		PD28_PF_CSPI1_SS0,
		PD29_PF_CSPI1_SCLK,
		PD30_PF_CSPI1_MISO,
		PD31_PF_CSPI1_MOSI,
		/* USB host 2 */
		PA0_PF_USBH2_CLK,
		PA1_PF_USBH2_DIR,
		PA2_PF_USBH2_DATA7,
		PA3_PF_USBH2_NXT,
		PA4_PF_USBH2_STP,
		PD19_AF_USBH2_DATA4,
		PD20_AF_USBH2_DATA3,
		PD21_AF_USBH2_DATA6,
		PD22_AF_USBH2_DATA0,
		PD23_AF_USBH2_DATA2,
		PD24_AF_USBH2_DATA1,
		PD26_AF_USBH2_DATA5,
		/* SDHC */
		PB4_PF_SD2_D0,
		PB5_PF_SD2_D1,
		PB6_PF_SD2_D2,
		PB7_PF_SD2_D3,
		PB8_PF_SD2_CMD,
		PB9_PF_SD2_CLK,
		PC7_PF_USBOTG_DATA5,
		PC8_PF_USBOTG_DATA6,
		PC9_PF_USBOTG_DATA0,
		PC10_PF_USBOTG_DATA2,
		PC11_PF_USBOTG_DATA1,
		PC12_PF_USBOTG_DATA4,
		PC13_PF_USBOTG_DATA3,
		PE0_PF_USBOTG_NXT,
		PE1_PF_USBOTG_STP,
		PE2_PF_USBOTG_DIR,
		PE24_PF_USBOTG_CLK,
		PE25_PF_USBOTG_DATA7,
		/* display */
		PA5_PF_LSCLK,
		PA6_PF_LD0,
		PA7_PF_LD1,
		PA8_PF_LD2,
		PA9_PF_LD3,
		PA10_PF_LD4,
		PA11_PF_LD5,
		PA12_PF_LD6,
		PA13_PF_LD7,
		PA14_PF_LD8,
		PA15_PF_LD9,
		PA16_PF_LD10,
		PA17_PF_LD11,
		PA18_PF_LD12,
		PA19_PF_LD13,
		PA20_PF_LD14,
		PA21_PF_LD15,
		PA22_PF_LD16,
		PA23_PF_LD17,
		PA26_PF_PS,
		PA28_PF_HSYNC,
		PA29_PF_VSYNC,
		PA31_PF_OE_ACD,
		/* external I2C */
		PD17_PF_I2C_DATA,
		PD18_PF_I2C_CLK,
	};

	pca100_usb_init();

	/* initizalize gpios */
	for (i = 0; i < ARRAY_SIZE(mode); i++)
		imx_gpio_mode(mode[i]);

	imx27_add_nand(&nand_info);
	imx27_add_fec(&fec_info);
	imx27_add_mmc1(NULL);
	imx27_add_fb(&pca100_fb_data);

#ifdef CONFIG_USB
	pca100_usb_register();
#endif

	nand = get_device_by_name("nand0");
	devfs_add_partition("nand0", 0x00000, 0x40000, DEVFS_PARTITION_FIXED, "self_raw");
	dev_add_bb_dev("self_raw", "self0");

	devfs_add_partition("nand0", 0x40000, 0x20000, DEVFS_PARTITION_FIXED, "env_raw");
	dev_add_bb_dev("env_raw", "env0");

	armlinux_set_bootparams((void *)0xa0000100);
	armlinux_set_architecture(2149);

	return 0;
}
Ejemplo n.º 18
0
static int pcm038_devices_init(void)
{
	int i;
	u64 uid = 0;
	char *envdev;
	long sram_size;

	unsigned int mode[] = {
		/* FEC */
		PD0_AIN_FEC_TXD0,
		PD1_AIN_FEC_TXD1,
		PD2_AIN_FEC_TXD2,
		PD3_AIN_FEC_TXD3,
		PD4_AOUT_FEC_RX_ER,
		PD5_AOUT_FEC_RXD1,
		PD6_AOUT_FEC_RXD2,
		PD7_AOUT_FEC_RXD3,
		PD8_AF_FEC_MDIO,
		PD9_AIN_FEC_MDC | GPIO_PUEN,
		PD10_AOUT_FEC_CRS,
		PD11_AOUT_FEC_TX_CLK,
		PD12_AOUT_FEC_RXD0,
		PD13_AOUT_FEC_RX_DV,
		PD14_AOUT_FEC_RX_CLK,
		PD15_AOUT_FEC_COL,
		PD16_AIN_FEC_TX_ER,
		PF23_AIN_FEC_TX_EN,
		PCM038_GPIO_FEC_RST | GPIO_GPIO | GPIO_OUT,
		/* UART1 */
		PE12_PF_UART1_TXD,
		PE13_PF_UART1_RXD,
		PE14_PF_UART1_CTS,
		PE15_PF_UART1_RTS,
		/* CSPI1 */
		PD25_PF_CSPI1_RDY,
		PD29_PF_CSPI1_SCLK,
		PD30_PF_CSPI1_MISO,
		PD31_PF_CSPI1_MOSI,
		PCM038_GPIO_SPI_CS0 | GPIO_GPIO | GPIO_OUT,
#ifdef CONFIG_MACH_PCM970_BASEBOARD
		PCM970_GPIO_SPI_CS1 | GPIO_GPIO | GPIO_OUT,
#endif
		/* Display */
		PA5_PF_LSCLK,
		PA6_PF_LD0,
		PA7_PF_LD1,
		PA8_PF_LD2,
		PA9_PF_LD3,
		PA10_PF_LD4,
		PA11_PF_LD5,
		PA12_PF_LD6,
		PA13_PF_LD7,
		PA14_PF_LD8,
		PA15_PF_LD9,
		PA16_PF_LD10,
		PA17_PF_LD11,
		PA18_PF_LD12,
		PA19_PF_LD13,
		PA20_PF_LD14,
		PA21_PF_LD15,
		PA22_PF_LD16,
		PA23_PF_LD17,
		PA24_PF_REV,
		PA25_PF_CLS,
		PA26_PF_PS,
		PA27_PF_SPL_SPR,
		PA28_PF_HSYNC,
		PA29_PF_VSYNC,
		PA30_PF_CONTRAST,
		PA31_PF_OE_ACD,
		/* USB OTG */
		PC7_PF_USBOTG_DATA5,
		PC8_PF_USBOTG_DATA6,
		PC9_PF_USBOTG_DATA0,
		PC10_PF_USBOTG_DATA2,
		PC11_PF_USBOTG_DATA1,
		PC12_PF_USBOTG_DATA4,
		PC13_PF_USBOTG_DATA3,
		PE0_PF_USBOTG_NXT,
		PCM038_GPIO_OTG_STP | GPIO_GPIO | GPIO_OUT,
		PE2_PF_USBOTG_DIR,
		PE24_PF_USBOTG_CLK,
		PE25_PF_USBOTG_DATA7,
		/* I2C1 */
		PD17_PF_I2C_DATA | GPIO_PUEN,
		PD18_PF_I2C_CLK,
		/* I2C2 */
		PC5_PF_I2C2_SDA,
		PC6_PF_I2C2_SCL,
	};

	/* configure 16 bit nor flash on cs0 */
	imx27_setup_weimcs(0, 0x22C2CF00, 0x75000D01, 0x00000900);

	/* configure SRAM on cs1 */
	imx27_setup_weimcs(1, 0x0000d843, 0x22252521, 0x22220a00);

	/* SRAM can be up to 2MiB */
	sram_size = get_ram_size((ulong *)MX27_CS1_BASE_ADDR, SZ_2M);
	if (sram_size)
		add_mem_device("ram1", MX27_CS1_BASE_ADDR, sram_size,
			       IORESOURCE_MEM_WRITEABLE);

	/* initizalize gpios */
	for (i = 0; i < ARRAY_SIZE(mode); i++)
		imx_gpio_mode(mode[i]);

	spi_register_board_info(pcm038_spi_board_info, ARRAY_SIZE(pcm038_spi_board_info));
	imx27_add_spi0(&pcm038_spi_0_data);

	pcm038_power_init();

	add_cfi_flash_device(DEVICE_ID_DYNAMIC, 0xC0000000, 32 * 1024 * 1024, 0);
	imx27_add_nand(&nand_info);
	imx27_add_fb(&pcm038_fb_data);

	imx27_add_i2c0(NULL);
	imx27_add_i2c1(NULL);

	/* Register the fec device after the PLL re-initialisation
	 * as the fec depends on the (now higher) ipg clock
	 */
	gpio_set_value(PCM038_GPIO_FEC_RST, 1);
	imx27_add_fec(&fec_info);

	/* Apply delay for STP line to stop ULPI */
	gpio_direction_output(PCM038_GPIO_OTG_STP, 1);
	mdelay(1);
	imx_gpio_mode(PE1_PF_USBOTG_STP);

	imx27_add_usbotg(&pcm038_otg_pdata);

	switch (bootsource_get()) {
	case BOOTSOURCE_NAND:
		devfs_add_partition("nand0", 0, SZ_512K,
				    DEVFS_PARTITION_FIXED, "self_raw");
		dev_add_bb_dev("self_raw", "self0");
		devfs_add_partition("nand0", SZ_512K, SZ_128K,
				    DEVFS_PARTITION_FIXED, "env_raw");
		dev_add_bb_dev("env_raw", "env0");
		envdev = "NAND";
		break;
	default:
		devfs_add_partition("nor0", 0, SZ_512K,
				    DEVFS_PARTITION_FIXED, "self0");
		devfs_add_partition("nor0", SZ_512K, SZ_128K,
				    DEVFS_PARTITION_FIXED, "env0");
		protect_file("/dev/env0", 1);
		envdev = "NOR";
	}

	pr_notice("Using environment in %s Flash\n", envdev);

	if (imx_iim_read(1, 0, &uid, 6) == 6)
		armlinux_set_serial(uid);
	armlinux_set_bootparams((void *)0xa0000100);
	armlinux_set_architecture(MACH_TYPE_PCM038);

	return 0;
}