void led_yellow_set_state( uint8_t state ) { if (state) outpw(P1DATA, (inpw(P1DATA) & ~0x1800) & ~0x200); else outpw(P1DATA, (inpw(P1DATA) & ~0x1800) | 0x200); }
void capClkRatio(BOOL ratio) { if(ratio==TRUE) outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x00100000); else outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xffEfffff); }
//***************************************************************************** // //! \brief ADC Interrupt Service Routine.According to the interrupt flags to call //! the corresponding callback function. //! //! \param None //! //! \return None // //***************************************************************************** void ADC_IRQHandler(void) { if(ADC->SR_BITS.ADF==1) { if(g_ptADCCallBack) g_ptADCCallBack(g_pu32UserData[0]); /* clear the A/D conversion flag */ /* "ADC->ADSR.ADF = 1;" is not recommended. It may clear CMPF0 and CMPF1. */ outpw(ADC_ADSR, (inpw(ADC_ADSR)&(~0x7))|0x1); } if(ADC->SR_BITS.CMPF0==1) { if(g_ptADCMP0CallBack) g_ptADCMP0CallBack(g_pu32UserData[1]); /* clear the A/D compare flag 0 */ /* "ADC->ADSR.CMPF0 = 1;" is not recommended. It may clear ADF and CMPF1. */ outpw(ADC_ADSR, (inpw(ADC_ADSR)&(~0x7))|0x2); } if(ADC->SR_BITS.CMPF1==1) { if(g_ptADCMP1CallBack) g_ptADCMP1CallBack(g_pu32UserData[2]); /* clear the A/D compare flag 1 */ /* "ADC->ADSR.CMPF1 = 1;" is not recommended. It may clear ADF and CMPF0. */ outpw(ADC_ADSR, (inpw(ADC_ADSR)&(~0x7))|0x4); } }
static void DELAY(int timeout) { /* NOTE: We assue the timer 0 is ready */ int init_cnt, timer_init; int cur_cnt; int max_cnt; init_cnt = inpw(REG_TDR0); timer_init = inpw(REG_TICR0); max_cnt = 0; do { cur_cnt = inpw(REG_TDR0); if(cur_cnt > init_cnt) cur_cnt = init_cnt + (timer_init - cur_cnt); else cur_cnt = init_cnt - cur_cnt; /* NOTE: the timeout value must be smaller than init_cnt */ if(cur_cnt >= timeout) break; }while(max_cnt++ < MAX_DELAY_LOOPS); dbg_printf("current system speed:%4d loops/us\n",max_cnt); }
/* addr: memory address len: byte count buf: buffer to put the read back data */ int usiRead(UINT32 addr, UINT32 len, UINT8 *buf) { int volatile i; outpw(REG_USI_SSR, inpw(REG_USI_SSR) | 0x01); // CS0 // read command outpw(REG_USI_Tx0, 03); usiTxLen(0, 8); usiActive(); // address outpw(REG_USI_Tx0, addr); usiTxLen(0, 24); usiActive(); // data for (i=0; i<len; i++) { outpw(REG_USI_Tx0, 0xff); usiTxLen(0, 8); usiActive(); *buf++ = inpw(REG_USI_Rx0) & 0xff; } outpw(REG_USI_SSR, inpw(REG_USI_SSR) & 0xfe); // CS0 return USI_NO_ERR; }
int usiEraseSector(UINT32 addr, UINT32 secCount) { int volatile i; for (i=0; i<secCount; i++) { usiWriteEnable(); outpw(REG_USI_SSR, inpw(REG_USI_SSR) | 0x01); // CS0 // erase command outpw(REG_USI_Tx0, 0xd8); usiTxLen(0, 8); usiActive(); // address outpw(REG_USI_Tx0, addr+i*0x10000); // 1 sector = 64KB usiTxLen(0, 24); usiActive(); outpw(REG_USI_SSR, inpw(REG_USI_SSR) & 0xfe); // CS0 // check status usiCheckBusy(); } return USI_NO_ERR; }
UINT16 usiReadID() { UINT16 volatile id; outpw(REG_USI_SSR, inpw(REG_USI_SSR) | 0x01); // CS0 // command 8 bit outpw(REG_USI_Tx0, 0x90); usiTxLen(0, 8); usiActive(); // address 24 bit outpw(REG_USI_Tx0, 0x000000); usiTxLen(0, 24); usiActive(); // data 16 bit outpw(REG_USI_Tx0, 0xffff); usiTxLen(0, 16); usiActive(); id = inpw(REG_USI_Rx0) & 0xffff; outpw(REG_USI_SSR, inpw(REG_USI_SSR) & 0xfe); // CS0 return id; }
void Int_Handler_FastI2C(void) #endif { unsigned int intst; intst=inpw(REG_FastSerialBusStatus); if ((intst&0x00000002)==0x02) { //k07055-1 if (_i2c_IrqHandlerTable[0]!=0) //k07055-1 _i2c_IrqHandlerTable[0](); intst=inpw(REG_FastSerialBusStatus)|0x02; outpw(REG_FastSerialBusStatus,intst); ++i2c_I2C_INT_CNT; // printf ("i2c_I2C_INT_CNT = %d\n", i2c_I2C_INT_CNT); if (_i2c_IrqHandlerTable[0]!=0) //k07055-1 _i2c_IrqHandlerTable[0](); //k07055-1 //#ifdef OPT_FastI2C_INT_TEST // cntFastI2C=cntFastI2C+1; //#endif //OPT_FastI2C_INT_TEST } #ifdef ECOS cyg_interrupt_acknowledge (vector); //k01105-1 return CYG_ISR_HANDLED; #endif //ECOS }
void i2cEnableInterrupt (BOOL bIsEnableINT) { UINT32 regdata; //k09144-1 sysSetInterruptType(IRQ_FI2C, LOW_LEVEL_SENSITIVE); //k08184-1 #ifdef ECOS if (bIsEnableINT) // enable I2C interrupt { cyg_interrupt_create(IRQ_FI2C, 1, 0, Int_Handler_FastI2C, NULL, &int_handle_I2C, &int_holder_I2C); cyg_interrupt_attach(int_handle_I2C); cyg_interrupt_unmask(IRQ_FI2C); } else { cyg_interrupt_mask(IRQ_FI2C); cyg_interrupt_detach(int_handle_I2C); } #else sysInstallISR(IRQ_LEVEL_1, IRQ_FI2C, (PVOID)Int_Handler_FastI2C); //IRQ_FI2C=24 if (bIsEnableINT) sysEnableInterrupt(IRQ_FI2C); //k03224-1 else sysDisableInterrupt (IRQ_FI2C); #endif _i2c_bINT_EN=bIsEnableINT; //k07195-1 //enable sensor I2C engine's interrupt if (bIsEnableINT) { regdata=inpw (REG_FastSerialBusCR)|0x02; outpw (REG_FastSerialBusCR,regdata); } //To clear interrupt status regdata=inpw (REG_FastSerialBusStatus)|0x03; outpw (REG_FastSerialBusStatus,regdata); /* enable I2C interrupt */ //k08204-1 sysEnableInterrupt(IRQ_FI2C); //k03224-1 }
static u16_t mdio_read(u8_t addr, u8_t reg) { outpw(REG_EMAC1_MIIDA, (addr << 8) | reg | 0xA0000); while (inpw(REG_EMAC1_MIIDA) & 0x20000); // wait busy flag clear return inpw(REG_EMAC1_MIID); }
/** * @brief This function reset the i2c interface and enable interrupt. * @param[in] param is interface number. * @return open status. * @retval 0 success. * @retval I2C_ERR_BUSY Interface already opened. * @retval I2C_ERR_NODEV Interface number out of range. */ int32_t i2cOpen(PVOID param) { i2c_dev *dev; if( (uint32_t)param >= I2C_NUMBER) return I2C_ERR_NODEV; dev = (i2c_dev *)((uint32_t)&i2c_device[(uint32_t)param] ); if( dev->openflag != 0 ) /* a card slot can open only once */ return(I2C_ERR_BUSY); /* Enable engine clock */ if((uint32_t)param == 0) outpw(REG_CLK_PCLKEN1, inpw(REG_CLK_PCLKEN1) | 0x1); else outpw(REG_CLK_PCLKEN1, inpw(REG_CLK_PCLKEN1) | 0x2); memset(dev, 0, sizeof(i2c_dev)); dev->base = ((uint32_t)param) ? I2C1_BA : I2C0_BA; _i2cReset(dev); dev->openflag = 1; return 0; }
static void plc_init(struct s_smc *smc, int p) { int i ; #ifndef MOT_ELM int rev ; /* Revision of PLC-x */ #endif /* MOT_ELM */ /* transit PCM state machine to MAINT state */ outpw(PLC(p,PL_CNTRL_B),0) ; outpw(PLC(p,PL_CNTRL_B),PL_PCM_STOP) ; outpw(PLC(p,PL_CNTRL_A),0) ; /* * if PLC-S then set control register C */ #ifndef MOT_ELM rev = inpw(PLC(p,PL_STATUS_A)) & PLC_REV_MASK ; if (rev != PLC_REVISION_A) #endif /* MOT_ELM */ { if (smc->y[p].pmd_scramble) { outpw(PLC(p,PL_CNTRL_C),PLCS_CONTROL_C_S) ; #ifdef MOT_ELM outpw(PLC(p,PL_T_FOT_ASS),PLCS_FASSERT_S) ; outpw(PLC(p,PL_T_FOT_DEASS),PLCS_FDEASSERT_S) ; #endif /* MOT_ELM */ } else { outpw(PLC(p,PL_CNTRL_C),PLCS_CONTROL_C_U) ; #ifdef MOT_ELM outpw(PLC(p,PL_T_FOT_ASS),PLCS_FASSERT_U) ; outpw(PLC(p,PL_T_FOT_DEASS),PLCS_FDEASSERT_U) ; #endif /* MOT_ELM */ } } /* * set timer register */ for ( i = 0 ; pltm[i].timer; i++) /* set timer parameter reg */ outpw(PLC(p,pltm[i].timer),pltm[i].para) ; (void)inpw(PLC(p,PL_INTR_EVENT)) ; /* clear interrupt event reg */ plc_clear_irq(smc,p) ; outpw(PLC(p,PL_INTR_MASK),plc_imsk_na); /* enable non active irq's */ /* * if PCM is configured for class s, it will NOT go to the * REMOVE state if offline (page 3-36;) * in the concentrator, all inactive PHYS always must be in * the remove state * there's no real need to use this feature at all .. */ #ifndef CONCENTRATOR if ((smc->s.sas == SMT_SAS) && (p == PS)) { outpw(PLC(p,PL_CNTRL_B),PL_CLASS_S) ; } #endif }
UINT8 MY_Read_GPIO7(void) { outpw(REG_GPIO_OE,inpw(REG_GPIO_OE)|0x00000080); if ((inpw(REG_GPIO_STS)&0x00000080)==0x00000080) return 1; else return 0; }
void led_green_set_state( uint8_t state ) { outpw(ETHPPPTR,0x114); // –егистр SelfCTL CS8900A if(state) outpw(ETHPPDATAL, inpw(ETHPPDATAL) | 0x4000); else outpw(ETHPPDATAL, inpw(ETHPPDATAL) & ~0x4000); }
void capPacketOut(T_CAP_SET* ptCapSet) { BOOL bIsPacOut; bIsPacOut = ptCapSet->bIsPacEnable; if(bIsPacOut) outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x00000100); else outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xfffffeff); }
void capPlanarSticker(T_CAP_SET* ptCapSet) { BOOL bIsPlaSticker; bIsPlaSticker = ptCapSet->bIsPlaSticker; if(bIsPlaSticker==TRUE)//Enable plabar overlay ? outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x0800); else outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xfffff7ff); }
/** * @brief Enter initialization mode * @param[in] uCAN CAN channel. * @return None * @details This function is used to set CAN to enter initialization mode and enable access bit timing * register. After bit timing configuration ready, user must call CAN_LeaveInitMode() * to leave initialization mode and lock bit timing register to let new configuration * take effect. */ void CAN_EnterInitMode(UINT32 uCAN) { UINT32 uOffset = uCAN * CAN_OFFSET; UINT32 uRegAddress; uRegAddress = REG_CAN0_CON + uOffset; outpw(uRegAddress, inpw(uRegAddress)|CAN_CON_INIT_Msk); outpw(uRegAddress, inpw(uRegAddress)|CAN_CON_CCE_Msk); }
void capPacketSticker(T_CAP_SET* ptCapSet) { BOOL bIsPacSticker; bIsPacSticker = ptCapSet->bIsPacSticker; if(bIsPacSticker==TRUE)//Enable packet overlay ? outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x1000); else outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xffffefff); }
/////////////////////////////////////////////////////////////////////////////// // // FUNCTION // gfxWaitEngineReady() // // DESCRIPTION // This function is used to wait for the previous command complete in // order to process a new graphics engine command. // // INPUTS // None // // OUTPUTS // None // // RETURN // None // /////////////////////////////////////////////////////////////////////////////// VOID gfxWaitEngineReady(VOID) { if ((inpw(REG_GE_TRIGGER) & 0x01) != 0) // engine busy? { while ((inpw(REG_GE_INTS) & 0x01) == 0); // wait for command complete } outpw(REG_GE_INTS, 1); // clear interrupt status }
void capPlanarOut(T_CAP_SET* ptCapSet) { BOOL bIsPlaOut; bIsPlaOut = ptCapSet->bIsPlaEnable; if(bIsPlaOut) outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)|0x00000200); else outpw(REG_CAPFuncEnable,inpw(REG_CAPFuncEnable)&0xfffffdff); }
//***************************************************************************** // //! \brief Enable the interrupt function of the specified GPIO pin. Except for //! Port3-2 and Port3-2 pins are for external interrupt used. //! //! \param port E_DRVGPIO_PORT, specify GPIO port. It could be E_PORT0, //! E_PORT1, E_PORT2, E_PORT3 and E_PORT4. //! //! \param pin Specify pin of the GPIO port. It could be E_PIN0, E_PIN2 ... ~ //! E_PIN7. But the Port3-2 and Port3-3 are only used for external interrupt //! 0/1. //! //! \param Type E_DRVGPIO_INT_TYPE, specify the interrupt trigger type. It //! could be E_IO_RISING, E_IO_FALLING or E_IO_BOTH_EDGE and it's meaning the //! interrupt function enable by rising egde/high level, falling edge/low level //! or both riging edge and falling egde. If the interrupt mode is E_MODE_LEVEL //! and interrupt type is E_BOTH_EDGE¡Athen calling this API is ignored. //! //! \param Mode E_DRVGPIO_INT_MODE, specify the interrupt mode. It could be //! E_MODE_EDGE or E_MODE_LEVEL to control the interrupt is by edge trigger or //! by level trigger. If the interrupt mode is E_MODE_LEVEL and interrupt type //! is E_BOTH_EDGE¡Athen calling this API is ignored. //! //! \return E_SUCCESS Operation successful //! E_DRVGPIO_ARGUMENT Incorrect argument // //***************************************************************************** int32_t DrvGPIO_EnableInt(E_DRVGPIO_PORT port, uint32_t pin, E_DRVGPIO_INT_TYPE Type, E_DRVGPIO_INT_MODE Mode) { volatile uint32_t u32Reg = (uint32_t)((uint32_t)&PORT0->IEN + (port*PORT_OFFSET)); if ((port == E_PORT3) && ((pin == E_EINT0_PIN) || (pin == E_EINT1_PIN))) { // // P32 is EINT0, P33 is EINT1. Both of them can't be assigned to gereral P3 // interrupt // return E_DRVGPIO_ARGUMENT; } // // Configure the interrupt to be rising/falling when edge trigger or high/low // level when level trigger // if (Type == E_IO_RISING) outpw(u32Reg, inpw(u32Reg) | (1<<(pin+16))); else if (Type == E_IO_FALLING) outpw(u32Reg , inpw(u32Reg) | (1<<pin)); else if (Type == E_IO_BOTH_EDGE) outpw(u32Reg , inpw(u32Reg) | (1<<pin)| (1<<(pin+16))); else return E_DRVGPIO_ARGUMENT; // // Configure to be level trigger or edge trigger // u32Reg = (uint32_t)((uint32_t)&PORT0->IMD + (port*PORT_OFFSET)); if (Mode == E_MODE_EDGE) outpw(u32Reg, inpw(u32Reg) & (~(1<<pin))); else if (Mode == E_MODE_LEVEL) outpw(u32Reg, inpw(u32Reg) | (1<<pin)); else return E_DRVGPIO_ARGUMENT; // // Configure the relative interrupt of M0 // if ((port == E_PORT0) || (port == E_PORT1)) { NVIC_SetPriority(GPIO_P0P1_IRQn, (1<<__NVIC_PRIO_BITS) - 2); NVIC_EnableIRQ(GPIO_P0P1_IRQn); } if ((port == E_PORT2) || (port == E_PORT3) || (port == E_PORT4)) { NVIC_SetPriority(GPIO_P2P3P4_IRQn, (1<<__NVIC_PRIO_BITS) - 2); NVIC_EnableIRQ(GPIO_P2P3P4_IRQn); } return E_SUCCESS; }
static void rtl_error(struct dev *dev, int status, int link_changed) { struct nic *tp = (struct nic *) dev->privdata; long ioaddr = tp->iobase; kprintf("%s: Abnormal interrupt, status %8.8x\n", dev->name, status); // Update the error count tp->stats.rx_missed_errors += inpd(ioaddr + RxMissed); outpd(ioaddr + RxMissed, 0); if (status & RxUnderrun) { // This might actually be a link change event if ((tp->flags & HAS_LNK_CHNG) && link_changed) { // Really link-change on new chips int lpar = inpw(ioaddr + NWayLPAR); int duplex = (lpar & 0x0100) || (lpar & 0x01C0) == 0x0040 || tp->duplex_lock; // Do not use MII_BMSR as that clears sticky bit //if (inpw(ioaddr + GPPinData) & 0x0004) // netif_link_down(dev); //else // netif_link_up(dev); kprintf("%s: Link changed, link partner %4.4x new duplex %d\n", dev->name, lpar, duplex); tp->full_duplex = duplex; // Only count as errors with no link change status &= ~RxUnderrun; } else { // If this does not work, we will do rtl_hw_start outp(ioaddr + ChipCmd, CmdTxEnb); rtl8139_set_rx_mode(dev); // Reset the multicast list outp(ioaddr + ChipCmd, CmdRxEnb | CmdTxEnb); tp->stats.rx_errors++; tp->stats.rx_fifo_errors++; } } if (status & (RxOverflow | RxErr | RxFIFOOver)) tp->stats.rx_errors++; if (status & (PCSTimeout)) tp->stats.rx_length_errors++; if (status & RxFIFOOver) tp->stats.rx_fifo_errors++; if (status & RxOverflow) { tp->stats.rx_over_errors++; tp->cur_rx = inpw(ioaddr + RxBufAddr) % tp->rx_buf_len; outpw(ioaddr + RxBufPtr, tp->cur_rx - 16); } if (status & PCIErr) { unsigned long pci_cmd_status; pci_cmd_status = pci_read_config_dword(dev->unit, PCI_CONFIG_CMD_STAT); kprintf(KERN_ERR "%s: PCI Bus error %4.4x.\n", dev->name, pci_cmd_status); } }
void capOnTheFly(T_CAP_SET* ptCapSet) { if(ptCapSet->pOTF->bIsOnTheFly==TRUE) { outpw(REG_CAPPlaYFB0StaAddr, ( (inpw(REG_CAPPlaYFB0StaAddr) & 0x00ffffff)|((UINT32)(ptCapSet->pOTF->eLine)<<24)) ); outpw(REG_CAPFuncEnable,(inpw(REG_CAPFuncEnable)|0x8000)); } else outpw(REG_CAPFuncEnable,(inpw(REG_CAPFuncEnable)&0xffff7fff)); }
uint32_t dosbox_id_read_data_nrl() { uint32_t r; #if TARGET_MSDOS == 32 r = (uint32_t)inpd(DOSBOX_IDPORT(DOSBOX_ID_DATA)); #else r = (uint32_t)inpw(DOSBOX_IDPORT(DOSBOX_ID_DATA)); r |= (uint32_t)inpw(DOSBOX_IDPORT(DOSBOX_ID_DATA)) << (uint32_t)16UL; #endif return r; }
int usiWriteDisable() { outpw(REG_USI_SSR, inpw(REG_USI_SSR) | 0x01); // CS0 outpw(REG_USI_Tx0, 0x04); usiTxLen(0, 8); usiActive(); outpw(REG_USI_SSR, inpw(REG_USI_SSR) & 0xfe); // CS0 return USI_NO_ERR; }
static void pwr_disable_vpost(void) { int cnt; if ((readw(REG_LCM_DCCS)&0x00000002)==0x00000002) { outpw(REG_LCM_DCCS, inpw(REG_LCM_DCCS) & ~(1<<3)); cnt = 50000; while( (inpw(REG_LCM_DCCS)&(1<<25)) && cnt--); writew(REG_LCM_DCCS,readw(REG_LCM_DCCS)&0xfffffff7); //display_out-disable } }
/** * @brief Leave initialization mode * @param[in] uCAN CAN channel. * @return None * @details This function is used to set CAN to leave initialization mode to let * bit timing configuration take effect after configuration ready. */ void CAN_LeaveInitMode(UINT32 uCAN) { UINT32 uOffset = uCAN * CAN_OFFSET; UINT32 uRegAddress, uRegVal; uRegAddress = REG_CAN0_CON + uOffset; uRegVal = inpw(uRegAddress); uRegVal &= (~(CAN_CON_INIT_Msk | CAN_CON_CCE_Msk)); outpw(uRegAddress, uRegVal); while(inpw(uRegAddress) & CAN_CON_INIT_Msk); }
void mcuWakeup() { /* Set GPIO for MCU */ mcuLock(); outpw(REG_GPIOB_OE,inpw(REG_GPIOB_OE) & ~MCU_GPIO); //19 output; outpw(REG_GPIOB_DAT,inpw(REG_GPIOB_DAT) & ~MCU_GPIO); //19 low tt_msleep(100); outpw(REG_GPIOB_DAT,inpw(REG_GPIOB_DAT) | MCU_GPIO); //19 high tt_msleep(100); mcuUnlock(); }
/* * read long value from buffer memory over memory data register (MDR), */ static u_long read_mdr(struct s_smc *smc, unsigned int addr) { long p ; CHECK_NPP() ; MARR(addr) ; outpw(FM_A(FM_CMDREG1),FM_IRMEMWO) ; CHECK_NPP() ; /* needed for PCI to prevent from timeing violations */ /* p = MDRR() ; */ /* bad read values if the workaround */ /* smc->hw.mc_dummy = *((short volatile far *)(addr)))*/ /* is used */ p = (u_long)inpw(FM_A(FM_MDRU))<<16 ; p += (u_long)inpw(FM_A(FM_MDRL)) ; return(p) ; }
void GPIO_ISR_USBPower(void) { USB_Power_Flag = MY_Read_GPIO7(); if (USB_Power_Flag==1) { outpw(REG_USB_CTL,(inpw(REG_USB_CTL)|0x00000001));//D+ high } else { USBModeFlag=0; outpw(REG_USB_CTL,(inpw(REG_USB_CTL)&0xfffffffe));//D+ low } outpw(REG_GPIO_IS,0x00000080); }