Ejemplo n.º 1
1
/**
 * Write the boot code and other various things into the CPU memory.
 */
void emu_rom (gleam_emu_t *emu) {
	gleam_mem_t *mem = emu->mem;

	// Write 0 to location 0
	// Write a small code fragment that sets cp to 0
	mem_write(0, 0, mem);
	mem_write(1, 0, mem);
	mem_write(2, cp, mem);
}
Ejemplo n.º 2
0
static int glut_abi_get_event(X86Context *ctx)
{
	struct x86_regs_t *regs = ctx->regs;
	struct mem_t *mem = ctx->mem;

	struct glut_event_t *event;
	struct glut_event_t idle_event;

	unsigned int event_ptr;

	/* Read arguments */
	event_ptr = regs->ecx;
	glut_debug("\tevent_ptr=0x%x\n", event_ptr);

	/* Get event at the head of the queue. If there is no event, create an
	 * event of type 'idle'. */
	event = glut_event_dequeue();
	if (event)
	{
		mem_write(mem, event_ptr, sizeof(struct glut_event_t), event);
		glut_event_free(event);
	}
	else
	{
		memset(&idle_event, 0, sizeof(struct glut_event_t));
		idle_event.type = glut_event_idle;
		mem_write(mem, event_ptr, sizeof(struct glut_event_t), &idle_event);
	}

	/* Return event */
	return 0;
}
Ejemplo n.º 3
0
void dp8390_device::recv(UINT8 *buf, int len) {
	int i;
	UINT16 start = (m_regs.curr << 8), offset;
	UINT32 high16;
	if(m_reset) return;
	if(m_regs.curr == m_regs.pstop) start = m_regs.pstart << 8;
	offset = start + 4;
	high16 = (m_regs.dcr & 4)?m_regs.rsar<<16:0;
	if(buf[0] & 1) {
		if(!(m_regs.rcr & 4) && !memcmp((const char *)buf, "\xff\xff\xff\xff\xff\xff", 6)) return;
		m_regs.rsr = 0x20;
	} else m_regs.rsr = 0;
	len &= 0xffff;

	for(i = 0; i < len; i++) {
		mem_write(high16 + offset, buf[i]);
		offset++;
		if(!(offset & 0xff)) {
			if((offset >> 8) == m_regs.pstop) offset = m_regs.pstart << 8;
			if((offset >> 8) == m_regs.bnry) return recv_overflow();
		}
	}
	m_regs.rsr |= 1;
	m_regs.isr |= 1;
	m_regs.curr = (offset >> 8) + ((offset & 0xff)?1:0);
	if(m_regs.curr == m_regs.pstop) m_regs.curr = m_regs.pstart;
	len += 4;
	mem_write(start, m_regs.rsr);
	mem_write(start+1, m_regs.curr);
	mem_write(start+2, len & 0xff);
	mem_write(start+3, len >> 8);
	check_irq();
}
Ejemplo n.º 4
0
void omapconf_emu_disable_domain()
{
	if (cpu_is_omap44xx())
		//omap4conf_emu_disable_domain();
		mem_write(OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 0);
	else if (cpu_is_omap54xx())
		//omap5conf_emu_disable_domain();
	        mem_write(OMAP5430_CM_L3INSTR_L3_MAIN_3_CLKCTRL, 0x0);
}
Ejemplo n.º 5
0
/* ------------------------------------------------------------------------*//**
 * @FUNCTION		emu44xx_disable
 * @BRIEF		Power OFF EMU domain and instrumentation
 * @DESCRIPTION		Power OFF EMU domain and instrumentation
 *//*------------------------------------------------------------------------ */
void emu44xx_disable(void)
{
	mem_write(OMAP4430_PRM_PRM_PROFILING_CLKCTRL, 0x1);
	mem_write(OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 0);
	mem_write(OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL, 0);
	mem_write(OMAP4430_CM_EMU_CLKSTCTRL, 0x3);

	emu_enabled = 0;
}
Ejemplo n.º 6
0
void uart_init(void)
{
	mem_write(0x6000,0b00000011); // master reset
	MDELAY(1);
	
	mem_write(0x6000,0b10010101); // clock/16 - 8N1 - receive int
	CYCLE_WAIT(8);
	
	mem_read(0xe000); // read status to start the device
	CYCLE_WAIT(8);
}
Ejemplo n.º 7
0
static int x86_clrt_func_init(struct x86_ctx_t *ctx)
{
	struct x86_regs_t *regs = ctx->regs;
	struct mem_t *mem = ctx->mem;

	unsigned int version_ptr;
	struct x86_clrt_version_t version;

	/* Arguments */
	version_ptr = regs->ecx;
	x86_clrt_debug("\tversion_ptr=0x%x\n", version_ptr);

	/* Return version */
	assert(sizeof(struct x86_clrt_version_t) == 8);
	version.major = X86_CLRT_VERSION_MAJOR;
	version.minor = X86_CLRT_VERSION_MINOR;
	mem_write(mem, version_ptr, sizeof version, &version);
	x86_clrt_debug("\tMulti2Sim OpenCL implementation in host: v. %d.%d.\n",
		X86_CLRT_VERSION_MAJOR, X86_CLRT_VERSION_MINOR);
	x86_clrt_debug("\tMulti2Sim OpenCL Runtime in guest: v. %d.%d.\n",
		version.major, version.minor);

	/* Return success */
	return 0;
}
Ejemplo n.º 8
0
/* ------------------------------------------------------------------------*//**
 * @FUNCTION		powerdm_emu_disable
 * @BRIEF		Power OFF EMU domain and clocks.
 * @DESCRIPTION		Power OFF EMU domain and clocks.
 *//*------------------------------------------------------------------------ */
void powerdm_emu_disable(void)
{
	if (cpu_is_omap44xx()) {
		mem_write(OMAP4430_CM_L3INSTR_L3_3_CLKCTRL, 0);
	} else if (cpu_is_omap54xx()) {
		if (cpu_revision_get() == REV_ES1_0)
			mem_write(OMAP5430ES1_CM_L3INSTR_L3_MAIN_3_CLKCTRL,
				0x0);
		else
			mem_write(OMAP5430_CM_L3INSTR_L3_MAIN_3_CLKCTRL, 0x0);
	} else {
		fprintf(stderr,
			"omapconf: %s(): warning: cpu not supported, skipping it.\n",
			__func__);
	}
}
Ejemplo n.º 9
0
void si_ndrange_const_buf_write(struct si_ndrange_t *ndrange,
                                int const_buf_num, int offset, void *pvalue, unsigned int size)
{
    unsigned int addr;

    struct si_buffer_desc_t buffer_desc;

    /* Sanity check */
    assert(const_buf_num < 2);
    if (const_buf_num == 0)
    {
        assert(offset + size < SI_EMU_CONST_BUF_0_SIZE);
    }
    else if (const_buf_num == 1)
    {
        assert(offset + size < SI_EMU_CONST_BUF_1_SIZE);
    }

    mem_read(si_emu->global_mem, ndrange->const_buf_table +
             const_buf_num*SI_EMU_CONST_BUF_TABLE_ENTRY_SIZE,
             sizeof(buffer_desc), &buffer_desc);

    addr = (unsigned int)buffer_desc.base_addr;
    addr += offset;

    /* Write */
    mem_write(si_emu->global_mem, addr, size, pvalue);
}
Ejemplo n.º 10
0
static int mips_sys_fstat64_impl(struct mips_ctx_t *ctx)
{
	struct mips_regs_t *regs = ctx->regs;
	struct mem_t *mem = ctx->mem;

	int fd;
	int host_fd;
	int err;

	unsigned int statbuf_ptr;

	struct stat statbuf;
	struct sim_stat64_t sim_statbuf;

	/* Arguments */
	fd = regs->regs_R[4];
	statbuf_ptr = regs->regs_R[5];
	mips_sys_debug("  fd=%d, statbuf_ptr=0x%x\n", fd, statbuf_ptr);

	/* Get host descriptor */
	host_fd = mips_file_desc_table_get_host_fd(ctx->file_desc_table, fd);
	mips_sys_debug("  host_fd=%d\n", host_fd);

	/* Host call */
	err = fstat(host_fd, &statbuf);
	if (err == -1)
		return -errno;

	/* Return */
	mips_sys_stat_host_to_guest(&sim_statbuf, &statbuf);
	mem_write(mem, statbuf_ptr, sizeof sim_statbuf, &sim_statbuf);
	return 0;
}
Ejemplo n.º 11
0
/*
 * memoryStage - writes or reads from memory when needed
 *               Updates values for writebackStage
 *
 * params - forwardType * forward, statusType* status, bubbleType* bubble
 * 
 */
void memoryStage(forwardType * forward, statusType* status, bubbleType* bubble)
{
    unsigned int addr = mem_addr();
    unsigned int valM = M.valA;
    bool memError = false;
    unsigned int stat = M.stat;
    
    if(mem_write())
    {
        putWord(addr, valM, &memError);
    }
    if(mem_read())
    {
        valM = getWord(addr, &memError);
    }
    if(memError)
        stat = SADR;
    
    //forward values
    forward->M_dstM = M.dstM;
    forward->M_dstE = M.dstE;
    forward->m_valM = valM;
    forward->M_valE = M.valE;
    forward->M_Cnd = M.Cnd;
    forward->M_valA = M.valA;
    forward->M_icode = M.icode;
    status->m_stat = stat;
    
    bubble->M_icode = M.icode;

    updateWregister(stat, M.icode, M.valE, valM, M.dstE, M.dstM);
}
Ejemplo n.º 12
0
void mips_isa_SB_impl(struct mips_ctx_t *ctx)
{
	unsigned char temp = mips_gpr_get_value(ctx,RT);
	unsigned int addr = mips_gpr_get_value(ctx,RS) + IMM;
	mem_write(ctx->mem, addr, sizeof(unsigned char), &temp);
	mips_isa_inst_debug("byte written: %x",temp);
}
Ejemplo n.º 13
0
void
bmlipc_write_data (BmlIpcBuf * self, int size, char *buffer)
{
  if (mem_write (self, buffer, size, 1) != 1) {
    self->io_error = 1;
  }
}
Ejemplo n.º 14
0
/* ------------------------------------------------------------------------*//**
 * @FUNCTION		stm_atb_capture_disable
 * @BRIEF		disable STM trace capture in ETB via ATB
 * @RETURNS		0 in case of success
 *			OMAPCONF_ERR_NOT_AVAILABLE
 * @DESCRIPTION		disable STM trace capture in ETB via ATB
 *			NB: make sure EMU domain is ON before calling this
 *			function.
 *			NB: blocking until STM FIFO is empty
 *//*------------------------------------------------------------------------ */
int stm_atb_capture_disable(void)
{
	unsigned int stm_sysstatus;

	if (!emu44xx_is_enabled()) {
		printf("stm_atb_capture_disable(): EMU domain OFF!!!\n");
		return OMAPCONF_ERR_NOT_AVAILABLE;
	}
	if (!stm_is_claimed()) {
		printf("stm_atb_capture_disable(): STM not claimed!\n");
		return OMAPCONF_ERR_INTERNAL;
	}

	do {
		mem_read(OMAP4430_STM_SYSSTATUS, &stm_sysstatus);
	} while (stm_sysstatus != 0x00000101);
	dprintf("stm_atb_capture_disable(): STM FIFO empty.\n");

	/* Disable ATB */
	mem_write(OMAP4430_ATB_CONFIG, 0x00000000);

	dprintf("stm_atb_capture_disable(): ATB capture disabled.\n");

	#ifdef STM_OMAP4_DEBUG
	stm_last_header_pos_get();
	stm_dump_regs();
	#endif

	return 0;
}
Ejemplo n.º 15
0
/* ------------------------------------------------------------------------*//**
 * @FUNCTION		stm_hw_master_disable
 * @BRIEF		disable stm hw master
 * @RETURNS		0 in case of success
 *			OMAPCONF_ERR_NOT_AVAILABLE
 *			OMAPCONF_ERR_INTERNAL
 *			OMAPCONF_ERR_ARG
 * @param[in]		pos: register position
 * @DESCRIPTION		disable stm hw master
 *//*------------------------------------------------------------------------ */
int stm_hw_master_disable(unsigned char pos)
{
	unsigned int stm_hwmctrl, mask;

	if (!emu44xx_is_enabled()) {
		printf("stm_hw_master_disable(): "
			"trying to enable ETB but EMU domain OFF!!!\n");
		return OMAPCONF_ERR_NOT_AVAILABLE;
	}
	if (!stm_is_claimed()) {
		printf("stm_hw_master_disable(): STM not claimed!\n");
		return OMAPCONF_ERR_INTERNAL;
	}
	if (pos > 3) {
		printf("stm_hw_master_disable(): pos (%d) > 3!\n", pos);
		return OMAPCONF_ERR_ARG;
	}

	mem_read(OMAP4430_STM_HWMCTRL, &stm_hwmctrl);
	pos = 2 + (8 * pos);
	mask = ~(0x1F << pos);
	stm_hwmctrl &= mask;
	mem_write(OMAP4430_STM_HWMCTRL, stm_hwmctrl);

	return 0;
}
Ejemplo n.º 16
0
int mem_push(int32_t word) 
{
    /* turn the 32 bit word into a 4 byte buffer according 
     * to the big endian notation.
     * we could also use the posix function htonl
     */
    uint8_t buffer[4] = { 0x0 };
    buffer[0] = word >> 24;
    buffer[1] = word >> 16;
    buffer[2] = word >>  8;
    buffer[3] = word;

    registers[SP].value -= 4;
    if (registers[SP].value <= registers[HE].value) {
        /* We generate a stack overflow interrupt if the 
         * SP register has a value less or equal than the HE register,
         * which stores the address of the last byte on the heap.
         */
        logmsg(LOG_WARN, "Mem: Stack Overflow: can not PUSH");
        registers[SP].value += 4; // reset SP
        interrupt(INT_STACK_OVERFLOW);
        return -1;
    }
    
    return (mem_write(buffer, registers[SP].value, 4));
}
Ejemplo n.º 17
0
void mips_isa_SC_impl(struct mips_ctx_t *ctx) {
  unsigned int temp = mips_gpr_get_value(ctx, RT);
  //	if()
  mem_write(ctx->mem, mips_gpr_get_value(ctx, RS) + IMM, 4, &temp);
  mips_gpr_set_value(ctx, RT, 1);
  // FIXME: revisit details in m2s-1.3/srs/kernel/machine.def
}
Ejemplo n.º 18
0
void mips_isa_SW_impl(struct mips_ctx_t *ctx) {
  unsigned int temp = mips_gpr_get_value(ctx, RT);
  unsigned int addr = mips_gpr_get_value(ctx, RS) + SEXT32(IMM, 16);

  mem_write(ctx->mem, addr, 4, &temp);
  mips_isa_inst_debug(" value stored: 0x%x", temp);
}
Ejemplo n.º 19
0
unsigned int si_opencl_kernel_get_work_group_info(struct si_opencl_kernel_t *kernel, unsigned int name,
	struct mem_t *mem, unsigned int addr, unsigned int size)
{
	unsigned int size_ret = 0;
	void *info = NULL;

	unsigned long long local_mem_size = 0;
	unsigned int max_work_group_size = 256;  /* FIXME */

	unsigned int compile_work_group_size[3];
	compile_work_group_size[0] = 1;  /* FIXME */
	compile_work_group_size[1] = 1;  /* FIXME */
	compile_work_group_size[2] = 1;  /* FIXME */

	switch (name)
	{

	case 0x11b0:  /* CL_KERNEL_WORK_GROUP_SIZE */
		info = &max_work_group_size;
		size_ret = 4;
		break;

	case 0x11b1:  /* CL_KERNEL_COMPILE_WORK_GROUP_SIZE */
		info = compile_work_group_size;
		size_ret = 4 * 3;
		break;

	case 0x11b2:  /* CL_KERNEL_LOCAL_MEM_SIZE */
	{
		int i;
		struct si_opencl_kernel_arg_t *arg;

		/* Compute local memory usage */
		local_mem_size = kernel->func_mem_local;
		for (i = 0; i < list_count(kernel->arg_list); i++)
		{
			arg = list_get(kernel->arg_list, i);
			if (arg->mem_scope == SI_OPENCL_MEM_SCOPE_LOCAL)
				local_mem_size += arg->size;
		}

		/* Return it */
		info = &local_mem_size;
		size_ret = 8;
		break;
	}
	
	case 0x11b3:  /* CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE */
	case 0x11b4:  /* CL_KERNEL_PRIVATE_MEM_SIZE */
	default:
		fatal("%s: invalid or not implemented value for 'name' (0x%x)\n%s",
			__FUNCTION__, name, si_err_opencl_param_note);
	}
	
	/* Write to memory and return size */
	assert(info);
	if (addr && size >= size_ret)
		mem_write(mem, addr, size_ret, info);
	return size_ret;
}
Ejemplo n.º 20
0
void
bmlipc_write_int (BmlIpcBuf * self, int buffer)
{
  if (mem_write (self, &buffer, sizeof (buffer), 1) != 1) {
    self->io_error = 1;
  }
}
Ejemplo n.º 21
0
void
bmlipc_write_string (BmlIpcBuf * self, char *buffer)
{
  if (mem_write (self, buffer, strlen (buffer) + 1, 1) != 1) {
    self->io_error = 1;
  }
}
Ejemplo n.º 22
0
unsigned int evg_opencl_context_get_info(struct evg_opencl_context_t *context,
	unsigned int name, struct mem_t *mem, unsigned int addr, unsigned int size)
{
	unsigned int num_devices = 1;

	unsigned int size_ret = 0;
	void *info = NULL;

	switch (name)
	{

	case 0x1081:  /* CL_CONTEXT_DEVICES */
		size_ret = 4;
		info = &context->device_id;
		break;

	case 0x1083:  /* CL_CONTEXT_NUM_DEVICES */
		size_ret = 4;
		info = &num_devices;
		break;

	case 0x1080:  /* CL_CONTEXT_REFERENCE_COUNT */
	case 0x1082:  /* CL_CONTEXT_PROPERTIES */
	default:
		fatal("opencl_context_get_info: invalid or not implemented value for 'name' (0x%x)\n%s",
			name, evg_err_opencl_param_note);
	}
	
	/* Write to memory and return size */
	assert(info);
	if (addr && size >= size_ret)
		mem_write(mem, addr, size_ret, info);
	return size_ret;
}
Ejemplo n.º 23
0
void si_ndrange_init_uav_table(struct si_ndrange_t *ndrange)
{
	int i;
	uint32_t buffer_addr;
	struct si_opencl_mem_t *mem_obj;
	struct si_buffer_resource_t buf_desc;

	/* Zero-out the buffer resource descriptor */
	memset(&buf_desc, 0, 16);

	for (i = 0; i < list_count(ndrange->uav_list); i++)
	{
		   /* Get the memory object for the buffer */
		   mem_obj = list_get(ndrange->uav_list, i);

		   /* Get the address of the buffer in global memory */
		   buffer_addr = mem_obj->device_ptr;

		   /* Initialize the buffer resource descriptor for this UAV */
		   buf_desc.base_addr = buffer_addr;

		   assert(UAV_TABLE_START + 320 + i*32 <= UAV_TABLE_START + UAV_TABLE_SIZE - 32);

		   /* Write the buffer resource descriptor into the UAV table at offset 320
			* with 32 bytes spacing */
		   mem_write(si_emu->global_mem, UAV_TABLE_START + 320 + i*32, 16, &buf_desc);
	}
}
Ejemplo n.º 24
0
void NOINLINE uart_send(uint8_t data)
{
		uint8_t status;

	// wait until previous byte is transmitted

	do
	{
		BLOCK_INT
		{
			status=mem_read(0xe000);
		}
		
		CYCLE_WAIT(4);
	}
	while(!(status&0x02));

	// send the new one

	BLOCK_INT
	{
		mem_write(0x6001,data);
		CYCLE_WAIT(4);
	}
}
Ejemplo n.º 25
0
/* ------------------------------------------------------------------------*//**
 * @FUNCTION		coresight_etb_buffer_read
 * @BRIEF		read ETB RAM buffer data at given position
 * @RETURNS		0 in case of success
 *			OMAPCONF_ERR_ARG in case of error
 * @param[in]		rrp: read pointer (position in buffer from 0
 *			to OMAP44xx_ETB_RAM_SIZE/4)
 * @param[in,out]	rrd: data read from ETB buffer at position 'rrp'
 * @DESCRIPTION		read ETB RAM buffer data at given position
 *//*------------------------------------------------------------------------ */
int coresight_etb_buffer_read(unsigned int rrp, unsigned int *rrd)
{
	if (rrp >= (OMAP44xx_ETB_RAM_SIZE / 4)) {
		fprintf(stderr, "coresight_etb_buffer_read(): "
			"rrp (%d) >= OMAP44xx_ETB_RAM_SIZE / 4 (%d)!\n",
			rrp, OMAP44xx_ETB_RAM_SIZE / 4);
		return OMAPCONF_ERR_ARG;
	}
	if (rrd == NULL) {
		fprintf(stderr, "coresight_etb_buffer_read(): rrd == NULL!\n");
		return OMAPCONF_ERR_ARG;
	}

	/* Set read pointer */
	mem_write(OMAP4430_ETB_RRP, rrp);

	/* Read data in ETB at location pointed by  rrp */
	#ifdef CORESIGHT_ETB_SAVE_TRACE_DEBUG
	*rrd = rrp;
	#else
	mem_read(OMAP4430_ETB_RRD, rrd);
	#endif

	return 0;
}
Ejemplo n.º 26
0
void invoke_consensus_req(node *cur, 
    call type, data, data_size) {
  vs;

  // Local preparation.
  spin_lock();
  vs = idx++;
  spin_unlock();
  call_entry *entry = build_entry(cur,vs,data,data_size);
  mem_write(cur_log_offset, entry); 
  store_entry(entry);

  // RDMA write.
  for (i = 0; i < group_size; i++) {
    RDMA_write(i, remote_log_offset[i], entry);
  }
  
  // Wait for quorum.
recheck:
  for (i = 0; i < ; i++) {
    bitmap += ack[i].reply;
  }
  if (reach_quorum()) {
    process_req();
  } else
    goto recheck;
}
Ejemplo n.º 27
0
static int opencl_abi_si_mem_copy_impl(X86Context *ctx)
{
	struct x86_regs_t *regs = ctx->regs;

	unsigned int dest_ptr;
	unsigned int src_ptr;
	unsigned int size;

	void *buf;

	/* Arguments */
	dest_ptr = regs->ecx;
	src_ptr = regs->edx;
	size = regs->esi;
	opencl_debug("\tdest_ptr = 0x%x, src_ptr = 0x%x, size = %d bytes\n",
			dest_ptr, src_ptr, size);

	/* Check memory range */
	if (src_ptr + size > si_emu->video_mem_top ||
			dest_ptr + size > si_emu->video_mem_top)
		fatal("%s: accessing device memory not allocated",
				__FUNCTION__);

	/* Write memory from host to device */
	buf = xmalloc(size);
	mem_read(si_emu->video_mem, src_ptr, size, buf);
	mem_write(si_emu->video_mem, dest_ptr, size, buf);
	free(buf);

	/* Return */
	return 0;
}
Ejemplo n.º 28
0
static int opencl_abi_si_mem_read_impl(X86Context *ctx)
{
	struct x86_regs_t *regs = ctx->regs;
	struct mem_t *mem = ctx->mem;

	unsigned int host_ptr;
	unsigned int device_ptr;
	unsigned int size;

	void *buf;

	/* Arguments */
	host_ptr = regs->ecx;
	device_ptr = regs->edx;
	size = regs->esi;
	opencl_debug("\thost_ptr = 0x%x, device_ptr = 0x%x, size = %d bytes\n",
			host_ptr, device_ptr, size);

	/* Check memory range */
	if (device_ptr + size > si_emu->video_mem_top)
		fatal("%s: accessing device memory not allocated",
				__FUNCTION__);

	/* Read memory from device to host */
	buf = xmalloc(size);
	mem_read(si_emu->video_mem, device_ptr, size, buf);
	mem_write(mem, host_ptr, size, buf);
	free(buf);

	/* Return */
	return 0;
}
Ejemplo n.º 29
0
static int opencl_abi_init_impl(X86Context *ctx)
{
	struct x86_regs_t *regs = ctx->regs;
	struct mem_t *mem = ctx->mem;

	unsigned int version_ptr;
	struct opencl_version_t version;

	/* Arguments */
	version_ptr = regs->ecx;
	opencl_debug("\tversion_ptr=0x%x\n", version_ptr);

	/* Return version */
	assert(sizeof(struct opencl_version_t) == 8);
	version.major = OPENCL_VERSION_MAJOR;
	version.minor = OPENCL_VERSION_MINOR;
	mem_write(mem, version_ptr, sizeof version, &version);
	opencl_debug("\tMulti2Sim OpenCL implementation in host: v. %d.%d.\n",
		OPENCL_VERSION_MAJOR, OPENCL_VERSION_MINOR);
	opencl_debug("\tMulti2Sim OpenCL Runtime in guest: v. %d.%d.\n",
		version.major, version.minor);

	/* Return success */
	return 0;
}
Ejemplo n.º 30
0
static int mem_puts(BIO *bp, const char *str)
{
    int n, ret;

    n = strlen(str);
    ret = mem_write(bp, str, n);
    /* memory semantics is that it will always work */
    return (ret);
}