Ejemplo n.º 1
0
Archivo: irq.c Proyecto: 4pao/openwrt
void __init arch_init_irq(void)
{
	mips_cpu_irq_init();
	ramips_intc_irq_init(RT3883_INTC_BASE, RT3883_CPU_IRQ_INTC,
			     RT3883_INTC_IRQ_BASE);
	cp0_perfcount_irq = RT3883_INTC_IRQ_PERFC;
}
Ejemplo n.º 2
0
void __init arch_init_irq(void)
{
	/* IRQ 0 - 7 are for MIPS common irq_cpu controller */
	mips_cpu_irq_init();

	gt64120_init_pic();
}
Ejemplo n.º 3
0
Archivo: irq.c Proyecto: 1800alex/linux
void __init arch_init_irq(void)
{
#ifdef CONFIG_BCM47XX_BCMA
	if (bcm47xx_bus_type == BCM47XX_BUS_TYPE_BCMA) {
		bcma_write32(bcm47xx_bus.bcma.bus.drv_mips.core,
			     BCMA_MIPS_MIPS74K_INTMASK(5), 1 << 31);
		/*
		 * the kernel reads the timer irq from some register and thinks
		 * it's #5, but we offset it by 2 and route to #7
		 */
		cp0_compare_irq = 7;
	}
#endif
	mips_cpu_irq_init();

	if (cpu_has_vint) {
		pr_info("Setting up vectored interrupts\n");
		set_vi_handler(2, bcm47xx_hw2_irqdispatch);
		set_vi_handler(3, bcm47xx_hw3_irqdispatch);
		set_vi_handler(4, bcm47xx_hw4_irqdispatch);
		set_vi_handler(5, bcm47xx_hw5_irqdispatch);
		set_vi_handler(6, bcm47xx_hw6_irqdispatch);
		set_vi_handler(7, bcm47xx_hw7_irqdispatch);
	}
}
Ejemplo n.º 4
0
void __init arch_init_irq(void)
{
	int i;

	if (IS_LASAT_200()) {
		lasat_int_status = (void *)LASAT_INT_STATUS_REG_200;
		lasat_int_mask = (void *)LASAT_INT_MASK_REG_200;
		lasat_int_mask_shift = LASATINT_MASK_SHIFT_200;
		get_int_status = get_int_status_200;
		*lasat_int_mask &= 0xffff;
	} else {
		lasat_int_status = (void *)LASAT_INT_STATUS_REG_100;
		lasat_int_mask = (void *)LASAT_INT_MASK_REG_100;
		lasat_int_mask_shift = LASATINT_MASK_SHIFT_100;
		get_int_status = get_int_status_100;
		*lasat_int_mask = 0;
	}

	mips_cpu_irq_init();

	for (i = LASAT_IRQ_BASE; i <= LASAT_IRQ_END; i++)
		irq_set_chip_and_handler(i, &lasat_irq_type, handle_level_irq);

	setup_irq(LASAT_CASCADE_IRQ, &cascade);
}
Ejemplo n.º 5
0
void __init tx4927_irq_init(void)
{
	mips_cpu_irq_init();
	txx9_irq_init(TX4927_IRC_REG & 0xfffffffffULL);
	set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4927_IRC_INT,
				handle_simple_irq);
}
Ejemplo n.º 6
0
void __init arch_init_irq(void)
{
	int i;

	bcm63xx_init_irq();
	mips_cpu_irq_init();
	for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i)
		irq_set_chip_and_handler(i, &bcm63xx_internal_irq_chip,
					 handle_level_irq);

	for (i = IRQ_EXTERNAL_BASE; i < IRQ_EXTERNAL_BASE + ext_irq_count; ++i)
		irq_set_chip_and_handler(i, &bcm63xx_external_irq_chip,
					 handle_edge_irq);

	if (!is_ext_irq_cascaded) {
		for (i = 3; i < 3 + ext_irq_count; ++i)
			setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
	}

	setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
#ifdef CONFIG_SMP
	if (is_ext_irq_cascaded) {
		setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
		bcm63xx_internal_irq_chip.irq_set_affinity =
			bcm63xx_internal_set_affinity;

		cpumask_clear(irq_default_affinity);
		cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
	}
#endif
}
Ejemplo n.º 7
0
void __init arch_init_irq(void)
{
	mips_cpu_irq_init(MIPSCPU_INT_BASE);

	/* Now safe to set the exception vector. */
	set_except_vector(0, mipsIRQ);
}
Ejemplo n.º 8
0
void __init arch_init_irq(void)
{
	unsigned int irq;

	/*                                  */
	mips_cpu_irq_init();

	/*                                 */
	for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
		pnx833x_hard_disable_pic_irq(irq);
		irq_set_chip_and_handler(irq, &pnx833x_pic_irq_type,
					 handle_simple_irq);
	}

	for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
		irq_set_chip_and_handler(irq, &pnx833x_gpio_irq_type,
					 handle_simple_irq);

	/*                                        */
	PNX833X_PIC_INT_PRIORITY = 0;

	/*                            */
	pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT);

	/*                          */
	if (cpu_has_vint)
		set_vi_handler(4, pic_dispatch);

	write_c0_status(read_c0_status() | IE_IRQ2);
}
Ejemplo n.º 9
0
void __init arch_init_irq(void)
{
	/* hardware initialization */
	nile4_irq_setup();
	m1543_irq_setup();

	/* controller setup */
	init_i8259_irqs();
	vrc5476_irq_init(VRC5476_IRQ_BASE);
	mips_cpu_irq_init(CPU_IRQ_BASE);

	/* setup cascade interrupts */
	setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade);
	setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade);

	/* setup error interrupts for debugging */
	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error);
	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error);
	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error);
	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error);
	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error);
	setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error);

	/* setup the grandpa intr vector */
	set_except_vector(0, ddb5476_handle_int);
}
Ejemplo n.º 10
0
void __init arch_init_irq(void)
{
	int i;

	if (!cpu_has_veic) {
		mips_cpu_irq_init();

		if (cpu_has_vint) {
			/* install generic handler */
			for (i = 0; i < 8; i++)
				set_vi_handler(i, plat_irq_dispatch);
		}
	}

	sead3_config_reg = (unsigned long)ioremap_nocache(SEAD_CONFIG_BASE, SEAD_CONFIG_SIZE);
	gic_present = (REG32(sead3_config_reg) & SEAD_CONFIG_GIC_PRESENT_MSK) >>
			SEAD_CONFIG_GIC_PRESENT_SHF;
	printk("GIC: %spresent\n", (gic_present) ? "" : "not ");
	printk("EIC: %s\n", (current_cpu_data.options & MIPS_CPU_VEIC) ? "on" : "off");

	if (gic_present) {
		gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
				ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);
	}
}
Ejemplo n.º 11
0
void __init arch_init_irq(void)
{
	unsigned int irq;

	/* setup standard internal cpu irqs */
	mips_cpu_irq_init();

	/* Set IRQ information in irq_desc */
	for (irq = PNX833X_PIC_IRQ_BASE; irq < (PNX833X_PIC_IRQ_BASE + PNX833X_PIC_NUM_IRQ); irq++) {
		pnx833x_hard_disable_pic_irq(irq);
		irq_set_chip_and_handler(irq, &pnx833x_pic_irq_type,
					 handle_simple_irq);
	}

	for (irq = PNX833X_GPIO_IRQ_BASE; irq < (PNX833X_GPIO_IRQ_BASE + PNX833X_GPIO_NUM_IRQ); irq++)
		irq_set_chip_and_handler(irq, &pnx833x_gpio_irq_type,
					 handle_simple_irq);

	/* Set PIC priority limiter register to 0 */
	PNX833X_PIC_INT_PRIORITY = 0;

	/* Setup GPIO IRQ dispatching */
	pnx833x_startup_pic_irq(PNX833X_PIC_GPIO_INT);

	/* Enable PIC IRQs (HWIRQ2) */
	if (cpu_has_vint)
		set_vi_handler(4, pic_dispatch);

	write_c0_status(read_c0_status() | IE_IRQ2);
}
Ejemplo n.º 12
0
void __init arch_init_irq(void)
{
    struct irq_chip_generic *gc;
    struct irq_chip_type *ct;

    mips_cpu_irq_init();

    jz_intc_base = ioremap(JZ4740_INTC_BASE_ADDR, 0x14);

    /* Mask all irqs */
    writel(0xffffffff, jz_intc_base + JZ_REG_INTC_SET_MASK);

    gc = irq_alloc_generic_chip("INTC", 1, JZ4740_IRQ_BASE, jz_intc_base,
                                handle_level_irq);

    gc->wake_enabled = IRQ_MSK(32);

    ct = gc->chip_types;
    ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;
    ct->regs.disable = JZ_REG_INTC_SET_MASK;
    ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
    ct->chip.irq_mask = irq_gc_mask_disable_reg;
    ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;
    ct->chip.irq_set_wake = irq_gc_set_wake;
    ct->chip.irq_suspend = jz4740_irq_suspend;
    ct->chip.irq_resume = jz4740_irq_resume;

    irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, IRQ_NOPROBE | IRQ_LEVEL);

    setup_irq(2, &jz4740_cascade_action);
}
void rs780e_init_irq(void)
{

	/* Route the HT interrupt to Core0 INT1 */
	INT_router_regs_HT1_int0 = 0x20 | (1 << phy_core_id[0]);
	INT_router_regs_HT1_int1 = 0x20 | (1 << phy_core_id[0]);
	INT_router_regs_HT1_int2 = 0x20 | (1 << phy_core_id[0]);
	INT_router_regs_HT1_int3 = 0x20 | (1 << phy_core_id[0]);
	INT_router_regs_HT1_int4 = 0x20 | (1 << phy_core_id[0]);
	INT_router_regs_HT1_int5 = 0x20 | (1 << phy_core_id[0]);
	INT_router_regs_HT1_int6 = 0x20 | (1 << phy_core_id[0]);
	INT_router_regs_HT1_int7 = 0x20 | (1 << phy_core_id[0]);
	/* Enable the all HT interrupt */
	HT_irq_enable_reg0 = 0x0000ffff;
	HT_irq_enable_reg1 = 0x00000000;
	HT_irq_enable_reg2 = 0x00000000;
	HT_irq_enable_reg3 = 0x00000000;
	HT_irq_enable_reg4 = 0x00000000;
	HT_irq_enable_reg5 = 0x00000000;
	HT_irq_enable_reg6 = 0x00000000;
	HT_irq_enable_reg7 = 0x00000000;

	/* Enable the IO interrupt controller */ 
	IO_control_regs_Intenset = IO_control_regs_Inten | (0xffff << 16);
	prom_printf("the new IO inten is %x\n", IO_control_regs_Inten);

	/* Sets the first-level interrupt dispatcher. */
	mips_cpu_irq_init();	

#ifdef CONFIG_I8259
	init_i8259_irqs();
#endif
	set_c0_status(STATUSF_IP6);
	mach_ip3 = dispatch_ht_irq;
}
Ejemplo n.º 14
0
Archivo: irq.c Proyecto: 03199618/linux
void __init arch_init_irq(void)
{
	if (soc_is_ar71xx()) {
		ath79_ip2_handler = ar71xx_ip2_handler;
		ath79_ip3_handler = ar71xx_ip3_handler;
	} else if (soc_is_ar724x()) {
		ath79_ip2_handler = ar724x_ip2_handler;
		ath79_ip3_handler = ar724x_ip3_handler;
	} else if (soc_is_ar913x()) {
		ath79_ip2_handler = ar913x_ip2_handler;
		ath79_ip3_handler = ar913x_ip3_handler;
	} else if (soc_is_ar933x()) {
		ath79_ip2_handler = ar933x_ip2_handler;
		ath79_ip3_handler = ar933x_ip3_handler;
	} else if (soc_is_ar934x()) {
		ath79_ip2_handler = ath79_default_ip2_handler;
		ath79_ip3_handler = ar934x_ip3_handler;
	} else if (soc_is_qca955x()) {
		ath79_ip2_handler = ath79_default_ip2_handler;
		ath79_ip3_handler = ath79_default_ip3_handler;
	} else {
		BUG();
	}

	cp0_perfcount_irq = ATH79_MISC_IRQ(5);
	mips_cpu_irq_init();
	ath79_misc_irq_init();

	if (soc_is_ar934x())
		ar934x_ip2_irq_init();
	else if (soc_is_qca955x())
		qca955x_irq_init();
}
Ejemplo n.º 15
0
void __init arch_init_irq(void)
{
	extern void hpIRQ(void);
	extern void mips_cpu_irq_init(u32 base);

	mips_cpu_irq_init(0);
	set_except_vector(0, hpIRQ);
}
Ejemplo n.º 16
0
void __init arch_init_irq(void)
{
	mips_hpt_frequency = QEMU_C0_COUNTER_CLOCK;		/* 100MHz */

	mips_cpu_irq_init();
	init_i8259_irqs();
	set_c0_status(0x400);
}
Ejemplo n.º 17
0
void __init arch_init_irq(void)
{
	mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
	init_vr41xx_icu_irq();
	init_vr41xx_giuint_irq();

	set_except_vector(0, vr41xx_handle_interrupt);
}
Ejemplo n.º 18
0
/*
 * Initialize the next level interrupt handler
 */
void __init arch_init_irq(void)
{
	clear_c0_status(ST0_IM);

	mips_cpu_irq_init();
	rm7k_cpu_irq_init();
	rm9k_cpu_irq_init();
}
Ejemplo n.º 19
0
void __init arch_init_irq(void)
{
	mips_cpu_irq_init();
	gt641xx_irq_init();
	init_i8259_irqs();

	setup_irq(GT641XX_CASCADE_IRQ, &cascade);
	setup_irq(I8259_CASCADE_IRQ, &cascade);
}
Ejemplo n.º 20
0
void __init arch_init_irq(void)
{
	int i;
	unsigned int gic_rev;

	mips_cpu_irq_init();

	if (cpu_has_vint)
		set_vi_handler(cp0_compare_irq, mips_timer_dispatch);

	if (gcmp_present) {
		GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK;
		gic_present = 1;
	}

	if (gic_present) {
#if defined (CONFIG_MIPS_GIC_IPI)
		gic_call_int_base = GIC_IPI_CALL_VPE0;
		gic_resched_int_base = GIC_IPI_RESCHED_VPE0;
		fill_ipi_map();
#endif
		gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map,
				ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE);

		GICREAD(GIC_REG(SHARED, GIC_SH_REVISIONID), gic_rev);
		printk("MIPS GIC RevID: %d.%d\n", (gic_rev >> 8) & 0xff, gic_rev & 0xff);

		if (cpu_has_vint) {
			pr_info("Setting up vectored interrupts\n");
			set_vi_handler(2 + GIC_CPU_INT0, gic_irq_dispatch);	// CPU
#if defined (CONFIG_MIPS_GIC_IPI)
			set_vi_handler(2 + GIC_CPU_INT1, gic_irq_dispatch);	// IPI resched
			set_vi_handler(2 + GIC_CPU_INT2, gic_irq_dispatch);	// IPI call
#endif
			set_vi_handler(2 + GIC_CPU_INT3, gic_irq_dispatch);	// FE
			set_vi_handler(2 + GIC_CPU_INT4, gic_irq_dispatch);	// PCIe
		}

#if defined (CONFIG_MIPS_GIC_IPI)
		set_c0_status(STATUSF_IP7 | STATUSF_IP6 | STATUSF_IP5 | STATUSF_IP2 |
			      STATUSF_IP4 | STATUSF_IP3);
		
		/* setup ipi interrupts */
		for (i = 0; i < nr_cpu_ids; i++) {
			arch_init_ipiirq(MIPS_GIC_IRQ_BASE + GIC_RESCHED_INT(i), &irq_resched);
			arch_init_ipiirq(MIPS_GIC_IRQ_BASE + GIC_CALL_INT(i), &irq_call);
		}
#else
		set_c0_status(STATUSF_IP7 | STATUSF_IP6 | STATUSF_IP5 | STATUSF_IP2);
#endif
		/* set hardware irq, mapped to GIC shared (skip 0, 1, 2, 5, 7) */
		for (i = 3; i <= 31; i++) {
			if (i != 5 && i != 7)
				irq_set_handler(MIPS_GIC_IRQ_BASE + i, handle_level_irq);
		}
		
	} else {
Ejemplo n.º 21
0
void __init arch_init_irq(void)
{
	/* by default, we disable all interrupts and route all vrc5477
	 * interrupts to pin 0 (irq 2) */
	ddb_out32(DDB_INTCTRL0, 0);
	ddb_out32(DDB_INTCTRL1, 0);
	ddb_out32(DDB_INTCTRL2, 0);
	ddb_out32(DDB_INTCTRL3, 0);

	clear_c0_status(0xff00);
	set_c0_status(0x0400);

	/* setup PCI interrupt attributes */
	set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
	if (mips_machtype == MACH_NEC_ROCKHOPPERII)
		set_pci_int_attr(PCI0, INTC, ACTIVE_HIGH, LEVEL_SENSE);
	else
		set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);

	set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);

	/*
	 * for debugging purpose, we enable several error interrupts
	 * and route them to pin 1. (IP3)
	 */
	/* cpu parity check - 0 */
	ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
	/* cpu no-target decode - 1 */
	ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
	/* local bus read time-out - 7 */
	ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
	/* PCI SERR# - 14 */
	ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
	/* PCI internal error - 15 */
	ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
	/* IOPCI SERR# - 30 */
	ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
	/* IOPCI internal error - 31 */
	ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);

	/* init all controllers */
	init_i8259_irqs();
	mips_cpu_irq_init();
	vrc5477_irq_init(VRC5477_IRQ_BASE);


	/* setup cascade interrupts */
	setup_irq(VRC5477_IRQ_BASE + VRC5477_I8259_CASCADE, &irq_cascade);
	setup_irq(CPU_IRQ_BASE + CPU_VRC5477_CASCADE, &irq_cascade);
}
Ejemplo n.º 22
0
void __init arch_init_irq(void)
{
	mips_cpu_irq_init();
	ip27_hub_irq_init();

	irq_set_percpu_devid(IP27_HUB_PEND0_IRQ);
	irq_set_chained_handler(IP27_HUB_PEND0_IRQ, ip27_do_irq_mask0);
	irq_set_percpu_devid(IP27_HUB_PEND1_IRQ);
	irq_set_chained_handler(IP27_HUB_PEND1_IRQ, ip27_do_irq_mask1);
}
Ejemplo n.º 23
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Archivo: board.c Proyecto: janfj/dd-wrt
void __init
arch_init_irq(void)
{
	clear_c0_status(ST0_IM);
	mips_cpu_irq_init();

	/* Initialize interrupt controllers */
	ar5312_irq_init();
	ar2315_irq_init();
}
Ejemplo n.º 24
0
/*
 * Initialize the interrupt handler
 */
void __init arch_init_irq(void)
{
	mips_cpu_irq_init();
	rm7k_cpu_irq_init();
	rm9k_cpu_irq_init();

#ifdef CONFIG_KGDB
	excite_kgdb_init();
#endif
}
Ejemplo n.º 25
0
void
ddb5477_irq_setup(void)
{
	db_run(printk("ddb5477_irq_setup invoked.\n"));

	/* by default, we disable all interrupts and route all vrc5477 
	 * interrupts to pin 0 (irq 2) */
	ddb_out32(DDB_INTCTRL0, 0);
	ddb_out32(DDB_INTCTRL1, 0);
	ddb_out32(DDB_INTCTRL2, 0);
	ddb_out32(DDB_INTCTRL3, 0);

	clear_cp0_status(0xff00);
	set_cp0_status(0x0400);

	/* setup PCI interrupt attributes */
	set_pci_int_attr(PCI0, INTA, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI0, INTB, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI0, INTC, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI0, INTD, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI0, INTE, ACTIVE_LOW, LEVEL_SENSE);

	set_pci_int_attr(PCI1, INTA, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI1, INTB, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI1, INTC, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI1, INTD, ACTIVE_LOW, LEVEL_SENSE);
	set_pci_int_attr(PCI1, INTE, ACTIVE_LOW, LEVEL_SENSE);

	/* 
	 * for debugging purpose, we enable several error interrupts
	 * and route them to pin 1. (IP3) 
	 */
	/* cpu parity check - 0 */
	ll_vrc5477_irq_route(0, 1); ll_vrc5477_irq_enable(0);
	/* cpu no-target decode - 1 */
	ll_vrc5477_irq_route(1, 1); ll_vrc5477_irq_enable(1);
	/* local bus read time-out - 7 */
	ll_vrc5477_irq_route(7, 1); ll_vrc5477_irq_enable(7);
	/* PCI SERR# - 14 */
	ll_vrc5477_irq_route(14, 1); ll_vrc5477_irq_enable(14);
	/* PCI internal error - 15 */
	ll_vrc5477_irq_route(15, 1); ll_vrc5477_irq_enable(15);
	/* IOPCI SERR# - 30 */
	ll_vrc5477_irq_route(30, 1); ll_vrc5477_irq_enable(30);
	/* IOPCI internal error - 31 */
	ll_vrc5477_irq_route(31, 1); ll_vrc5477_irq_enable(31);

	/* init all controllers */
	mips_cpu_irq_init(0);
	vrc5477_irq_init(8);

	/* hook up the first-level interrupt handler */
	set_except_vector(0, ddb5477_handle_int);
}
Ejemplo n.º 26
0
void __init init_IRQ(void)
{
	memset(irq_desc, 0, sizeof(irq_desc));

	init_generic_irq();
	mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
	init_vr41xx_icu_irq();
	init_vr41xx_giuint_irq();

	set_except_vector(0, vr41xx_handle_interrupt);
}
Ejemplo n.º 27
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void __init sni_pcimt_irq_init(void)
{
	int i;

	*(volatile u8 *) PCIMT_IRQSEL = IT_ETH | IT_EISA;
	mips_cpu_irq_init();
	/* Actually we've got more interrupts to handle ...  */
	for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_SCSI; i++)
		set_irq_chip(i, &pcimt_irq_type);
	sni_hwint = sni_pcimt_hwint;
	change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ3);
}
Ejemplo n.º 28
0
void __init arch_init_irq(void)
{
	int i;

	/*
	 * Initialize interrupt controllers to a safe state.
	 */
	au_writel(0xffffffff, IC0_CFG0CLR);
	au_writel(0xffffffff, IC0_CFG1CLR);
	au_writel(0xffffffff, IC0_CFG2CLR);
	au_writel(0xffffffff, IC0_MASKCLR);
	au_writel(0xffffffff, IC0_ASSIGNSET);
	au_writel(0xffffffff, IC0_WAKECLR);
	au_writel(0xffffffff, IC0_SRCSET);
	au_writel(0xffffffff, IC0_FALLINGCLR);
	au_writel(0xffffffff, IC0_RISINGCLR);
	au_writel(0x00000000, IC0_TESTBIT);

	au_writel(0xffffffff, IC1_CFG0CLR);
	au_writel(0xffffffff, IC1_CFG1CLR);
	au_writel(0xffffffff, IC1_CFG2CLR);
	au_writel(0xffffffff, IC1_MASKCLR);
	au_writel(0xffffffff, IC1_ASSIGNSET);
	au_writel(0xffffffff, IC1_WAKECLR);
	au_writel(0xffffffff, IC1_SRCSET);
	au_writel(0xffffffff, IC1_FALLINGCLR);
	au_writel(0xffffffff, IC1_RISINGCLR);
	au_writel(0x00000000, IC1_TESTBIT);

	mips_cpu_irq_init();

	/* register all 64 possible IC0+IC1 irq sources as type "none".
	 * Use set_irq_type() to set edge/level behaviour at runtime.
	 */
	for (i = AU1000_INTC0_INT_BASE;
	     (i < AU1000_INTC0_INT_BASE + 32); i++)
		au1x_ic_settype(i, IRQ_TYPE_NONE);

	for (i = AU1000_INTC1_INT_BASE;
	     (i < AU1000_INTC1_INT_BASE + 32); i++)
		au1x_ic_settype(i, IRQ_TYPE_NONE);

	/*
	 * Initialize IC0, which is fixed per processor.
	 */
	au1xxx_setup_irqmap(au1xxx_ic0_map, ARRAY_SIZE(au1xxx_ic0_map));

	/* Boards can register additional (GPIO-based) IRQs.
	*/
	board_init_irq();

	set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
}
Ejemplo n.º 29
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void __init arch_init_irq(void)
{
	int i;

	set_except_vector(0, vr4181_handle_irq);

	/* init CPU irqs */
	mips_cpu_irq_init(VR4181_CPU_IRQ_BASE);

	/* init sys irqs */
	sys_irq_base = VR4181_SYS_IRQ_BASE;
	for (i=sys_irq_base; i < sys_irq_base + VR4181_NUM_SYS_IRQ; i++) {
		irq_desc[i].status = IRQ_DISABLED;
		irq_desc[i].action = NULL;
		irq_desc[i].depth = 1;
		irq_desc[i].handler = &sys_irq_controller;
	}

	/* init gpio irqs */
	gpio_irq_base = VR4181_GPIO_IRQ_BASE;
	for (i=gpio_irq_base; i < gpio_irq_base + VR4181_NUM_GPIO_IRQ; i++) {
		irq_desc[i].status = IRQ_DISABLED;
		irq_desc[i].action = NULL;
		irq_desc[i].depth = 1;
		irq_desc[i].handler = &gpio_irq_controller;
	}

	/* Default all ICU IRQs to off ... */
	*VR4181_MSYSINT1REG = 0;
	*VR4181_MSYSINT2REG = 0;

	/* We initialize the level 2 ICU registers to all bits disabled. */
	*VR4181_MPIUINTREG = 0;
	*VR4181_MAIUINTREG = 0;
	*VR4181_MKIUINTREG = 0;

	/* disable all GPIO intrs */
	*VR4181_GPINTMSK = 0xffff;

	/* vector handler.  What these do is register the IRQ as non-sharable */
	setup_irq(VR4181_IRQ_INT0, &cascade);
	setup_irq(VR4181_IRQ_GIU, &cascade);

	/*
	 * RTC interrupts are interesting.  They have two destinations.
	 * One is at sys irq controller, and the other is at CPU IP3 and IP4.
	 * RTC timer is used as system timer.
	 * We enable them here, but timer routine will register later
	 * with CPU IP3/IP4.
	 */
	setup_irq(VR4181_IRQ_RTCL1, &reserved);
	setup_irq(VR4181_IRQ_RTCL2, &reserved);
}
Ejemplo n.º 30
0
Archivo: irq.c Proyecto: 1x23/unifi-gpl
void __init arch_init_irq(void)
{
	mips_cpu_irq_init();

	ar71xx_misc_irq_init();

#ifdef CONFIG_PCI
	ar71xx_pci_irq_init();
#endif

	ar71xx_gpio_irq_init();
}