/**
* dt_init_idle_driver() - Parse the DT idle states and initialize the
* idle driver states array
* @drv: Pointer to CPU idle driver to be initialized
* @matches: Array of of_device_id match structures to search in for
* compatible idle state nodes. The data pointer for each valid
* struct of_device_id entry in the matches array must point to
* a function with the following signature, that corresponds to
* the CPUidle state enter function signature:
*
* int (*)(struct cpuidle_device *dev,
* struct cpuidle_driver *drv,
* int index);
*
* @start_idx: First idle state index to be initialized
*
* If DT idle states are detected and are valid the state count and states
* array entries in the cpuidle driver are initialized accordingly starting
* from index start_idx.
*
* Return: number of valid DT idle states parsed, <0 on failure
*/
int dt_init_idle_driver(struct cpuidle_driver *drv,
const struct of_device_id *matches,
unsigned int start_idx)
{
struct cpuidle_state *idle_state;
struct device_node *state_node, *cpu_node;
int i, err = 0;
const cpumask_t *cpumask;
unsigned int state_idx = start_idx;
if (state_idx >= CPUIDLE_STATE_MAX)
return -EINVAL;
/*
* We get the idle states for the first logical cpu in the
* driver mask (or cpu_possible_mask if the driver cpumask is not set)
* and we check through idle_state_valid() if they are uniform
* across CPUs, otherwise we hit a firmware misconfiguration.
*/
cpumask = drv->cpumask ? : cpu_possible_mask;
cpu_node = of_cpu_device_node_get(cpumask_first(cpumask));
for (i = 0; ; i++) {
state_node = of_parse_phandle(cpu_node, "cpu-idle-states", i);
if (!state_node)
break;
if (!of_device_is_available(state_node)) {
of_node_put(state_node);
continue;
}
if (!idle_state_valid(state_node, i, cpumask)) {
pr_warn("%pOF idle state not valid, bailing out\n",
state_node);
err = -EINVAL;
break;
}
if (state_idx == CPUIDLE_STATE_MAX) {
pr_warn("State index reached static CPU idle driver states array size\n");
break;
}
idle_state = &drv->states[state_idx++];
err = init_state_node(idle_state, matches, state_node);
if (err) {
pr_err("Parsing idle state node %pOF failed with err %d\n",
state_node, err);
err = -EINVAL;
break;
}
of_node_put(state_node);
}
of_node_put(state_node);
of_node_put(cpu_node);
if (err)
return err;
/*
* Update the driver state count only if some valid DT idle states
* were detected
*/
if (i)
drv->state_count = state_idx;
/*
* Return the number of present and valid DT idle states, which can
* also be 0 on platforms with missing DT idle states or legacy DT
* configuration predating the DT idle states bindings.
*/
return i;
}
static int esd_fg_init(struct lcd_info *lcd)
{
struct device *dev;
struct device_node *np;
struct platform_device *pdev;
enum of_gpio_flags flags;
unsigned int irqf_type = IRQF_TRIGGER_RISING;
unsigned int active_level = 1;
int ret = 0;
lcd->esd_fg_gpio = -EINVAL;
if (!lcd->connected)
return ret;
np = of_parse_phandle(lcd->dsim->dev->of_node, "lcd_info", 0);
pdev = of_platform_device_create(np, NULL, lcd->dsim->dev);
dev = &pdev->dev;
lcd->esd_fg_gpio = of_get_named_gpio_flags(np, "gpio-tcon-int", 0, &flags);
if (lcd->esd_fg_gpio < 0) {
dev_err(&lcd->ld->dev, "failed to get proper gpio number\n");
return -EINVAL;
}
if (flags & OF_GPIO_ACTIVE_LOW) {
irqf_type = IRQF_TRIGGER_FALLING;
active_level = 0;
}
if (gpio_get_value(lcd->esd_fg_gpio) == active_level) {
dev_err(&lcd->ld->dev, "%s: gpio(%d) is already %s\n",
__func__, lcd->esd_fg_gpio, active_level ? "high" : "low");
return ret;
}
lcd->esd_fg_pins = devm_pinctrl_get(dev);
if (IS_ERR(lcd->esd_fg_pins)) {
dev_err(&lcd->ld->dev, "failed to get pinctrl\n");
return -EINVAL;
}
lcd->esd_fg_pins_state[0] = pinctrl_lookup_state(lcd->esd_fg_pins, "errfg_off");
if (IS_ERR(lcd->esd_fg_pins_state[0])) {
dev_err(&lcd->ld->dev, "failed to get proper errfg off pinctrl\n");
return -EINVAL;
}
lcd->esd_fg_pins_state[1] = pinctrl_lookup_state(lcd->esd_fg_pins, "errfg_on");
if (IS_ERR(lcd->esd_fg_pins_state[1])) {
dev_err(&lcd->ld->dev, "failed to get proper errfg on pinctrl\n");
return -EINVAL;
}
lcd->esd_fg_irq = gpio_to_irq(lcd->esd_fg_gpio);
if (!lcd->esd_fg_irq) {
dev_err(&lcd->ld->dev, "failed to get proper irq number\n");
return -EINVAL;
}
spin_lock_init(&lcd->esd_fg_lock);
INIT_DELAYED_WORK(&lcd->esd_fg, esd_fg_work);
irq_set_status_flags(lcd->esd_fg_irq, IRQ_NOAUTOEN);
ret = request_irq(lcd->esd_fg_irq, esd_fg_isr, irqf_type, "esd_fg", lcd);
if (ret) {
dev_err(&lcd->ld->dev, "esd_fg irq request failed\n");
return ret;
}
esd_fg_enable(lcd, 1);
dev_info(&lcd->ld->dev, "%s: gpio(%d) is active %s(%d), %s edge\n",
__func__, lcd->esd_fg_gpio, active_level ? "high" : "low",
gpio_get_value(lcd->esd_fg_gpio),
(irqf_type == IRQF_TRIGGER_RISING) ? "rising" : "falling");
return ret;
}
static int ti_dma_xbar_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
const struct of_device_id *match;
struct device_node *dma_node;
struct ti_dma_xbar_data *xbar;
struct resource *res;
u32 safe_val;
void __iomem *iomem;
int i, ret;
if (!node)
return -ENODEV;
xbar = devm_kzalloc(&pdev->dev, sizeof(*xbar), GFP_KERNEL);
if (!xbar)
return -ENOMEM;
idr_init(&xbar->map_idr);
dma_node = of_parse_phandle(node, "dma-masters", 0);
if (!dma_node) {
dev_err(&pdev->dev, "Can't get DMA master node\n");
return -ENODEV;
}
match = of_match_node(ti_dma_master_match, dma_node);
if (!match) {
dev_err(&pdev->dev, "DMA master is not supported\n");
return -EINVAL;
}
if (of_property_read_u32(dma_node, "dma-requests",
&xbar->dma_requests)) {
dev_info(&pdev->dev,
"Missing XBAR output information, using %u.\n",
TI_XBAR_OUTPUTS);
xbar->dma_requests = TI_XBAR_OUTPUTS;
}
of_node_put(dma_node);
if (of_property_read_u32(node, "dma-requests", &xbar->xbar_requests)) {
dev_info(&pdev->dev,
"Missing XBAR input information, using %u.\n",
TI_XBAR_INPUTS);
xbar->xbar_requests = TI_XBAR_INPUTS;
}
if (!of_property_read_u32(node, "ti,dma-safe-map", &safe_val))
xbar->safe_val = (u16)safe_val;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
iomem = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(iomem))
return PTR_ERR(iomem);
xbar->iomem = iomem;
xbar->dmarouter.dev = &pdev->dev;
xbar->dmarouter.route_free = ti_dma_xbar_free;
xbar->dma_offset = (u32)match->data;
platform_set_drvdata(pdev, xbar);
/* Reset the crossbar */
for (i = 0; i < xbar->dma_requests; i++)
ti_dma_xbar_write(xbar->iomem, i, xbar->safe_val);
ret = of_dma_router_register(node, ti_dma_xbar_route_allocate,
&xbar->dmarouter);
if (ret) {
/* Restore the defaults for the crossbar */
for (i = 0; i < xbar->dma_requests; i++)
ti_dma_xbar_write(xbar->iomem, i, i);
}
return ret;
}
static int omap2430_probe(struct platform_device *pdev)
{
struct resource musb_resources[3];
struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
struct omap_musb_board_data *data;
struct platform_device *musb;
struct omap2430_glue *glue;
struct device_node *np = pdev->dev.of_node;
struct musb_hdrc_config *config;
struct device_node *control_node;
struct platform_device *control_pdev;
int ret = -ENOMEM, val;
if (!np)
return -ENODEV;
glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
if (!glue)
goto err0;
musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
if (!musb) {
dev_err(&pdev->dev, "failed to allocate musb device\n");
goto err0;
}
musb->dev.parent = &pdev->dev;
musb->dev.dma_mask = &omap2430_dmamask;
musb->dev.coherent_dma_mask = omap2430_dmamask;
glue->dev = &pdev->dev;
glue->musb = musb;
glue->status = MUSB_UNKNOWN;
glue->control_otghs = ERR_PTR(-ENODEV);
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
goto err2;
data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
if (!data)
goto err2;
config = devm_kzalloc(&pdev->dev, sizeof(*config), GFP_KERNEL);
if (!config)
goto err2;
of_property_read_u32(np, "mode", (u32 *)&pdata->mode);
of_property_read_u32(np, "interface-type",
(u32 *)&data->interface_type);
of_property_read_u32(np, "num-eps", (u32 *)&config->num_eps);
of_property_read_u32(np, "ram-bits", (u32 *)&config->ram_bits);
of_property_read_u32(np, "power", (u32 *)&pdata->power);
ret = of_property_read_u32(np, "multipoint", &val);
if (!ret && val)
config->multipoint = true;
pdata->board_data = data;
pdata->config = config;
control_node = of_parse_phandle(np, "ctrl-module", 0);
if (control_node) {
control_pdev = of_find_device_by_node(control_node);
if (!control_pdev) {
dev_err(&pdev->dev, "Failed to get control device\n");
ret = -EINVAL;
goto err2;
}
glue->control_otghs = &control_pdev->dev;
}
pdata->platform_ops = &omap2430_ops;
platform_set_drvdata(pdev, glue);
/*
* REVISIT if we ever have two instances of the wrapper, we will be
* in big trouble
*/
_glue = glue;
INIT_WORK(&glue->omap_musb_mailbox_work, omap_musb_mailbox_work);
memset(musb_resources, 0x00, sizeof(*musb_resources) *
ARRAY_SIZE(musb_resources));
musb_resources[0].name = pdev->resource[0].name;
musb_resources[0].start = pdev->resource[0].start;
musb_resources[0].end = pdev->resource[0].end;
musb_resources[0].flags = pdev->resource[0].flags;
musb_resources[1].name = pdev->resource[1].name;
musb_resources[1].start = pdev->resource[1].start;
musb_resources[1].end = pdev->resource[1].end;
musb_resources[1].flags = pdev->resource[1].flags;
musb_resources[2].name = pdev->resource[2].name;
musb_resources[2].start = pdev->resource[2].start;
musb_resources[2].end = pdev->resource[2].end;
musb_resources[2].flags = pdev->resource[2].flags;
ret = platform_device_add_resources(musb, musb_resources,
ARRAY_SIZE(musb_resources));
if (ret) {
dev_err(&pdev->dev, "failed to add resources\n");
goto err2;
}
ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
if (ret) {
dev_err(&pdev->dev, "failed to add platform_data\n");
goto err2;
}
pm_runtime_enable(glue->dev);
ret = platform_device_add(musb);
if (ret) {
dev_err(&pdev->dev, "failed to register musb device\n");
goto err3;
}
return 0;
err3:
pm_runtime_disable(glue->dev);
err2:
platform_device_put(musb);
err0:
return ret;
}
static int tpiu_parse_of_data(struct platform_device *pdev,
struct tpiu_drvdata *drvdata)
{
struct device_node *node = pdev->dev.of_node;
struct device_node *reg_node = NULL;
struct device *dev = &pdev->dev;
const __be32 *prop;
int i, len, gpio, ret;
uint32_t *seta_cfgs, *setb_cfgs;
struct pinctrl *pctrl;
reg_node = of_parse_phandle(node, "vdd-supply", 0);
if (reg_node) {
drvdata->reg = devm_regulator_get(dev, "vdd");
if (IS_ERR(drvdata->reg))
return PTR_ERR(drvdata->reg);
prop = of_get_property(node, "qcom,vdd-voltage-level", &len);
if (!prop || (len != (2 * sizeof(__be32)))) {
dev_err(dev, "sdc voltage levels not specified\n");
} else {
drvdata->reg_low = be32_to_cpup(&prop[0]);
drvdata->reg_high = be32_to_cpup(&prop[1]);
}
prop = of_get_property(node, "qcom,vdd-current-level", &len);
if (!prop || (len != (2 * sizeof(__be32)))) {
dev_err(dev, "sdc current levels not specified\n");
} else {
drvdata->reg_lpm = be32_to_cpup(&prop[0]);
drvdata->reg_hpm = be32_to_cpup(&prop[1]);
}
of_node_put(reg_node);
} else {
dev_err(dev, "sdc voltage supply not specified or available\n");
}
reg_node = of_parse_phandle(node, "vdd-io-supply", 0);
if (reg_node) {
drvdata->reg_io = devm_regulator_get(dev, "vdd-io");
if (IS_ERR(drvdata->reg_io))
return PTR_ERR(drvdata->reg_io);
prop = of_get_property(node, "qcom,vdd-io-voltage-level", &len);
if (!prop || (len != (2 * sizeof(__be32)))) {
dev_err(dev, "sdc io voltage levels not specified\n");
} else {
drvdata->reg_low_io = be32_to_cpup(&prop[0]);
drvdata->reg_high_io = be32_to_cpup(&prop[1]);
}
prop = of_get_property(node, "qcom,vdd-io-current-level", &len);
if (!prop || (len != (2 * sizeof(__be32)))) {
dev_err(dev, "sdc io current levels not specified\n");
} else {
drvdata->reg_lpm_io = be32_to_cpup(&prop[0]);
drvdata->reg_hpm_io = be32_to_cpup(&prop[1]);
}
of_node_put(reg_node);
} else {
dev_err(dev,
"sdc io voltage supply not specified or available\n");
}
drvdata->out_mode = TPIU_OUT_MODE_MICTOR;
drvdata->set = TPIU_SET_B;
pctrl = devm_pinctrl_get(dev);
if (!IS_ERR(pctrl)) {
drvdata->tpiu_pctrl = devm_kzalloc(dev,
sizeof(struct tpiu_pinctrl),
GFP_KERNEL);
if (!drvdata->tpiu_pctrl)
return -ENOMEM;
devm_pinctrl_put(pctrl);
goto out;
}
dev_err(dev, "Pinctrl failed, falling back to GPIO lib\n");
drvdata->seta_gpiocnt = of_gpio_named_count(node, "qcom,seta-gpios");
if (drvdata->seta_gpiocnt > 0) {
drvdata->seta_gpios = devm_kzalloc(dev,
sizeof(*drvdata->seta_gpios) *
drvdata->seta_gpiocnt, GFP_KERNEL);
if (!drvdata->seta_gpios)
return -ENOMEM;
for (i = 0; i < drvdata->seta_gpiocnt; i++) {
gpio = of_get_named_gpio(node, "qcom,seta-gpios", i);
if (!gpio_is_valid(gpio))
return gpio;
drvdata->seta_gpios[i] = gpio;
}
drvdata->seta_cfgs = devm_kzalloc(dev,
sizeof(*drvdata->seta_cfgs) *
drvdata->seta_gpiocnt, GFP_KERNEL);
if (!drvdata->seta_cfgs)
return -ENOMEM;
seta_cfgs = devm_kzalloc(dev, sizeof(*seta_cfgs) *
drvdata->seta_gpiocnt, GFP_KERNEL);
if (!seta_cfgs)
return -ENOMEM;
ret = of_property_read_u32_array(node, "qcom,seta-gpios-func",
(u32 *)seta_cfgs,
drvdata->seta_gpiocnt);
if (ret)
return ret;
for (i = 0; i < drvdata->seta_gpiocnt; i++)
drvdata->seta_cfgs[i].func = seta_cfgs[i];
ret = of_property_read_u32_array(node, "qcom,seta-gpios-drv",
(u32 *)seta_cfgs,
drvdata->seta_gpiocnt);
if (ret)
return ret;
for (i = 0; i < drvdata->seta_gpiocnt; i++)
drvdata->seta_cfgs[i].drv = seta_cfgs[i];
ret = of_property_read_u32_array(node, "qcom,seta-gpios-pull",
(u32 *)seta_cfgs,
drvdata->seta_gpiocnt);
if (ret)
return ret;
for (i = 0; i < drvdata->seta_gpiocnt; i++)
drvdata->seta_cfgs[i].pull = seta_cfgs[i];
ret = of_property_read_u32_array(node, "qcom,seta-gpios-dir",
(u32 *)seta_cfgs,
drvdata->seta_gpiocnt);
if (ret)
return ret;
for (i = 0; i < drvdata->seta_gpiocnt; i++)
drvdata->seta_cfgs[i].dir = seta_cfgs[i];
devm_kfree(dev, seta_cfgs);
} else {
dev_err(dev, "seta gpios not specified\n");
}
drvdata->setb_gpiocnt = of_gpio_named_count(node, "qcom,setb-gpios");
if (drvdata->setb_gpiocnt > 0) {
drvdata->setb_gpios = devm_kzalloc(dev,
sizeof(*drvdata->setb_gpios) *
drvdata->setb_gpiocnt, GFP_KERNEL);
if (!drvdata->setb_gpios)
return -ENOMEM;
for (i = 0; i < drvdata->setb_gpiocnt; i++) {
gpio = of_get_named_gpio(node, "qcom,setb-gpios", i);
if (!gpio_is_valid(gpio))
return gpio;
drvdata->setb_gpios[i] = gpio;
}
drvdata->setb_cfgs = devm_kzalloc(dev,
sizeof(*drvdata->setb_cfgs) *
drvdata->setb_gpiocnt, GFP_KERNEL);
if (!drvdata->setb_cfgs)
return -ENOMEM;
setb_cfgs = devm_kzalloc(dev, sizeof(*setb_cfgs) *
drvdata->setb_gpiocnt, GFP_KERNEL);
if (!setb_cfgs)
return -ENOMEM;
ret = of_property_read_u32_array(node, "qcom,setb-gpios-func",
(u32 *)setb_cfgs,
drvdata->setb_gpiocnt);
if (ret)
return ret;
for (i = 0; i < drvdata->setb_gpiocnt; i++)
drvdata->setb_cfgs[i].func = setb_cfgs[i];
ret = of_property_read_u32_array(node, "qcom,setb-gpios-drv",
(u32 *)setb_cfgs,
drvdata->setb_gpiocnt);
if (ret)
return ret;
for (i = 0; i < drvdata->setb_gpiocnt; i++)
drvdata->setb_cfgs[i].drv = setb_cfgs[i];
ret = of_property_read_u32_array(node, "qcom,setb-gpios-pull",
(u32 *)setb_cfgs,
drvdata->setb_gpiocnt);
if (ret)
return ret;
for (i = 0; i < drvdata->setb_gpiocnt; i++)
drvdata->setb_cfgs[i].pull = setb_cfgs[i];
ret = of_property_read_u32_array(node, "qcom,setb-gpios-dir",
(u32 *)setb_cfgs,
drvdata->setb_gpiocnt);
if (ret)
return ret;
for (i = 0; i < drvdata->setb_gpiocnt; i++)
drvdata->setb_cfgs[i].dir = setb_cfgs[i];
devm_kfree(dev, setb_cfgs);
} else {
dev_err(dev, "setb gpios not specified\n");
}
out:
drvdata->nidnt = of_property_read_bool(pdev->dev.of_node,
"qcom,nidnt");
return 0;
}
static int ohci_hcd_nxp_probe(struct platform_device *pdev)
{
struct usb_hcd *hcd = 0;
const struct hc_driver *driver = &ohci_nxp_hc_driver;
struct resource *res;
int ret = 0, irq;
struct device_node *isp1301_node;
if (pdev->dev.of_node) {
isp1301_node = of_parse_phandle(pdev->dev.of_node,
"transceiver", 0);
} else {
isp1301_node = NULL;
}
isp1301_i2c_client = isp1301_get_client(isp1301_node);
if (!isp1301_i2c_client) {
return -EPROBE_DEFER;
}
ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
if (ret)
goto fail_disable;
dev_dbg(&pdev->dev, "%s: " DRIVER_DESC " (nxp)\n", hcd_name);
if (usb_disabled()) {
dev_err(&pdev->dev, "USB is disabled\n");
ret = -ENODEV;
goto fail_disable;
}
/* Enable AHB slave USB clock, needed for further USB clock control */
__raw_writel(USB_SLAVE_HCLK_EN | PAD_CONTROL_LAST_DRIVEN, USB_CTRL);
/* Enable USB PLL */
usb_pll_clk = devm_clk_get(&pdev->dev, "ck_pll5");
if (IS_ERR(usb_pll_clk)) {
dev_err(&pdev->dev, "failed to acquire USB PLL\n");
ret = PTR_ERR(usb_pll_clk);
goto fail_disable;
}
ret = clk_enable(usb_pll_clk);
if (ret < 0) {
dev_err(&pdev->dev, "failed to start USB PLL\n");
goto fail_disable;
}
ret = clk_set_rate(usb_pll_clk, 48000);
if (ret < 0) {
dev_err(&pdev->dev, "failed to set USB clock rate\n");
goto fail_rate;
}
/* Enable USB device clock */
usb_dev_clk = devm_clk_get(&pdev->dev, "ck_usbd");
if (IS_ERR(usb_dev_clk)) {
dev_err(&pdev->dev, "failed to acquire USB DEV Clock\n");
ret = PTR_ERR(usb_dev_clk);
goto fail_rate;
}
ret = clk_enable(usb_dev_clk);
if (ret < 0) {
dev_err(&pdev->dev, "failed to start USB DEV Clock\n");
goto fail_rate;
}
/* Enable USB otg clocks */
usb_otg_clk = devm_clk_get(&pdev->dev, "ck_usb_otg");
if (IS_ERR(usb_otg_clk)) {
dev_err(&pdev->dev, "failed to acquire USB DEV Clock\n");
ret = PTR_ERR(usb_otg_clk);
goto fail_otg;
}
__raw_writel(__raw_readl(USB_CTRL) | USB_HOST_NEED_CLK_EN, USB_CTRL);
ret = clk_enable(usb_otg_clk);
if (ret < 0) {
dev_err(&pdev->dev, "failed to start USB DEV Clock\n");
goto fail_otg;
}
isp1301_configure();
hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
if (!hcd) {
dev_err(&pdev->dev, "Failed to allocate HC buffer\n");
ret = -ENOMEM;
goto fail_hcd;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
hcd->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(hcd->regs)) {
ret = PTR_ERR(hcd->regs);
goto fail_resource;
}
hcd->rsrc_start = res->start;
hcd->rsrc_len = resource_size(res);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
ret = -ENXIO;
goto fail_resource;
}
ohci_nxp_start_hc();
platform_set_drvdata(pdev, hcd);
dev_info(&pdev->dev, "at 0x%p, irq %d\n", hcd->regs, hcd->irq);
ret = usb_add_hcd(hcd, irq, 0);
if (ret == 0) {
device_wakeup_enable(hcd->self.controller);
return ret;
}
ohci_nxp_stop_hc();
fail_resource:
usb_put_hcd(hcd);
fail_hcd:
clk_disable(usb_otg_clk);
fail_otg:
clk_disable(usb_dev_clk);
fail_rate:
clk_disable(usb_pll_clk);
fail_disable:
isp1301_i2c_client = NULL;
return ret;
}
static int at91sam9g20ek_audio_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *codec_np, *cpu_np;
struct clk *pllb;
struct snd_soc_card *card = &snd_soc_at91sam9g20ek;
int ret;
if (!np) {
return -ENODEV;
}
ret = atmel_ssc_set_audio(0);
if (ret) {
dev_err(&pdev->dev, "ssc channel is not valid\n");
return -EINVAL;
}
/*
* Codec MCLK is supplied by PCK0 - set it up.
*/
mclk = clk_get(NULL, "pck0");
if (IS_ERR(mclk)) {
printk(KERN_ERR "ASoC: Failed to get MCLK\n");
ret = PTR_ERR(mclk);
goto err;
}
pllb = clk_get(NULL, "pllb");
if (IS_ERR(pllb)) {
printk(KERN_ERR "ASoC: Failed to get PLLB\n");
ret = PTR_ERR(pllb);
goto err_mclk;
}
ret = clk_set_parent(mclk, pllb);
clk_put(pllb);
if (ret != 0) {
printk(KERN_ERR "ASoC: Failed to set MCLK parent\n");
goto err_mclk;
}
clk_set_rate(mclk, MCLK_RATE);
card->dev = &pdev->dev;
/* Parse device node info */
ret = snd_soc_of_parse_card_name(card, "atmel,model");
if (ret)
goto err;
ret = snd_soc_of_parse_audio_routing(card,
"atmel,audio-routing");
if (ret)
goto err;
/* Parse codec info */
at91sam9g20ek_dai.codec_name = NULL;
codec_np = of_parse_phandle(np, "atmel,audio-codec", 0);
if (!codec_np) {
dev_err(&pdev->dev, "codec info missing\n");
return -EINVAL;
}
at91sam9g20ek_dai.codec_of_node = codec_np;
/* Parse dai and platform info */
at91sam9g20ek_dai.cpu_dai_name = NULL;
at91sam9g20ek_dai.platform_name = NULL;
cpu_np = of_parse_phandle(np, "atmel,ssc-controller", 0);
if (!cpu_np) {
dev_err(&pdev->dev, "dai and pcm info missing\n");
return -EINVAL;
}
at91sam9g20ek_dai.cpu_of_node = cpu_np;
at91sam9g20ek_dai.platform_of_node = cpu_np;
of_node_put(codec_np);
of_node_put(cpu_np);
ret = snd_soc_register_card(card);
if (ret) {
printk(KERN_ERR "ASoC: snd_soc_register_card() failed\n");
}
return ret;
err_mclk:
clk_put(mclk);
mclk = NULL;
err:
atmel_ssc_put_audio(0);
return ret;
}
struct coresight_platform_data *of_get_coresight_platform_data(
struct device *dev, struct device_node *node)
{
int i, ret = 0;
uint32_t outports_len = 0;
struct device_node *child_node;
struct coresight_platform_data *pdata;
pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return ERR_PTR(-ENOMEM);
ret = of_property_read_u32(node, "coresight-id", &pdata->id);
if (ret)
return ERR_PTR(ret);
ret = of_property_read_string(node, "coresight-name", &pdata->name);
if (ret)
return ERR_PTR(ret);
ret = of_property_read_u32(node, "coresight-nr-inports",
&pdata->nr_inports);
if (ret)
return ERR_PTR(ret);
pdata->nr_outports = 0;
if (of_get_property(node, "coresight-outports", &outports_len))
pdata->nr_outports = outports_len/sizeof(uint32_t);
if (pdata->nr_outports) {
pdata->outports = devm_kzalloc(dev, pdata->nr_outports *
sizeof(*pdata->outports),
GFP_KERNEL);
if (!pdata->outports)
return ERR_PTR(-ENOMEM);
ret = of_property_read_u32_array(node, "coresight-outports",
(u32 *)pdata->outports,
pdata->nr_outports);
if (ret)
return ERR_PTR(ret);
pdata->child_ids = devm_kzalloc(dev, pdata->nr_outports *
sizeof(*pdata->child_ids),
GFP_KERNEL);
if (!pdata->child_ids)
return ERR_PTR(-ENOMEM);
for (i = 0; i < pdata->nr_outports; i++) {
child_node = of_parse_phandle(node,
"coresight-child-list",
i);
if (!child_node)
return ERR_PTR(-EINVAL);
ret = of_property_read_u32(child_node, "coresight-id",
(u32 *)&pdata->child_ids[i]);
of_node_put(child_node);
if (ret)
return ERR_PTR(ret);
}
pdata->child_ports = devm_kzalloc(dev, pdata->nr_outports *
sizeof(*pdata->child_ports),
GFP_KERNEL);
if (!pdata->child_ports)
return ERR_PTR(-ENOMEM);
ret = of_property_read_u32_array(node, "coresight-child-ports",
(u32 *)pdata->child_ports,
pdata->nr_outports);
if (ret)
return ERR_PTR(ret);
}
pdata->default_sink = of_property_read_bool(node,
"coresight-default-sink");
return pdata;
}
static int dsa_slave_phy_setup(struct dsa_slave_priv *p,
struct net_device *slave_dev)
{
struct dsa_switch *ds = p->parent;
struct dsa_chip_data *cd = ds->pd;
struct device_node *phy_dn, *port_dn;
bool phy_is_fixed = false;
u32 phy_flags = 0;
int mode, ret;
port_dn = cd->port_dn[p->port];
mode = of_get_phy_mode(port_dn);
if (mode < 0)
mode = PHY_INTERFACE_MODE_NA;
p->phy_interface = mode;
phy_dn = of_parse_phandle(port_dn, "phy-handle", 0);
if (of_phy_is_fixed_link(port_dn)) {
/* In the case of a fixed PHY, the DT node associated
* to the fixed PHY is the Port DT node
*/
ret = of_phy_register_fixed_link(port_dn);
if (ret) {
netdev_err(slave_dev, "failed to register fixed PHY\n");
return ret;
}
phy_is_fixed = true;
phy_dn = port_dn;
}
if (ds->drv->get_phy_flags)
phy_flags = ds->drv->get_phy_flags(ds, p->port);
if (phy_dn) {
ret = of_mdio_parse_addr(&slave_dev->dev, phy_dn);
/* If this PHY address is part of phys_mii_mask, which means
* that we need to divert reads and writes to/from it, then we
* want to bind this device using the slave MII bus created by
* DSA to make that happen.
*/
if (!phy_is_fixed && ret >= 0 &&
(ds->phys_mii_mask & (1 << ret))) {
ret = dsa_slave_phy_connect(p, slave_dev, ret);
if (ret)
return ret;
} else {
p->phy = of_phy_connect(slave_dev, phy_dn,
dsa_slave_adjust_link,
phy_flags,
p->phy_interface);
}
}
if (p->phy && phy_is_fixed)
fixed_phy_set_link_update(p->phy, dsa_slave_fixed_link_update);
/* We could not connect to a designated PHY, so use the switch internal
* MDIO bus instead
*/
if (!p->phy) {
ret = dsa_slave_phy_connect(p, slave_dev, p->port);
if (ret)
return ret;
} else {
netdev_info(slave_dev, "attached PHY at address %d [%s]\n",
p->phy->addr, p->phy->drv->name);
}
return 0;
}
static int kpssv1_release_secondary(unsigned int cpu)
{
int ret = 0;
void __iomem *reg, *saw_reg;
struct device_node *cpu_node, *acc_node, *saw_node;
u32 val;
cpu_node = of_get_cpu_node(cpu, NULL);
if (!cpu_node)
return -ENODEV;
acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
if (!acc_node) {
ret = -ENODEV;
goto out_acc;
}
saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0);
if (!saw_node) {
ret = -ENODEV;
goto out_saw;
}
reg = of_iomap(acc_node, 0);
if (!reg) {
ret = -ENOMEM;
goto out_acc_map;
}
saw_reg = of_iomap(saw_node, 0);
if (!saw_reg) {
ret = -ENOMEM;
goto out_saw_map;
}
/* Turn on CPU rail */
writel_relaxed(0xA4, saw_reg + APCS_SAW2_VCTL);
mb();
udelay(512);
/* Krait bring-up sequence */
val = PLL_CLAMP | L2DT_SLP | CLAMP;
writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
val &= ~L2DT_SLP;
writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
mb();
ndelay(300);
val |= COREPOR_RST;
writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
mb();
udelay(2);
val &= ~CLAMP;
writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
mb();
udelay(2);
val &= ~COREPOR_RST;
writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
mb();
udelay(100);
val |= CORE_PWRD_UP;
writel_relaxed(val, reg + APCS_CPU_PWR_CTL);
mb();
iounmap(saw_reg);
out_saw_map:
iounmap(reg);
out_acc_map:
of_node_put(saw_node);
out_saw:
of_node_put(acc_node);
out_acc:
of_node_put(cpu_node);
return ret;
}
static int tegra_wm8753_driver_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &snd_soc_tegra_wm8753;
struct tegra_wm8753 *machine;
struct tegra_asoc_platform_data *pdata;
int ret;
pdata = pdev->dev.platform_data;
if (!pdata) {
dev_err(&pdev->dev, "No platform data supplied\n");
return -EINVAL;
}
machine = devm_kzalloc(&pdev->dev, sizeof(struct tegra_wm8753),
GFP_KERNEL);
if (!machine) {
dev_err(&pdev->dev, "Can't allocate tegra_wm8753 struct\n");
ret = -ENOMEM;
goto err;
}
card->dev = &pdev->dev;
platform_set_drvdata(pdev, card);
snd_soc_card_set_drvdata(card, machine);
ret = snd_soc_of_parse_card_name(card, "nvidia,model");
if (ret)
goto err;
ret = snd_soc_of_parse_audio_routing(card, "nvidia,audio-routing");
if (ret)
goto err;
tegra_wm8753_dai.codec_of_node = of_parse_phandle(
pdev->dev.of_node, "nvidia,audio-codec", 0);
if (!tegra_wm8753_dai.codec_of_node) {
dev_err(&pdev->dev,
"Property 'nvidia,audio-codec' missing or invalid\n");
ret = -EINVAL;
goto err;
}
tegra_wm8753_dai.cpu_of_node = of_parse_phandle(
pdev->dev.of_node, "nvidia,i2s-controller", 0);
if (!tegra_wm8753_dai.cpu_of_node) {
dev_err(&pdev->dev,
"Property 'nvidia,i2s-controller' missing or invalid\n");
ret = -EINVAL;
goto err;
}
tegra_wm8753_dai.platform_of_node =
tegra_wm8753_dai.cpu_of_node;
ret = tegra_asoc_utils_init(&machine->util_data, &pdev->dev, card);
if (ret)
goto err;
ret = snd_soc_register_card(card);
if (ret) {
dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
ret);
goto err_fini_utils;
}
if (!card->instantiated) {
dev_err(&pdev->dev, "No WM8753 codec\n");
goto err_unregister_card;
}
#ifdef CONFIG_SWITCH
/* Add h2w swith class support */
ret = tegra_asoc_switch_register(&wired_switch_dev);
if (ret < 0) {
dev_err(&pdev->dev, "not able to register switch device\n");
goto err_unregister_card;
}
#endif
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
ret = tegra_asoc_utils_set_parent(&machine->util_data,
pdata->i2s_param[HIFI_CODEC].is_i2s_master);
if (ret) {
dev_err(&pdev->dev, "tegra_asoc_utils_set_parent failed (%d)\n",
ret);
goto err_unregister_card;
}
#endif
return 0;
err_unregister_card:
snd_soc_unregister_card(card);
err_fini_utils:
tegra_asoc_utils_fini(&machine->util_data);
err:
return ret;
}
static int kpssv2_release_secondary(unsigned int cpu)
{
void __iomem *reg;
struct device_node *cpu_node, *l2_node, *acc_node, *saw_node;
void __iomem *l2_saw_base;
unsigned reg_val;
int ret;
cpu_node = of_get_cpu_node(cpu, NULL);
if (!cpu_node)
return -ENODEV;
acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
if (!acc_node) {
ret = -ENODEV;
goto out_acc;
}
l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);
if (!l2_node) {
ret = -ENODEV;
goto out_l2;
}
saw_node = of_parse_phandle(l2_node, "qcom,saw", 0);
if (!saw_node) {
ret = -ENODEV;
goto out_saw;
}
reg = of_iomap(acc_node, 0);
if (!reg) {
ret = -ENOMEM;
goto out_map;
}
l2_saw_base = of_iomap(saw_node, 0);
if (!l2_saw_base) {
ret = -ENOMEM;
goto out_saw_map;
}
/* Turn on the BHS, turn off LDO Bypass and power down LDO */
reg_val = (64 << BHS_CNT_SHIFT) | (0x3f << LDO_PWR_DWN_SHIFT) | BHS_EN;
writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
mb();
/* wait for the BHS to settle */
udelay(1);
/* Turn on BHS segments */
reg_val |= 0x3f << BHS_SEG_SHIFT;
writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
mb();
/* wait for the BHS to settle */
udelay(1);
/* Finally turn on the bypass so that BHS supplies power */
reg_val |= 0x3f << LDO_BYP_SHIFT;
writel_relaxed(reg_val, reg + APC_PWR_GATE_CTL);
/* enable max phases */
writel_relaxed(0x10003, l2_saw_base + APCS_SAW2_2_VCTL);
mb();
udelay(50);
reg_val = COREPOR_RST | CLAMP;
writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
mb();
udelay(2);
reg_val &= ~CLAMP;
writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
mb();
udelay(2);
reg_val &= ~COREPOR_RST;
writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
mb();
reg_val |= CORE_PWRD_UP;
writel_relaxed(reg_val, reg + APCS_CPU_PWR_CTL);
mb();
ret = 0;
iounmap(l2_saw_base);
out_saw_map:
iounmap(reg);
out_map:
of_node_put(saw_node);
out_saw:
of_node_put(l2_node);
out_l2:
of_node_put(acc_node);
out_acc:
of_node_put(cpu_node);
return ret;
}
static int ti_dra7_xbar_probe(struct platform_device *pdev)
{
struct device_node *node = pdev->dev.of_node;
const struct of_device_id *match;
struct device_node *dma_node;
struct ti_dra7_xbar_data *xbar;
struct property *prop;
struct resource *res;
u32 safe_val;
size_t sz;
void __iomem *iomem;
int i, ret;
if (!node)
return -ENODEV;
xbar = devm_kzalloc(&pdev->dev, sizeof(*xbar), GFP_KERNEL);
if (!xbar)
return -ENOMEM;
dma_node = of_parse_phandle(node, "dma-masters", 0);
if (!dma_node) {
dev_err(&pdev->dev, "Can't get DMA master node\n");
return -ENODEV;
}
match = of_match_node(ti_dra7_master_match, dma_node);
if (!match) {
dev_err(&pdev->dev, "DMA master is not supported\n");
return -EINVAL;
}
if (of_property_read_u32(dma_node, "dma-requests",
&xbar->dma_requests)) {
dev_info(&pdev->dev,
"Missing XBAR output information, using %u.\n",
TI_DRA7_XBAR_OUTPUTS);
xbar->dma_requests = TI_DRA7_XBAR_OUTPUTS;
}
of_node_put(dma_node);
xbar->dma_inuse = devm_kcalloc(&pdev->dev,
BITS_TO_LONGS(xbar->dma_requests),
sizeof(unsigned long), GFP_KERNEL);
if (!xbar->dma_inuse)
return -ENOMEM;
if (of_property_read_u32(node, "dma-requests", &xbar->xbar_requests)) {
dev_info(&pdev->dev,
"Missing XBAR input information, using %u.\n",
TI_DRA7_XBAR_INPUTS);
xbar->xbar_requests = TI_DRA7_XBAR_INPUTS;
}
if (!of_property_read_u32(node, "ti,dma-safe-map", &safe_val))
xbar->safe_val = (u16)safe_val;
prop = of_find_property(node, "ti,reserved-dma-request-ranges", &sz);
if (prop) {
const char pname[] = "ti,reserved-dma-request-ranges";
u32 (*rsv_events)[2];
size_t nelm = sz / sizeof(*rsv_events);
int i;
if (!nelm)
return -EINVAL;
rsv_events = kcalloc(nelm, sizeof(*rsv_events), GFP_KERNEL);
if (!rsv_events)
return -ENOMEM;
ret = of_property_read_u32_array(node, pname, (u32 *)rsv_events,
nelm * 2);
if (ret)
return ret;
for (i = 0; i < nelm; i++) {
ti_dra7_xbar_reserve(rsv_events[i][0], rsv_events[i][1],
xbar->dma_inuse);
}
kfree(rsv_events);
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
iomem = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(iomem))
return PTR_ERR(iomem);
xbar->iomem = iomem;
xbar->dmarouter.dev = &pdev->dev;
xbar->dmarouter.route_free = ti_dra7_xbar_free;
xbar->dma_offset = (u32)match->data;
mutex_init(&xbar->mutex);
platform_set_drvdata(pdev, xbar);
/* Reset the crossbar */
for (i = 0; i < xbar->dma_requests; i++) {
if (!test_bit(i, xbar->dma_inuse))
ti_dra7_xbar_write(xbar->iomem, i, xbar->safe_val);
}
ret = of_dma_router_register(node, ti_dra7_xbar_route_allocate,
&xbar->dmarouter);
if (ret) {
/* Restore the defaults for the crossbar */
for (i = 0; i < xbar->dma_requests; i++) {
if (!test_bit(i, xbar->dma_inuse))
ti_dra7_xbar_write(xbar->iomem, i, i);
}
}
return ret;
}
static int tegra_alc5632_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct snd_soc_card *card = &snd_soc_tegra_alc5632;
struct tegra_alc5632 *alc5632;
int ret;
alc5632 = devm_kzalloc(&pdev->dev,
sizeof(struct tegra_alc5632), GFP_KERNEL);
if (!alc5632) {
dev_err(&pdev->dev, "Can't allocate tegra_alc5632\n");
return -ENOMEM;
}
card->dev = &pdev->dev;
platform_set_drvdata(pdev, card);
snd_soc_card_set_drvdata(card, alc5632);
alc5632->gpio_hp_det = of_get_named_gpio(np, "nvidia,hp-det-gpios", 0);
if (alc5632->gpio_hp_det == -EPROBE_DEFER)
return -EPROBE_DEFER;
ret = snd_soc_of_parse_card_name(card, "nvidia,model");
if (ret)
goto err;
ret = snd_soc_of_parse_audio_routing(card, "nvidia,audio-routing");
if (ret)
goto err;
tegra_alc5632_dai.codec_of_node = of_parse_phandle(
pdev->dev.of_node, "nvidia,audio-codec", 0);
if (!tegra_alc5632_dai.codec_of_node) {
dev_err(&pdev->dev,
"Property 'nvidia,audio-codec' missing or invalid\n");
ret = -EINVAL;
goto err;
}
tegra_alc5632_dai.cpu_of_node = of_parse_phandle(np,
"nvidia,i2s-controller", 0);
if (!tegra_alc5632_dai.cpu_of_node) {
dev_err(&pdev->dev,
"Property 'nvidia,i2s-controller' missing or invalid\n");
ret = -EINVAL;
goto err;
}
tegra_alc5632_dai.platform_of_node = tegra_alc5632_dai.cpu_of_node;
ret = tegra_asoc_utils_init(&alc5632->util_data, &pdev->dev);
if (ret)
goto err;
ret = snd_soc_register_card(card);
if (ret) {
dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
ret);
goto err_fini_utils;
}
return 0;
err_fini_utils:
tegra_asoc_utils_fini(&alc5632->util_data);
err:
return ret;
}
/* Search EMAC board, allocate space and register it
*/
static int emac_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct emac_board_info *db;
struct net_device *ndev;
int ret = 0;
const char *mac_addr;
ndev = alloc_etherdev(sizeof(struct emac_board_info));
if (!ndev) {
dev_err(&pdev->dev, "could not allocate device.\n");
return -ENOMEM;
}
SET_NETDEV_DEV(ndev, &pdev->dev);
db = netdev_priv(ndev);
memset(db, 0, sizeof(*db));
db->dev = &pdev->dev;
db->ndev = ndev;
db->pdev = pdev;
spin_lock_init(&db->lock);
db->membase = of_iomap(np, 0);
if (!db->membase) {
dev_err(&pdev->dev, "failed to remap registers\n");
ret = -ENOMEM;
goto out;
}
/* fill in parameters for net-dev structure */
ndev->base_addr = (unsigned long)db->membase;
ndev->irq = irq_of_parse_and_map(np, 0);
if (ndev->irq == -ENXIO) {
netdev_err(ndev, "No irq resource\n");
ret = ndev->irq;
goto out;
}
db->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(db->clk)) {
ret = PTR_ERR(db->clk);
goto out;
}
clk_prepare_enable(db->clk);
ret = sunxi_sram_claim(&pdev->dev);
if (ret) {
dev_err(&pdev->dev, "Error couldn't map SRAM to device\n");
goto out;
}
db->phy_node = of_parse_phandle(np, "phy", 0);
if (!db->phy_node) {
dev_err(&pdev->dev, "no associated PHY\n");
ret = -ENODEV;
goto out_release_sram;
}
/* Read MAC-address from DT */
mac_addr = of_get_mac_address(np);
if (mac_addr)
memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
/* Check if the MAC address is valid, if not get a random one */
if (!is_valid_ether_addr(ndev->dev_addr)) {
eth_hw_addr_random(ndev);
dev_warn(&pdev->dev, "using random MAC address %pM\n",
ndev->dev_addr);
}
db->emacrx_completed_flag = 1;
emac_powerup(ndev);
emac_reset(db);
ndev->netdev_ops = &emac_netdev_ops;
ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
ndev->ethtool_ops = &emac_ethtool_ops;
platform_set_drvdata(pdev, ndev);
/* Carrier starts down, phylib will bring it up */
netif_carrier_off(ndev);
ret = register_netdev(ndev);
if (ret) {
dev_err(&pdev->dev, "Registering netdev failed!\n");
ret = -ENODEV;
goto out_release_sram;
}
dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n",
ndev->name, db->membase, ndev->irq, ndev->dev_addr);
return 0;
out_release_sram:
sunxi_sram_release(&pdev->dev);
out:
dev_err(db->dev, "not found (%d).\n", ret);
free_netdev(ndev);
return ret;
}
static int power_on_l2_msm8976(struct device_node *l2ccc_node, u32 pon_mask,
int cpu)
{
u32 pon_status;
void __iomem *l2_base;
int ret = 0;
struct device_node *vctl_node;
uint32_t val;
vctl_node = of_parse_phandle(l2ccc_node, "qcom,vctl-node", 0);
if (!vctl_node)
return -ENODEV;
l2_base = of_iomap_by_name(l2ccc_node, "l2-base");
if (!l2_base)
return -ENOMEM;
/* Skip power-on sequence if l2 cache is already powered up */
pon_status = (__raw_readl(l2_base + L2_PWR_CTL) & pon_mask)
== pon_mask;
/* Check L2 SPM Status */
if (pon_status) {
ret = kick_l2spm(l2ccc_node, vctl_node);
iounmap(l2_base);
return ret;
}
/* Need to power on the rail */
ret = of_property_read_u32(l2ccc_node, "qcom,vctl-val", &val);
if (ret) {
iounmap(l2_base);
pr_err("Unable to read L2 voltage\n");
return -EFAULT;
}
ret = msm_spm_turn_on_cpu_rail(vctl_node, val, cpu, L2_VREG_CTL);
if (ret) {
iounmap(l2_base);
pr_err("Error turning on power rail.\n");
return -EFAULT;
}
/* Close Few of the head-switches for L2SCU logic */
writel_relaxed(0x10F700, l2_base + L2_PWR_CTL);
mb();
udelay(2);
/* Close Rest of the head-switches for L2SCU logic */
writel_relaxed(0x410F700, l2_base + L2_PWR_CTL);
mb();
udelay(2);
/* Assert PRESETDBG */
writel_relaxed(0x400000, l2_base + L2_PWR_CTL_OVERRIDE);
mb();
udelay(2);
/* De-assert L2/SCU memory Clamp */
writel_relaxed(0x4103700, l2_base + L2_PWR_CTL);
/* Assert L2 memory slp_nret_n */
writel_relaxed(0x4103703, l2_base + L2_PWR_CTL);
mb();
udelay(4);
/* Assert L2 memory slp_ret_n */
writel_relaxed(0x4101703, l2_base + L2_PWR_CTL);
mb();
udelay(4);
/* Assert L2 memory wl_en_clk */
writel_relaxed(0x4101783, l2_base + L2_PWR_CTL);
mb();
udelay(1);
/* De-assert L2 memory wl_en_clk */
writel_relaxed(0x4101703, l2_base + L2_PWR_CTL);
mb();
/* Enable clocks via SW_CLK_EN */
writel_relaxed(0x01, l2_base + L2_CORE_CBCR);
/* De-assert L2/SCU logic clamp */
writel_relaxed(0x4101603, l2_base + L2_PWR_CTL);
mb();
udelay(2);
/* De-assert PRESETDBG */
writel_relaxed(0x0, l2_base + L2_PWR_CTL_OVERRIDE);
/* De-assert L2/SCU Logic reset */
writel_relaxed(0x4100203, l2_base + L2_PWR_CTL);
mb();
udelay(54);
/* Turn on the PMIC_APC */
writel_relaxed(0x14100203, l2_base + L2_PWR_CTL);
/* Set H/W clock control for the cluster CBC block */
writel_relaxed(0x03, l2_base + L2_CORE_CBCR);
mb();
iounmap(l2_base);
return 0;
}
static int32_t msm_flash_get_pmic_source_info(
struct device_node *of_node,
struct msm_flash_ctrl_t *fctrl)
{
int32_t rc = 0;
uint32_t count = 0, i = 0;
struct device_node *flash_src_node = NULL;
struct device_node *torch_src_node = NULL;
if (of_get_property(of_node, "qcom,flash-source", &count)) {
count /= sizeof(uint32_t);
CDBG("count %d\n", count);
if (count > MAX_LED_TRIGGERS) {
pr_err("invalid count\n");
return -EINVAL;
}
fctrl->flash_num_sources = count;
CDBG("%s:%d flash_num_sources = %d",
__func__, __LINE__, fctrl->flash_num_sources);
for (i = 0; i < count; i++) {
flash_src_node = of_parse_phandle(of_node,
"qcom,flash-source", i);
if (!flash_src_node) {
pr_err("flash_src_node NULL\n");
continue;
}
rc = of_property_read_string(flash_src_node,
"qcom,default-led-trigger",
&fctrl->flash_trigger_name[i]);
if (rc < 0) {
rc = of_property_read_string(flash_src_node,
"linux,default-trigger",
&fctrl->flash_trigger_name[i]);
if (rc < 0) {
pr_err("default-trigger read failed\n");
of_node_put(flash_src_node);
continue;
}
}
CDBG("default trigger %s\n",
fctrl->flash_trigger_name[i]);
/* Read operational-current */
rc = of_property_read_u32(flash_src_node,
"qcom,current",
&fctrl->flash_op_current[i]);
if (rc < 0) {
pr_err("current: read failed\n");
of_node_put(flash_src_node);
continue;
}
/* Read max-current */
rc = of_property_read_u32(flash_src_node,
"qcom,max-current",
&fctrl->flash_max_current[i]);
if (rc < 0) {
pr_err("current: read failed\n");
of_node_put(flash_src_node);
continue;
}
of_node_put(flash_src_node);
CDBG("max_current[%d] %d\n",
i, fctrl->flash_op_current[i]);
led_trigger_register_simple(
fctrl->flash_trigger_name[i],
&fctrl->flash_trigger[i]);
}
if (fctrl->flash_driver_type == FLASH_DRIVER_DEFAULT)
fctrl->flash_driver_type = FLASH_DRIVER_PMIC;
CDBG("%s:%d fctrl->flash_driver_type = %d", __func__, __LINE__,
fctrl->flash_driver_type);
}
if (of_get_property(of_node, "qcom,torch-source", &count)) {
count /= sizeof(uint32_t);
CDBG("count %d\n", count);
if (count > MAX_LED_TRIGGERS) {
pr_err("invalid count\n");
return -EINVAL;
}
fctrl->torch_num_sources = count;
CDBG("%s:%d torch_num_sources = %d",
__func__, __LINE__, fctrl->torch_num_sources);
for (i = 0; i < count; i++) {
torch_src_node = of_parse_phandle(of_node,
"qcom,torch-source", i);
if (!torch_src_node) {
pr_err("torch_src_node NULL\n");
continue;
}
rc = of_property_read_string(torch_src_node,
"qcom,default-led-trigger",
&fctrl->torch_trigger_name[i]);
if (rc < 0) {
rc = of_property_read_string(torch_src_node,
"linux,default-trigger",
&fctrl->torch_trigger_name[i]);
if (rc < 0) {
pr_err("default-trigger read failed\n");
of_node_put(torch_src_node);
continue;
}
}
CDBG("default trigger %s\n",
fctrl->torch_trigger_name[i]);
/* Read operational-current */
rc = of_property_read_u32(torch_src_node,
"qcom,current",
&fctrl->torch_op_current[i]);
if (rc < 0) {
pr_err("current: read failed\n");
of_node_put(torch_src_node);
continue;
}
/* Read max-current */
rc = of_property_read_u32(torch_src_node,
"qcom,max-current",
&fctrl->torch_max_current[i]);
if (rc < 0) {
pr_err("current: read failed\n");
of_node_put(torch_src_node);
continue;
}
of_node_put(torch_src_node);
CDBG("max_current[%d] %d\n",
i, fctrl->torch_op_current[i]);
led_trigger_register_simple(
fctrl->torch_trigger_name[i],
&fctrl->torch_trigger[i]);
}
if (fctrl->flash_driver_type == FLASH_DRIVER_DEFAULT)
fctrl->flash_driver_type = FLASH_DRIVER_PMIC;
CDBG("%s:%d fctrl->flash_driver_type = %d", __func__, __LINE__,
fctrl->flash_driver_type);
}
return 0;
}
static int power_on_l2_msm8916(struct device_node *l2ccc_node, u32 pon_mask,
int cpu)
{
u32 pon_status;
void __iomem *l2_base;
int ret = 0;
struct device_node *vctl_node;
vctl_node = of_parse_phandle(l2ccc_node, "qcom,vctl-node", 0);
if (vctl_node)
vctl_parsed = true;
l2_base = of_iomap_by_name(l2ccc_node, "l2-base");
if (!l2_base)
return -ENOMEM;
/* Skip power-on sequence if l2 cache is already powered up*/
pon_status = (__raw_readl(l2_base + L2_PWR_CTL) & pon_mask)
== pon_mask;
/* Check L2 SPM Status */
if (pon_status) {
if (vctl_node)
ret = kick_l2spm(l2ccc_node, vctl_node);
iounmap(l2_base);
return ret;
}
/* Close L2/SCU Logic GDHS and power up the cache */
writel_relaxed(0x10D700, l2_base + L2_PWR_CTL);
/* Assert PRESETDBGn */
writel_relaxed(0x400000, l2_base + L2_PWR_CTL_OVERRIDE);
mb();
udelay(2);
/* De-assert L2/SCU memory Clamp */
writel_relaxed(0x101700, l2_base + L2_PWR_CTL);
/* Wakeup L2/SCU RAMs by deasserting sleep signals */
writel_relaxed(0x101703, l2_base + L2_PWR_CTL);
mb();
udelay(2);
/* Enable clocks via SW_CLK_EN */
writel_relaxed(0x01, l2_base + L2_CORE_CBCR);
/* De-assert L2/SCU logic clamp */
writel_relaxed(0x101603, l2_base + L2_PWR_CTL);
mb();
udelay(2);
/* De-assert PRESSETDBg */
writel_relaxed(0x0, l2_base + L2_PWR_CTL_OVERRIDE);
/* De-assert L2/SCU Logic reset */
writel_relaxed(0x100203, l2_base + L2_PWR_CTL);
mb();
udelay(54);
/* Turn on the PMIC_APC */
writel_relaxed(0x10100203, l2_base + L2_PWR_CTL);
/* Set H/W clock control for the cpu CBC block */
writel_relaxed(0x03, l2_base + L2_CORE_CBCR);
mb();
iounmap(l2_base);
return 0;
}
static int rpi_power_probe(struct platform_device *pdev)
{
struct device_node *fw_np;
struct device *dev = &pdev->dev;
struct rpi_power_domains *rpi_domains;
rpi_domains = devm_kzalloc(dev, sizeof(*rpi_domains), GFP_KERNEL);
if (!rpi_domains)
return -ENOMEM;
rpi_domains->xlate.domains =
devm_kcalloc(dev,
RPI_POWER_DOMAIN_COUNT,
sizeof(*rpi_domains->xlate.domains),
GFP_KERNEL);
if (!rpi_domains->xlate.domains)
return -ENOMEM;
rpi_domains->xlate.num_domains = RPI_POWER_DOMAIN_COUNT;
fw_np = of_parse_phandle(pdev->dev.of_node, "firmware", 0);
if (!fw_np) {
dev_err(&pdev->dev, "no firmware node\n");
return -ENODEV;
}
rpi_domains->fw = rpi_firmware_get(fw_np);
of_node_put(fw_np);
if (!rpi_domains->fw)
return -EPROBE_DEFER;
rpi_domains->has_new_interface =
rpi_has_new_domain_support(rpi_domains);
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_I2C0, "I2C0");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_I2C1, "I2C1");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_I2C2, "I2C2");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_VIDEO_SCALER,
"VIDEO_SCALER");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_VPU1, "VPU1");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_HDMI, "HDMI");
/*
* Use the old firmware interface for USB power, so that we
* can turn it on even if the firmware hasn't been updated.
*/
rpi_init_old_power_domain(rpi_domains, RPI_POWER_DOMAIN_USB,
RPI_OLD_POWER_DOMAIN_USB, "USB");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_VEC, "VEC");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_JPEG, "JPEG");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_H264, "H264");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_V3D, "V3D");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_ISP, "ISP");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_UNICAM0, "UNICAM0");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_UNICAM1, "UNICAM1");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_CCP2RX, "CCP2RX");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_CSI2, "CSI2");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_CPI, "CPI");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_DSI0, "DSI0");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_DSI1, "DSI1");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_TRANSPOSER,
"TRANSPOSER");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_CCP2TX, "CCP2TX");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_CDP, "CDP");
rpi_init_power_domain(rpi_domains, RPI_POWER_DOMAIN_ARM, "ARM");
of_genpd_add_provider_onecell(dev->of_node, &rpi_domains->xlate);
platform_set_drvdata(pdev, rpi_domains);
return 0;
}
static int power_on_l2_msm8994(struct device_node *l2ccc_node, u32 pon_mask,
int cpu)
{
u32 pon_status;
void __iomem *l2_base;
int ret = 0;
uint32_t val;
struct device_node *vctl_node;
vctl_node = of_parse_phandle(l2ccc_node, "qcom,vctl-node", 0);
if (!vctl_node)
return -ENODEV;
l2_base = of_iomap_by_name(l2ccc_node, "l2-base");
if (!l2_base)
return -ENOMEM;
pon_status = (__raw_readl(l2_base + L2_PWR_CTL) & pon_mask) == pon_mask;
/* Check L2 SPM Status */
if (pon_status) {
ret = kick_l2spm(l2ccc_node, vctl_node);
iounmap(l2_base);
return ret;
}
/* Need to power on the rail */
ret = of_property_read_u32(l2ccc_node, "qcom,vctl-val", &val);
if (ret) {
iounmap(l2_base);
pr_err("Unable to read L2 voltage\n");
return -EFAULT;
}
ret = msm_spm_turn_on_cpu_rail(vctl_node, val, cpu, L2_VREG_CTL);
if (ret) {
iounmap(l2_base);
pr_err("Error turning on power rail.\n");
return -EFAULT;
}
/* Enable L1 invalidation by h/w */
writel_relaxed(0x00000000, l2_base + L1_RST_DIS);
mb();
/* Assert PRESETDBGn */
writel_relaxed(0x00400000 , l2_base + L2_PWR_CTL_OVERRIDE);
mb();
/* Close L2/SCU Logic GDHS and power up the cache */
writel_relaxed(0x00029716 , l2_base + L2_PWR_CTL);
mb();
udelay(8);
/* De-assert L2/SCU memory Clamp */
writel_relaxed(0x00023716 , l2_base + L2_PWR_CTL);
mb();
/* Wakeup L2/SCU RAMs by deasserting sleep signals */
writel_relaxed(0x0002371E , l2_base + L2_PWR_CTL);
mb();
udelay(8);
/* Un-gate clock and wait for sequential waking up
* of L2 rams with a delay of 2*X0 cycles
*/
writel_relaxed(0x0002371C , l2_base + L2_PWR_CTL);
mb();
udelay(4);
/* De-assert L2/SCU logic clamp */
writel_relaxed(0x0002361C , l2_base + L2_PWR_CTL);
mb();
udelay(2);
/* De-assert L2/SCU logic reset */
writel_relaxed(0x00022218 , l2_base + L2_PWR_CTL);
mb();
udelay(4);
/* Turn on the PMIC_APC */
writel_relaxed(0x10022218 , l2_base + L2_PWR_CTL);
mb();
/* De-assert PRESETDBGn */
writel_relaxed(0x00000000 , l2_base + L2_PWR_CTL_OVERRIDE);
mb();
iounmap(l2_base);
return 0;
}
static int fsl_asoc_card_probe(struct platform_device *pdev)
{
struct device_node *cpu_np, *codec_np, *asrc_np;
struct device_node *np = pdev->dev.of_node;
struct platform_device *asrc_pdev = NULL;
struct platform_device *cpu_pdev;
struct fsl_asoc_card_priv *priv;
struct i2c_client *codec_dev;
const char *codec_dai_name;
u32 width;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
cpu_np = of_parse_phandle(np, "audio-cpu", 0);
/* Give a chance to old DT binding */
if (!cpu_np)
cpu_np = of_parse_phandle(np, "ssi-controller", 0);
if (!cpu_np) {
dev_err(&pdev->dev, "CPU phandle missing or invalid\n");
ret = -EINVAL;
goto fail;
}
cpu_pdev = of_find_device_by_node(cpu_np);
if (!cpu_pdev) {
dev_err(&pdev->dev, "failed to find CPU DAI device\n");
ret = -EINVAL;
goto fail;
}
codec_np = of_parse_phandle(np, "audio-codec", 0);
if (codec_np)
codec_dev = of_find_i2c_device_by_node(codec_np);
else
codec_dev = NULL;
asrc_np = of_parse_phandle(np, "audio-asrc", 0);
if (asrc_np)
asrc_pdev = of_find_device_by_node(asrc_np);
/* Get the MCLK rate only, and leave it controlled by CODEC drivers */
if (codec_dev) {
struct clk *codec_clk = clk_get(&codec_dev->dev, NULL);
if (!IS_ERR(codec_clk)) {
priv->codec_priv.mclk_freq = clk_get_rate(codec_clk);
clk_put(codec_clk);
}
}
/* Default sample rate and format, will be updated in hw_params() */
priv->sample_rate = 44100;
priv->sample_format = SNDRV_PCM_FORMAT_S16_LE;
/* Assign a default DAI format, and allow each card to overwrite it */
priv->dai_fmt = DAI_FMT_BASE;
/* Diversify the card configurations */
if (of_device_is_compatible(np, "fsl,imx-audio-cs42888")) {
codec_dai_name = "cs42888";
priv->card.set_bias_level = NULL;
priv->cpu_priv.sysclk_freq[TX] = priv->codec_priv.mclk_freq;
priv->cpu_priv.sysclk_freq[RX] = priv->codec_priv.mclk_freq;
priv->cpu_priv.sysclk_dir[TX] = SND_SOC_CLOCK_OUT;
priv->cpu_priv.sysclk_dir[RX] = SND_SOC_CLOCK_OUT;
priv->cpu_priv.slot_width = 32;
priv->dai_fmt |= SND_SOC_DAIFMT_CBS_CFS;
} else if (of_device_is_compatible(np, "fsl,imx-audio-cs427x")) {
codec_dai_name = "cs4271-hifi";
priv->codec_priv.mclk_id = CS427x_SYSCLK_MCLK;
priv->dai_fmt |= SND_SOC_DAIFMT_CBM_CFM;
} else if (of_device_is_compatible(np, "fsl,imx-audio-sgtl5000")) {
codec_dai_name = "sgtl5000";
priv->codec_priv.mclk_id = SGTL5000_SYSCLK;
priv->dai_fmt |= SND_SOC_DAIFMT_CBM_CFM;
} else if (of_device_is_compatible(np, "fsl,imx-audio-wm8962")) {
codec_dai_name = "wm8962";
priv->card.set_bias_level = fsl_asoc_card_set_bias_level;
priv->codec_priv.mclk_id = WM8962_SYSCLK_MCLK;
priv->codec_priv.fll_id = WM8962_SYSCLK_FLL;
priv->codec_priv.pll_id = WM8962_FLL;
priv->dai_fmt |= SND_SOC_DAIFMT_CBM_CFM;
} else if (of_device_is_compatible(np, "fsl,imx-audio-wm8960")) {
codec_dai_name = "wm8960-hifi";
priv->card.set_bias_level = fsl_asoc_card_set_bias_level;
priv->codec_priv.fll_id = WM8960_SYSCLK_AUTO;
priv->codec_priv.pll_id = WM8960_SYSCLK_AUTO;
priv->dai_fmt |= SND_SOC_DAIFMT_CBM_CFM;
} else if (of_device_is_compatible(np, "fsl,imx-audio-ac97")) {
codec_dai_name = "ac97-hifi";
priv->card.set_bias_level = NULL;
priv->dai_fmt = SND_SOC_DAIFMT_AC97;
} else {
dev_err(&pdev->dev, "unknown Device Tree compatible\n");
ret = -EINVAL;
goto asrc_fail;
}
if (!fsl_asoc_card_is_ac97(priv) && !codec_dev) {
dev_err(&pdev->dev, "failed to find codec device\n");
ret = -EINVAL;
goto asrc_fail;
}
/* Common settings for corresponding Freescale CPU DAI driver */
if (strstr(cpu_np->name, "ssi")) {
/* Only SSI needs to configure AUDMUX */
ret = fsl_asoc_card_audmux_init(np, priv);
if (ret) {
dev_err(&pdev->dev, "failed to init audmux\n");
goto asrc_fail;
}
} else if (strstr(cpu_np->name, "esai")) {
priv->cpu_priv.sysclk_id[1] = ESAI_HCKT_EXTAL;
priv->cpu_priv.sysclk_id[0] = ESAI_HCKR_EXTAL;
} else if (strstr(cpu_np->name, "sai")) {
priv->cpu_priv.sysclk_id[1] = FSL_SAI_CLK_MAST1;
priv->cpu_priv.sysclk_id[0] = FSL_SAI_CLK_MAST1;
}
snprintf(priv->name, sizeof(priv->name), "%s-audio",
fsl_asoc_card_is_ac97(priv) ? "ac97" :
codec_dev->name);
/* Initialize sound card */
priv->pdev = pdev;
priv->card.dev = &pdev->dev;
priv->card.name = priv->name;
priv->card.dai_link = priv->dai_link;
priv->card.dapm_routes = fsl_asoc_card_is_ac97(priv) ?
audio_map_ac97 : audio_map;
priv->card.late_probe = fsl_asoc_card_late_probe;
priv->card.num_dapm_routes = ARRAY_SIZE(audio_map);
priv->card.dapm_widgets = fsl_asoc_card_dapm_widgets;
priv->card.num_dapm_widgets = ARRAY_SIZE(fsl_asoc_card_dapm_widgets);
/* Drop the second half of DAPM routes -- ASRC */
if (!asrc_pdev)
priv->card.num_dapm_routes /= 2;
memcpy(priv->dai_link, fsl_asoc_card_dai,
sizeof(struct snd_soc_dai_link) * ARRAY_SIZE(priv->dai_link));
ret = snd_soc_of_parse_audio_routing(&priv->card, "audio-routing");
if (ret) {
dev_err(&pdev->dev, "failed to parse audio-routing: %d\n", ret);
goto asrc_fail;
}
/* Normal DAI Link */
priv->dai_link[0].cpu_of_node = cpu_np;
priv->dai_link[0].codec_dai_name = codec_dai_name;
if (!fsl_asoc_card_is_ac97(priv))
priv->dai_link[0].codec_of_node = codec_np;
else {
u32 idx;
ret = of_property_read_u32(cpu_np, "cell-index", &idx);
if (ret) {
dev_err(&pdev->dev,
"cannot get CPU index property\n");
goto asrc_fail;
}
priv->dai_link[0].codec_name =
devm_kasprintf(&pdev->dev, GFP_KERNEL,
"ac97-codec.%u",
(unsigned int)idx);
}
priv->dai_link[0].platform_of_node = cpu_np;
priv->dai_link[0].dai_fmt = priv->dai_fmt;
priv->card.num_links = 1;
if (asrc_pdev) {
/* DPCM DAI Links only if ASRC exsits */
priv->dai_link[1].cpu_of_node = asrc_np;
priv->dai_link[1].platform_of_node = asrc_np;
priv->dai_link[2].codec_dai_name = codec_dai_name;
priv->dai_link[2].codec_of_node = codec_np;
priv->dai_link[2].codec_name =
priv->dai_link[0].codec_name;
priv->dai_link[2].cpu_of_node = cpu_np;
priv->dai_link[2].dai_fmt = priv->dai_fmt;
priv->card.num_links = 3;
ret = of_property_read_u32(asrc_np, "fsl,asrc-rate",
&priv->asrc_rate);
if (ret) {
dev_err(&pdev->dev, "failed to get output rate\n");
ret = -EINVAL;
goto asrc_fail;
}
ret = of_property_read_u32(asrc_np, "fsl,asrc-width", &width);
if (ret) {
dev_err(&pdev->dev, "failed to get output rate\n");
ret = -EINVAL;
goto asrc_fail;
}
if (width == 24)
priv->asrc_format = SNDRV_PCM_FORMAT_S24_LE;
else
priv->asrc_format = SNDRV_PCM_FORMAT_S16_LE;
}
/* Finish card registering */
platform_set_drvdata(pdev, priv);
snd_soc_card_set_drvdata(&priv->card, priv);
ret = devm_snd_soc_register_card(&pdev->dev, &priv->card);
if (ret)
dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
asrc_fail:
of_node_put(asrc_np);
of_node_put(codec_np);
fail:
of_node_put(cpu_np);
return ret;
}
int msm8994_unclamp_secondary_arm_cpu(unsigned int cpu)
{
int ret = 0;
int val;
struct device_node *cpu_node, *acc_node, *l2_node, *l2ccc_node;
void __iomem *acc_reg, *ldo_bhs_reg;
struct resource res;
cpu_node = of_get_cpu_node(cpu, NULL);
if (!cpu_node)
return -ENODEV;
acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
if (!acc_node) {
ret = -ENODEV;
goto out_acc;
}
l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);
if (!l2_node) {
ret = -ENODEV;
goto out_l2;
}
l2ccc_node = of_parse_phandle(l2_node, "power-domain", 0);
if (!l2ccc_node) {
ret = -ENODEV;
goto out_l2;
}
/*
* Ensure L2-cache of the CPU is powered on before
* unclamping cpu power rails.
*/
ret = power_on_l2_cache(l2ccc_node, cpu);
if (ret) {
pr_err("L2 cache power up failed for CPU%d\n", cpu);
goto out_l2ccc;
}
ldo_bhs_reg = of_iomap(acc_node, 0);
if (!ldo_bhs_reg) {
ret = -ENOMEM;
goto out_bhs_reg;
}
acc_reg = of_iomap(acc_node, 1);
if (!acc_reg) {
ret = -ENOMEM;
goto out_acc_reg;
}
/* Assert head switch enable few */
writel_relaxed(0x00000001, acc_reg + CPU_PWR_GATE_CTL);
mb();
udelay(1);
/* Assert head switch enable rest */
writel_relaxed(0x00000003, acc_reg + CPU_PWR_GATE_CTL);
mb();
udelay(1);
/* De-assert coremem clamp. This is asserted by default */
writel_relaxed(0x00000079, acc_reg + CPU_PWR_CTL);
mb();
udelay(2);
/* Close coremem array gdhs */
writel_relaxed(0x0000007D, acc_reg + CPU_PWR_CTL);
mb();
udelay(2);
/* De-assert clamp */
writel_relaxed(0x0000003D, acc_reg + CPU_PWR_CTL);
mb();
/* De-assert clamp */
writel_relaxed(0x0000003C, acc_reg + CPU_PWR_CTL);
mb();
udelay(1);
/* De-assert core0 reset */
writel_relaxed(0x0000000C, acc_reg + CPU_PWR_CTL);
mb();
/* Assert PWRDUP */
writel_relaxed(0x0000008C, acc_reg + CPU_PWR_CTL);
mb();
iounmap(acc_reg);
ret = of_address_to_resource(l2ccc_node, 1, &res);
if (ret)
goto out_acc_reg;
val = scm_io_read((u32)res.start);
val &= ~BIT(0);
scm_io_write((u32)res.start, val);
out_acc_reg:
iounmap(ldo_bhs_reg);
out_bhs_reg:
of_node_put(l2ccc_node);
out_l2ccc:
of_node_put(l2_node);
out_l2:
of_node_put(acc_node);
out_acc:
of_node_put(cpu_node);
return ret;
}
static int bimc_bwmon_driver_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct resource *res;
struct bwmon *m;
const struct of_device_id *id;
int ret;
u32 data;
m = devm_kzalloc(dev, sizeof(*m), GFP_KERNEL);
if (!m)
return -ENOMEM;
m->dev = dev;
ret = of_property_read_u32(dev->of_node, "qcom,mport", &data);
if (ret) {
dev_err(dev, "mport not found!\n");
return ret;
}
m->mport = data;
id = of_match_device(match_table, dev);
if (!id) {
dev_err(dev, "Unknown device type!\n");
return -ENODEV;
}
m->spec = id->data;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
if (!res) {
dev_err(dev, "base not found!\n");
return -EINVAL;
}
m->base = devm_ioremap(dev, res->start, resource_size(res));
if (!m->base) {
dev_err(dev, "Unable map base!\n");
return -ENOMEM;
}
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "global_base");
if (!res) {
dev_err(dev, "global_base not found!\n");
return -EINVAL;
}
m->global_base = devm_ioremap(dev, res->start, resource_size(res));
if (!m->global_base) {
dev_err(dev, "Unable map global_base!\n");
return -ENOMEM;
}
m->irq = platform_get_irq(pdev, 0);
if (m->irq < 0) {
dev_err(dev, "Unable to get IRQ number\n");
return m->irq;
}
m->hw.of_node = of_parse_phandle(dev->of_node, "qcom,target-dev", 0);
if (!m->hw.of_node)
return -EINVAL;
m->hw.start_hwmon = &start_bw_hwmon,
m->hw.stop_hwmon = &stop_bw_hwmon,
m->hw.suspend_hwmon = &suspend_bw_hwmon,
m->hw.resume_hwmon = &resume_bw_hwmon,
m->hw.meas_bw_and_set_irq = &meas_bw_and_set_irq,
ret = register_bw_hwmon(dev, &m->hw);
if (ret) {
dev_err(dev, "Dev BW hwmon registration failed\n");
return ret;
}
return 0;
}
int msm8976_cpu_ldo_config(unsigned int cpu)
{
struct device_node *cpu_node, *ldo_node;
void __iomem *ldo_bhs_reg_base;
u32 ldo_vref_ret = 0;
u32 ref_val = 0;
int ret = 0;
u32 val;
cpu_node = of_get_cpu_node(cpu, NULL);
if (!cpu_node)
return -ENODEV;
ldo_node = of_parse_phandle(cpu_node, "qcom,ldo", 0);
if (!ldo_node) {
pr_debug("LDO is not configured to enable retention\n");
goto exit_cpu_node;
}
ldo_bhs_reg_base = of_iomap(ldo_node, 0);
if (!ldo_bhs_reg_base) {
pr_err("LDO configuration failed due to iomap failure\n");
ret = -ENOMEM;
goto exit_cpu_node;
}
ret = of_property_read_u32(ldo_node, "qcom,ldo-vref-ret", &ref_val);
if (ret) {
pr_err("Failed to get LDO Reference voltage for CPU%u\n",
cpu);
ret = -ENOENT;
goto exit_cpu_node;
}
/* Bring LDO out of reset */
ldo_vref_ret = readl_relaxed(ldo_bhs_reg_base + APC_LDO_VREF_CFG);
ldo_vref_ret &= ~BIT(16);
writel_relaxed(ldo_vref_ret, ldo_bhs_reg_base + APC_LDO_VREF_CFG);
val = readl_relaxed(ldo_bhs_reg_base + APC_LDO_CFG1);
val = (val & 0xffffff00) | 0x90;
writel_relaxed(val, ldo_bhs_reg_base + APC_LDO_CFG1);
val = readl_relaxed(ldo_bhs_reg_base + APC_LDO_RDAC_CTL);
val = (val & 0xffffff00) | 0x60;
writel_relaxed(val, ldo_bhs_reg_base + APC_LDO_RDAC_CTL);
/* Program the retention voltage */
ldo_vref_ret = readl_relaxed(ldo_bhs_reg_base + APC_LDO_VREF_CFG);
ldo_vref_ret = (ldo_vref_ret & 0xffff80ff) | (ref_val << 8);
writel_relaxed(ldo_vref_ret, ldo_bhs_reg_base + APC_LDO_VREF_CFG);
/* Write the sequence to latch on the LDO voltage */
writel_relaxed(0x0, ldo_bhs_reg_base);
writel_relaxed(0x1, ldo_bhs_reg_base);
/* After writing 1 to the UPDATE register, '1 xo clk cycle' delay
* is required for the update to take effect. This delay needs to
* start after the reg write is complete. Make sure that the reg
* write is complete using a memory barrier */
mb();
usleep(1);
writel_relaxed(0x0, ldo_bhs_reg_base);
/* Use a memory barrier to make sure the reg write is complete before
* the node is unmapped. */
mb();
of_node_put(ldo_node);
iounmap(ldo_bhs_reg_base);
exit_cpu_node:
of_node_put(cpu_node);
return ret;
}
static int mxs_saif_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct resource *iores;
struct mxs_saif *saif;
int irq, ret = 0;
struct device_node *master;
if (!np)
return -EINVAL;
saif = devm_kzalloc(&pdev->dev, sizeof(*saif), GFP_KERNEL);
if (!saif)
return -ENOMEM;
ret = of_alias_get_id(np, "saif");
if (ret < 0)
return ret;
else
saif->id = ret;
if (saif->id >= ARRAY_SIZE(mxs_saif)) {
dev_err(&pdev->dev, "get wrong saif id\n");
return -EINVAL;
}
/*
* If there is no "fsl,saif-master" phandle, it's a saif
* master. Otherwise, it's a slave and its phandle points
* to the master.
*/
master = of_parse_phandle(np, "fsl,saif-master", 0);
if (!master) {
saif->master_id = saif->id;
} else {
ret = of_alias_get_id(master, "saif");
if (ret < 0)
return ret;
else
saif->master_id = ret;
if (saif->master_id >= ARRAY_SIZE(mxs_saif)) {
dev_err(&pdev->dev, "get wrong master id\n");
return -EINVAL;
}
}
mxs_saif[saif->id] = saif;
saif->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(saif->clk)) {
ret = PTR_ERR(saif->clk);
dev_err(&pdev->dev, "Cannot get the clock: %d\n",
ret);
return ret;
}
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
saif->base = devm_ioremap_resource(&pdev->dev, iores);
if (IS_ERR(saif->base))
return PTR_ERR(saif->base);
irq = platform_get_irq(pdev, 0);
if (irq < 0) {
ret = irq;
dev_err(&pdev->dev, "failed to get irq resource: %d\n",
ret);
return ret;
}
saif->dev = &pdev->dev;
ret = devm_request_irq(&pdev->dev, irq, mxs_saif_irq, 0,
dev_name(&pdev->dev), saif);
if (ret) {
dev_err(&pdev->dev, "failed to request irq\n");
return ret;
}
platform_set_drvdata(pdev, saif);
/* We only support saif0 being tx and clock master */
if (saif->id == 0) {
ret = mxs_saif_mclk_init(pdev);
if (ret)
dev_warn(&pdev->dev, "failed to init clocks\n");
}
ret = devm_snd_soc_register_component(&pdev->dev, &mxs_saif_component,
&mxs_saif_dai, 1);
if (ret) {
dev_err(&pdev->dev, "register DAI failed\n");
return ret;
}
ret = mxs_pcm_platform_register(&pdev->dev);
if (ret) {
dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
return ret;
}
return 0;
}
int msm8976_unclamp_secondary_arm_cpu(unsigned int cpu)
{
int ret = 0;
struct device_node *cpu_node, *acc_node, *l2_node, *l2ccc_node;
void __iomem *reg;
u32 mpidr = cpu_logical_map(cpu);
struct resource res;
int val;
cpu_node = of_get_cpu_node(cpu, NULL);
if (!cpu_node)
return -ENODEV;
acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
if (!acc_node) {
ret = -ENODEV;
goto out_acc;
}
l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);
if (!l2_node) {
ret = -ENODEV;
goto out_l2;
}
l2ccc_node = of_parse_phandle(l2_node, "power-domain", 0);
if (!l2ccc_node) {
ret = -ENODEV;
goto out_l2ccc;
}
/*
* Ensure L2-cache of the CPU is powered on before
* unclamping cpu power rails.
*/
ret = power_on_l2_cache(l2ccc_node, cpu);
if (ret) {
pr_err("L2 cache power up failed for CPU%d\n", cpu);
goto out_acc_reg;
}
reg = of_iomap(acc_node, 0);
if (!reg) {
ret = -ENOMEM;
goto out_acc_reg;
}
if (MPIDR_AFFINITY_LEVEL(mpidr, 1))
msm8976_unclamp_perf_cluster_cpu(reg);
else
msm8976_unclamp_power_cluster_cpu(reg);
/* Secondary CPU-N is now alive.
* Allowing L2 Low power modes
*/
ret = of_address_to_resource(l2ccc_node, 1, &res);
if (ret)
goto out_l2ccc_1;
val = scm_io_read((u32)res.start);
val &= ~BIT(0);
scm_io_write((u32)res.start, val);
out_l2ccc_1:
iounmap(reg);
out_acc_reg:
of_node_put(l2ccc_node);
out_l2ccc:
of_node_put(l2_node);
out_l2:
of_node_put(acc_node);
out_acc:
of_node_put(cpu_node);
return ret;
}
static int anx7808_parse_dt(
struct device *dev, struct anx7808_platform_data *pdata)
{
int rc = 0;
struct device_node *np = dev->of_node;
#ifdef CONFIG_SLIMPORT_DYNAMIC_HPD
struct platform_device *sp_pdev = NULL;
struct device_node *sp_tx_node = NULL;
#endif
pdata->gpio_p_dwn = of_get_named_gpio_flags(
np, "analogix,p-dwn-gpio", 0, NULL);
pdata->gpio_reset = of_get_named_gpio_flags(
np, "analogix,reset-gpio", 0, NULL);
pdata->gpio_int = of_get_named_gpio_flags(
np, "analogix,irq-gpio", 0, NULL);
pdata->gpio_cbl_det = of_get_named_gpio_flags(
np, "analogix,cbl-det-gpio", 0, NULL);
printk(KERN_INFO
"%s gpio p_dwn : %d, reset : %d, irq : %d, gpio_cbl_det %d\n",
LOG_TAG, pdata->gpio_p_dwn,
pdata->gpio_reset,
pdata->gpio_int,
pdata->gpio_cbl_det);
/*
* if "lge,external-ldo-control" property is not exist, we
* assume that it is used in board.
* lgps11 don't use external ldo control,
* please use "lge,external-ldo-control=<0>" in dtsi
*/
rc = of_property_read_u32(np, "lge,external-ldo-control",
&pdata->external_ldo_control);
if (rc == -EINVAL)
pdata->external_ldo_control = 1;
if (pdata->external_ldo_control) {
pdata->gpio_v10_ctrl = of_get_named_gpio_flags(
np, "analogix,v10-ctrl-gpio", 0, NULL);
pdata->gpio_v33_ctrl = of_get_named_gpio_flags(
np, "analogix,v33-ctrl-gpio", 0, NULL);
printk(KERN_INFO "%s gpio_v10_ctrl %d avdd33-en-gpio %d\n",
LOG_TAG, pdata->gpio_v10_ctrl, pdata->gpio_v33_ctrl);
}
#ifdef CONFIG_SLIMPORT_DYNAMIC_HPD
/* parse phandle for hdmi tx */
sp_tx_node = of_parse_phandle(np, "qcom,hdmi-tx-map", 0);
if (!sp_tx_node) {
pr_err("%s %s: can't find hdmi phandle\n", LOG_TAG, __func__);
return -ENODEV;
}
sp_pdev = of_find_device_by_node(sp_tx_node);
if (!sp_pdev) {
pr_err("%s %s: can't find the device by node\n",
LOG_TAG, __func__);
return -ENODEV;
}
pr_info("%s %s : sp_pdev [0X%x] to pdata->pdev\n",
LOG_TAG, __func__, (unsigned int)sp_pdev);
pdata->hdmi_pdev = sp_pdev;
#endif
if (anx7808_regulator_configure(dev, pdata) < 0) {
pr_err("%s %s: parsing dt for anx7808 is failed.\n",
LOG_TAG, __func__);
return rc;
}
/* connects function nodes which are not provided with dts */
pdata->avdd_power = slimport_avdd_power;
pdata->dvdd_power = slimport_dvdd_power;
#ifdef USE_HDMI_SWITCH
hdmi_switch_gpio = of_get_named_gpio_flags(
np, "analogix,hdmi-switch-gpio", 0, NULL);
printk(KERN_INFO "%s hdmi_switch_gpio : %d \n",
LOG_TAG, hdmi_switch_gpio);
#endif
return 0;
}
int msm_unclamp_secondary_arm_cpu(unsigned int cpu)
{
int ret = 0;
struct device_node *cpu_node, *acc_node, *l2_node, *l2ccc_node;
void __iomem *reg;
struct resource res;
int val;
cpu_node = of_get_cpu_node(cpu, NULL);
if (!cpu_node)
return -ENODEV;
acc_node = of_parse_phandle(cpu_node, "qcom,acc", 0);
if (!acc_node) {
ret = -ENODEV;
goto out_acc;
}
l2_node = of_parse_phandle(cpu_node, "next-level-cache", 0);
if (!l2_node) {
ret = -ENODEV;
goto out_l2;
}
l2ccc_node = of_parse_phandle(l2_node, "power-domain", 0);
if (!l2ccc_node) {
ret = -ENODEV;
goto out_l2;
}
/* Ensure L2-cache of the CPU is powered on before
* unclamping cpu power rails.
*/
ret = power_on_l2_cache(l2ccc_node, cpu);
if (ret) {
pr_err("L2 cache power up failed for CPU%d\n", cpu);
goto out_l2ccc;
}
reg = of_iomap(acc_node, 0);
if (!reg) {
ret = -ENOMEM;
goto out_acc_reg;
}
/* Assert Reset on cpu-n */
writel_relaxed(0x00000033, reg + CPU_PWR_CTL);
mb();
/*Program skew to 16 X0 clock cycles*/
writel_relaxed(0x10000001, reg + CPU_PWR_GATE_CTL);
mb();
udelay(2);
/* De-assert coremem clamp */
writel_relaxed(0x00000031, reg + CPU_PWR_CTL);
mb();
/* Close coremem array gdhs */
writel_relaxed(0x00000039, reg + CPU_PWR_CTL);
mb();
udelay(2);
/* De-assert cpu-n clamp */
writel_relaxed(0x00020038, reg + CPU_PWR_CTL);
mb();
udelay(2);
/* De-assert cpu-n reset */
writel_relaxed(0x00020008, reg + CPU_PWR_CTL);
mb();
/* Assert PWRDUP signal on core-n */
writel_relaxed(0x00020088, reg + CPU_PWR_CTL);
mb();
/* Secondary CPU-N is now alive.
* Allowing L2 Low power modes
*/
if (!vctl_parsed)
goto out_l2ccc_1;
else {
ret = of_address_to_resource(l2ccc_node, 1, &res);
if (ret)
goto out_l2ccc_1;
}
val = scm_io_read((u32)res.start);
val &= ~BIT(0);
scm_io_write((u32)res.start, val);
out_l2ccc_1:
iounmap(reg);
out_acc_reg:
of_node_put(l2ccc_node);
out_l2ccc:
of_node_put(l2_node);
out_l2:
of_node_put(acc_node);
out_acc:
of_node_put(cpu_node);
return ret;
}
int dsi_panel_device_register(struct device_node *pan_node,
struct mdss_dsi_ctrl_pdata *ctrl_pdata)
{
struct mipi_panel_info *mipi;
int rc, i, len;
struct device_node *dsi_ctrl_np = NULL;
struct platform_device *ctrl_pdev = NULL;
bool dynamic_fps;
const char *data;
struct mdss_panel_info *pinfo = &(ctrl_pdata->panel_data.panel_info);
mipi = &(pinfo->mipi);
pinfo->type =
((mipi->mode == DSI_VIDEO_MODE)
? MIPI_VIDEO_PANEL : MIPI_CMD_PANEL);
rc = mdss_dsi_clk_div_config(pinfo, mipi->frame_rate);
if (rc) {
pr_err("%s: unable to initialize the clk dividers\n", __func__);
return rc;
}
dsi_ctrl_np = of_parse_phandle(pan_node,
"qcom,mdss-dsi-panel-controller", 0);
if (!dsi_ctrl_np) {
pr_err("%s: Dsi controller node not initialized\n", __func__);
return -EPROBE_DEFER;
}
ctrl_pdev = of_find_device_by_node(dsi_ctrl_np);
rc = mdss_dsi_regulator_init(ctrl_pdev);
if (rc) {
pr_err("%s: failed to init regulator, rc=%d\n",
__func__, rc);
return rc;
}
data = of_get_property(ctrl_pdev->dev.of_node,
"qcom,platform-strength-ctrl", &len);
if ((!data) || (len != 2)) {
pr_err("%s:%d, Unable to read Phy Strength ctrl settings",
__func__, __LINE__);
return -EINVAL;
}
pinfo->mipi.dsi_phy_db.strength[0] = data[0];
pinfo->mipi.dsi_phy_db.strength[1] = data[1];
data = of_get_property(ctrl_pdev->dev.of_node,
"qcom,platform-regulator-settings", &len);
if ((!data) || (len != 7)) {
pr_err("%s:%d, Unable to read Phy regulator settings",
__func__, __LINE__);
return -EINVAL;
}
for (i = 0; i < len; i++) {
pinfo->mipi.dsi_phy_db.regulator[i]
= data[i];
}
data = of_get_property(ctrl_pdev->dev.of_node,
"qcom,platform-bist-ctrl", &len);
if ((!data) || (len != 6)) {
pr_err("%s:%d, Unable to read Phy Bist Ctrl settings",
__func__, __LINE__);
return -EINVAL;
}
for (i = 0; i < len; i++) {
pinfo->mipi.dsi_phy_db.bistctrl[i]
= data[i];
}
data = of_get_property(ctrl_pdev->dev.of_node,
"qcom,platform-lane-config", &len);
if ((!data) || (len != 45)) {
pr_err("%s:%d, Unable to read Phy lane configure settings",
__func__, __LINE__);
return -EINVAL;
}
for (i = 0; i < len; i++) {
pinfo->mipi.dsi_phy_db.lanecfg[i] =
data[i];
}
ctrl_pdata->shared_pdata.broadcast_enable = of_property_read_bool(
pan_node, "qcom,mdss-dsi-panel-broadcast-mode");
dynamic_fps = of_property_read_bool(pan_node,
"qcom,mdss-dsi-pan-enable-dynamic-fps");
if (dynamic_fps) {
pinfo->dynamic_fps = true;
data = of_get_property(pan_node,
"qcom,mdss-dsi-pan-fps-update", NULL);
if (data) {
if (!strcmp(data, "dfps_suspend_resume_mode")) {
pinfo->dfps_update =
DFPS_SUSPEND_RESUME_MODE;
pr_debug("%s: dfps mode: suspend/resume\n",
__func__);
} else if (!strcmp(data,
"dfps_immediate_clk_mode")) {
pinfo->dfps_update =
DFPS_IMMEDIATE_CLK_UPDATE_MODE;
pr_debug("%s: dfps mode: Immediate clk\n",
__func__);
} else {
pr_debug("%s: dfps to default mode\n",
__func__);
pinfo->dfps_update =
DFPS_SUSPEND_RESUME_MODE;
pr_debug("%s: dfps mode: suspend/resume\n",
__func__);
}
} else {
pr_debug("%s: dfps update mode not configured\n",
__func__);
pinfo->dynamic_fps =
false;
pr_debug("%s: dynamic FPS disabled\n",
__func__);
}
pinfo->new_fps = pinfo->mipi.frame_rate;
}
ctrl_pdata->disp_en_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,
"qcom,platform-enable-gpio", 0);
if (!gpio_is_valid(ctrl_pdata->disp_en_gpio)) {
pr_err("%s:%d, Disp_en gpio not specified\n",
__func__, __LINE__);
} else {
rc = gpio_request(ctrl_pdata->disp_en_gpio, "disp_enable");
if (rc) {
pr_err("request reset gpio failed, rc=%d\n",
rc);
gpio_free(ctrl_pdata->disp_en_gpio);
return -ENODEV;
}
}
if (pinfo->type == MIPI_CMD_PANEL) {
ctrl_pdata->disp_te_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,
"qcom,platform-te-gpio", 0);
if (!gpio_is_valid(ctrl_pdata->disp_te_gpio)) {
pr_err("%s:%d, Disp_te gpio not specified\n",
__func__, __LINE__);
}
}
if (gpio_is_valid(ctrl_pdata->disp_te_gpio) &&
pinfo->type == MIPI_CMD_PANEL) {
rc = gpio_request(ctrl_pdata->disp_te_gpio, "disp_te");
if (rc) {
pr_err("request TE gpio failed, rc=%d\n",
rc);
gpio_free(ctrl_pdata->disp_te_gpio);
return -ENODEV;
}
rc = gpio_tlmm_config(GPIO_CFG(
ctrl_pdata->disp_te_gpio, 1,
GPIO_CFG_INPUT,
GPIO_CFG_PULL_DOWN,
GPIO_CFG_2MA),
GPIO_CFG_ENABLE);
if (rc) {
pr_err("%s: unable to config tlmm = %d\n",
__func__, ctrl_pdata->disp_te_gpio);
gpio_free(ctrl_pdata->disp_te_gpio);
return -ENODEV;
}
rc = gpio_direction_input(ctrl_pdata->disp_te_gpio);
if (rc) {
pr_err("set_direction for disp_en gpio failed, rc=%d\n",
rc);
gpio_free(ctrl_pdata->disp_te_gpio);
return -ENODEV;
}
pr_debug("%s: te_gpio=%d\n", __func__,
ctrl_pdata->disp_te_gpio);
}
ctrl_pdata->rst_gpio = of_get_named_gpio(ctrl_pdev->dev.of_node,
"qcom,platform-reset-gpio", 0);
if (!gpio_is_valid(ctrl_pdata->rst_gpio)) {
pr_err("%s:%d, reset gpio not specified\n",
__func__, __LINE__);
} else {
rc = gpio_request(ctrl_pdata->rst_gpio, "disp_rst_n");
if (rc) {
pr_err("request reset gpio failed, rc=%d\n",
rc);
gpio_free(ctrl_pdata->rst_gpio);
if (gpio_is_valid(ctrl_pdata->disp_en_gpio))
gpio_free(ctrl_pdata->disp_en_gpio);
return -ENODEV;
}
}
if (pinfo->mode_gpio_state != MODE_GPIO_NOT_VALID) {
ctrl_pdata->mode_gpio = of_get_named_gpio(
ctrl_pdev->dev.of_node,
"qcom,platform-mode-gpio", 0);
if (!gpio_is_valid(ctrl_pdata->mode_gpio)) {
pr_info("%s:%d, mode gpio not specified\n",
__func__, __LINE__);
} else {
rc = gpio_request(ctrl_pdata->mode_gpio, "panel_mode");
if (rc) {
pr_err("request panel mode gpio failed,rc=%d\n",
rc);
gpio_free(ctrl_pdata->mode_gpio);
if (gpio_is_valid(ctrl_pdata->disp_en_gpio))
gpio_free(ctrl_pdata->disp_en_gpio);
if (gpio_is_valid(ctrl_pdata->rst_gpio))
gpio_free(ctrl_pdata->rst_gpio);
if (gpio_is_valid(ctrl_pdata->disp_te_gpio))
gpio_free(ctrl_pdata->disp_te_gpio);
return -ENODEV;
}
}
}
if (mdss_dsi_clk_init(ctrl_pdev, ctrl_pdata)) {
pr_err("%s: unable to initialize Dsi ctrl clks\n", __func__);
return -EPERM;
}
if (mdss_dsi_retrieve_ctrl_resources(ctrl_pdev,
pinfo->pdest,
ctrl_pdata)) {
pr_err("%s: unable to get Dsi controller res\n", __func__);
return -EPERM;
}
ctrl_pdata->panel_data.event_handler = mdss_dsi_event_handler;
if (ctrl_pdata->bklt_ctrl == BL_PWM)
mdss_dsi_panel_pwm_cfg(ctrl_pdata);
mdss_dsi_ctrl_init(ctrl_pdata);
/*
* register in mdp driver
*/
ctrl_pdata->pclk_rate = mipi->dsi_pclk_rate;
ctrl_pdata->byte_clk_rate = pinfo->clk_rate / 8;
pr_debug("%s: pclk=%d, bclk=%d\n", __func__,
ctrl_pdata->pclk_rate, ctrl_pdata->byte_clk_rate);
ctrl_pdata->ctrl_state = CTRL_STATE_UNKNOWN;
if (pinfo->cont_splash_enabled) {
pinfo->panel_power_on = 1;
rc = mdss_dsi_panel_power_on(&(ctrl_pdata->panel_data), 1);
if (rc) {
pr_err("%s: Panel power on failed\n", __func__);
return rc;
}
mdss_dsi_clk_ctrl(ctrl_pdata, 1);
ctrl_pdata->ctrl_state |=
(CTRL_STATE_PANEL_INIT | CTRL_STATE_MDP_ACTIVE);
} else {
pinfo->panel_power_on = 0;
}
rc = mdss_register_panel(ctrl_pdev, &(ctrl_pdata->panel_data));
if (rc) {
pr_err("%s: unable to register MIPI DSI panel\n", __func__);
if (ctrl_pdata->rst_gpio)
gpio_free(ctrl_pdata->rst_gpio);
if (gpio_is_valid(ctrl_pdata->disp_en_gpio))
gpio_free(ctrl_pdata->disp_en_gpio);
return rc;
}
if (pinfo->pdest == DISPLAY_1) {
mdss_debug_register_base("dsi0",
ctrl_pdata->ctrl_base, ctrl_pdata->reg_size);
ctrl_pdata->ndx = 0;
} else {
mdss_debug_register_base("dsi1",
ctrl_pdata->ctrl_base, ctrl_pdata->reg_size);
ctrl_pdata->ndx = 1;
}
pr_debug("%s: Panel data initialized\n", __func__);
return 0;
}
static int mt2701_cs42448_machine_probe(struct platform_device *pdev)
{
struct snd_soc_card *card = &mt2701_cs42448_soc_card;
int ret;
int i;
struct device_node *platform_node, *codec_node, *codec_node_bt_mrg;
struct mt2701_cs42448_private *priv =
devm_kzalloc(&pdev->dev, sizeof(struct mt2701_cs42448_private),
GFP_KERNEL);
struct device *dev = &pdev->dev;
if (!priv)
return -ENOMEM;
platform_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,platform", 0);
if (!platform_node) {
dev_err(&pdev->dev, "Property 'platform' missing or invalid\n");
return -EINVAL;
}
for (i = 0; i < card->num_links; i++) {
if (mt2701_cs42448_dai_links[i].platform_name)
continue;
mt2701_cs42448_dai_links[i].platform_of_node = platform_node;
}
card->dev = dev;
codec_node = of_parse_phandle(pdev->dev.of_node,
"mediatek,audio-codec", 0);
if (!codec_node) {
dev_err(&pdev->dev,
"Property 'audio-codec' missing or invalid\n");
return -EINVAL;
}
for (i = 0; i < card->num_links; i++) {
if (mt2701_cs42448_dai_links[i].codec_name)
continue;
mt2701_cs42448_dai_links[i].codec_of_node = codec_node;
}
codec_node_bt_mrg = of_parse_phandle(pdev->dev.of_node,
"mediatek,audio-codec-bt-mrg", 0);
if (!codec_node_bt_mrg) {
dev_err(&pdev->dev,
"Property 'audio-codec-bt-mrg' missing or invalid\n");
return -EINVAL;
}
mt2701_cs42448_dai_links[DAI_LINK_BE_MRG_BT].codec_of_node
= codec_node_bt_mrg;
ret = snd_soc_of_parse_audio_routing(card, "audio-routing");
if (ret) {
dev_err(&pdev->dev, "failed to parse audio-routing: %d\n", ret);
return ret;
}
priv->i2s1_in_mux_gpio_sel_1 =
of_get_named_gpio(dev->of_node, "i2s1-in-sel-gpio1", 0);
if (gpio_is_valid(priv->i2s1_in_mux_gpio_sel_1)) {
ret = devm_gpio_request(dev, priv->i2s1_in_mux_gpio_sel_1,
"i2s1_in_mux_gpio_sel_1");
if (ret)
dev_warn(&pdev->dev, "%s devm_gpio_request fail %d\n",
__func__, ret);
gpio_direction_output(priv->i2s1_in_mux_gpio_sel_1, 0);
}
priv->i2s1_in_mux_gpio_sel_2 =
of_get_named_gpio(dev->of_node, "i2s1-in-sel-gpio2", 0);
if (gpio_is_valid(priv->i2s1_in_mux_gpio_sel_2)) {
ret = devm_gpio_request(dev, priv->i2s1_in_mux_gpio_sel_2,
"i2s1_in_mux_gpio_sel_2");
if (ret)
dev_warn(&pdev->dev, "%s devm_gpio_request fail2 %d\n",
__func__, ret);
gpio_direction_output(priv->i2s1_in_mux_gpio_sel_2, 0);
}
snd_soc_card_set_drvdata(card, priv);
ret = devm_snd_soc_register_card(&pdev->dev, card);
if (ret)
dev_err(&pdev->dev, "%s snd_soc_register_card fail %d\n",
__func__, ret);
return ret;
}
