long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param)
{
// Supported main clock sources: PCL_MC_RC120M
// Supported synchronous clocks frequencies if RC120M is the main clock source:
// 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.
// NOTE: by default, this implementation doesn't perform thorough checks on the
// input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
#ifdef AVR32SFW_INPUT_CHECK
// Verify that fCPU >= fPBx
if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
return(-1);
#endif
#ifdef AVR32SFW_INPUT_CHECK
// Verify that the target frequencies are reachable.
if((param->cpu_f > SCIF_RC120M_FREQ_HZ) || (param->pba_f > SCIF_RC120M_FREQ_HZ)
|| (param->pbb_f > SCIF_RC120M_FREQ_HZ))
return(-1);
#endif
// Start the 120MHz internal RCosc (RC120M) clock
scif_start_rc120M();
return(pcl_configure_synchronous_clocks(PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, param));
}
void demo_init_pwma(void)
{
// Enable the pins driving the LEDs with the PWMA function (functionality E).
gpio_enable_module_pin(LED0_GPIO, LED0_PWM_FUNCTION);
gpio_enable_module_pin(LED1_GPIO, LED1_PWM_FUNCTION);
gpio_enable_module_pin(LED2_GPIO, LED2_PWM_FUNCTION);
gpio_enable_module_pin(LED3_GPIO, LED3_PWM_FUNCTION);
//#
//# Setup and enable the "PWMA and GCLK3 pin" generic clock to 120MHz
//#
// Start the RC120M clock
scif_start_rc120M();
// Setup the generic clock at 120MHz
scif_gc_setup( AVR32_PM_GCLK_PWMA, // The generic clock to setup
SCIF_GCCTRL_RC120M, // The input clock source to use for the generic clock
false, // Disable the generic clock divisor
0); // divfactor = DFLL0freq/gclkfreq
// Enable the generic clock
scif_gc_enable(AVR32_PM_GCLK_PWMA);
//#
//# Enable all the PWMAs to output to all LEDs. LEDs are default turned on by
//# setting PWM duty cycles to 0.
//#
pwma_config_enable(&AVR32_PWMA,PWMA_OUTPUT_FREQUENCY,PWMA_GCLK_FREQUENCY,0);
pwma_set_channels_value(&AVR32_PWMA,LED_PWMA_CHANNELS_MASK,PWMA_DUTY_CYCLE_INIT_VAL);
}
/* \brief Start RC120M, switch main clock to RC120M.
*/
static void local_set_main_clock_to_rc120m(void)
{
// Start the 120MHz internal RCosc (RC120M) clock
scif_start_rc120M();
#if UC3D
// Set one wait-state (WS) for flash controller. 0 WS access is up to 30MHz for HSB/CPU clock.
// As we want to have 48MHz on HSB/CPU clock, we need to set 1 WS on flash controller.
flashcdw_set_wait_state(1);
#else
// Since our target is to set the CPU&HSB frequency domains to 30MHz, set the
// appropriate wait-state and speed read mode on the flash controller.
flashcdw_set_flash_waitstate_and_readmode(EXAMPLE_CPUCLK_HZ);
#endif
// Set the CPU clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_4);
// Set the PBA clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_4);
// Set the PBB clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_4);
// Set the main clock source to be the RC120M.
pm_set_mclk_source(PM_CLK_SRC_RC120M);
}
void board_init(void)
{
/* This function is meant to contain board-specific initialization code
* for, e.g., the I/O pins. The initialization can rely on application-
* specific board configuration, found in conf_board.h.
*/
scif_start_rc120M();
scif_start_rc8M();
//enable brownout detection
scif_bod50_enable_irq(); //4.something volts
//set cpu divide by 2^(1+1) = 4
pm_set_clk_domain_div(AVR32_PM_CLK_GRP_CPU,1);
//switch main clock source
pm_set_mclk_source(PM_CLK_SRC_RC120M);
//cpu frequency is now 30 MHz
//set up pba, pbb, pbc. must be less than fcpu/4
//cpu is divide by 4 --> need divide by 16. 2^(3+1) = 16
pm_set_clk_domain_div(AVR32_PM_CLK_GRP_PBA,3);
pm_set_clk_domain_div(AVR32_PM_CLK_GRP_PBB,3);
pm_set_clk_domain_div(AVR32_PM_CLK_GRP_PBB,3);
//120MHz / 16 = 7.5MHz
//setup adc
ADCInit();
//setup millis()
millis_init();
//set up pwm
PWMInit();
//setup usart
USARTInit();
// CANInit();
}
/**
* \brief Detects extern OSC frequency and initialize system clocks on it
*/
void sysclk_auto_init(void)
{
int mul;
// Switch to OSC ISP
// Set max startup time to make sure any crystal will be supported
// We cannot use a TC to measure this OSC frequency
// because the master clock must be faster than the clock selected by the TC
// Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
// Replace "scif_configure_osc_crystalmode(SCIF_OSC0, 16000000)" by
// inline routine to safe code (160B)
{
u_avr32_scif_oscctrl0_t u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0};
// Modify : Configure the oscillator mode to crystal and set the gain according to the
// crystal frequency.
u_avr32_scif_oscctrl0.OSCCTRL0.mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
u_avr32_scif_oscctrl0.OSCCTRL0.gain =
(16000000 < 900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 :
(16000000 < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 :
(16000000 < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 :
AVR32_SCIF_OSCCTRL0_GAIN_G3;
AVR32_ENTER_CRITICAL_REGION( );
// Unlock the write-protected OSCCTRL0 register
SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
// Write Back
AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0;
AVR32_LEAVE_CRITICAL_REGION( );
}
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC, true);
pm_set_mclk_source(PM_CLK_SRC_OSC0);
// Initialize the AST with the internal RC oscillator
// AST will count at the frequency of 115KHz/2
if (!ast_init_counter(&AVR32_AST, AST_OSC_RC, 0, 0)) {
while (1);
}
// Enable the AST
ast_enable(&AVR32_AST);
// Detect the frequency
switch (freq_detect_start()) {
case 8000000:
mul = 11;
break;
case 16000000:
mul = 5;
break;
case 12000000:
default:
mul = 7;
break;
}
scif_pll_opt_t opt;
// Set PLL0 VCO @ 96 MHz
// Set PLL0 @ 48 MHz
opt.osc = SCIF_OSC0;
opt.lockcount = 63;
opt.div = 1;
opt.mul = mul;
opt.pll_div2 = 1;
opt.pll_wbwdisable = 0;
opt.pll_freq = 1;
// lockcount in main clock for the PLL wait lock
scif_pll0_setup((const scif_pll_opt_t *)&opt);
/* Enable PLL0 */
scif_pll0_enable();
/* Wait for PLL0 locked */
scif_wait_for_pll0_locked();
// Configure and start the RC120Mhz internal oscillator.
scif_start_rc120M();
// Since our target is to set the CPU&HSB frequency domains to 30MHz, we must
// set one wait-state and enable the High-speed read mode on the flash controller.
flashcdw_set_flash_waitstate_and_readmode(30000000UL);
// Set the CPU clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_4);
// Set the PBA clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_4);
// Set the PBB clock domain to 30MHz (by applying a division ratio = 4).
pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_4);
// Set the main clock source to be DFLL0.
pm_set_mclk_source(PM_CLK_SRC_RC120M);
}