void sr_init(){ SR_PORT &= ~((1<<SR_DATA_IN) | (1<<SR_DATA_CLK) | (1<<SR_LATCH_CLK)); SR_DDR |= (1<<SR_DATA_IN) | (1<<SR_OUTPUT_EN) | (1<<SR_DATA_CLK) | (1<<SR_LATCH_CLK); sr_clear(); sr_set_state(SR_ENABLE); }
StorageRegister::StorageRegister() { sr_clear(); _load(); }