Ejemplo n.º 1
0
Archivo: trap.c Proyecto: cky9301/6.828
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.
        // TODO: chky
        int i;
        extern uint32_t handlers[];
        extern void handler48();
        
        extern uint32_t irq_handlers[];
        
        //FIXME: istrap, sel, off, dpl
        for (i = 0; i <= T_SIMDERR; i++) {
          SETGATE(idt[i], 0, GD_KT, handlers[i], (i==T_BRKPT)? 3:0);
        }
        SETGATE(idt[T_SYSCALL], 0, GD_KT, handler48, 3);
        
        // LAB 4: chky, set IRQ handlers
        for (i = 0; i <= 15; i++) {
          SETGATE(idt[IRQ_OFFSET+i], 0, GD_KT, irq_handlers[i], 3);
        }

	// Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 2
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// Ashish
	SETGATE(idt[T_DIVIDE], 0, GD_KT, divide_error_handler, 3);
	SETGATE(idt[T_DEBUG], 0, GD_KT, debug_exception_handler, 3);
	SETGATE(idt[T_NMI], 0, GD_KT, non_maskable_interrupt_handler, 3);
	SETGATE(idt[T_BRKPT], 0, GD_KT, breakpoint_handler, 3);
	SETGATE(idt[T_OFLOW], 0, GD_KT, overflow_handler, 3);
	SETGATE(idt[T_BOUND], 0, GD_KT, bounds_check_handler, 3);
	SETGATE(idt[T_ILLOP], 0, GD_KT, illegal_opcode_handler, 3);
	SETGATE(idt[T_DEVICE], 0, GD_KT, device_no_available_handler, 3);
	SETGATE(idt[T_DBLFLT], 0, GD_KT, double_fault_handler, 3);
	SETGATE(idt[T_TSS], 0, GD_KT, invalid_tss_handler, 3);
	SETGATE(idt[T_SEGNP], 0, GD_KT, segment_not_present_handler, 3);
	SETGATE(idt[T_STACK], 0, GD_KT, stack_exception_handler, 3);
	SETGATE(idt[T_GPFLT], 0, GD_KT, general_protection_fault_handler, 3);
	SETGATE(idt[T_PGFLT], 0, GD_KT, page_fault_handler_1, 0);
	SETGATE(idt[T_FPERR], 0, GD_KT, floating_point_error_handler, 3);
	SETGATE(idt[T_ALIGN], 0, GD_KT, allign_check_handler, 3);
	SETGATE(idt[T_MCHK], 0, GD_KT, machine_check_handler, 3);
	SETGATE(idt[T_SIMDERR], 0, GD_KT, SIMD_floating_point_error_handler, 3);
	SETGATE(idt[T_SYSCALL], 0, GD_KT, system_call_handler, 3); //Diable interrupts if an env is in middle of a syscall.
	SETGATE(idt[IRQ_TIMER+IRQ_OFFSET], 0, GD_KT, irq_timer_handler, 0);
	SETGATE(idt[IRQ_KBD+IRQ_OFFSET], 0, GD_KT, irq_kbd_handler, 0);
	SETGATE(idt[IRQ_SERIAL+IRQ_OFFSET], 0, GD_KT, irq_serial_handler, 0);
	SETGATE(idt[IRQ_SPURIOUS+IRQ_OFFSET], 0, GD_KT, irq_spurious_handler, 0);
	SETGATE(idt[IRQ_IDE+IRQ_OFFSET], 0, GD_KT, irq_ide_handler, 0);
    idt_pd.pd_lim = sizeof(idt)-1;
    idt_pd.pd_base = (uint64_t)idt;
	// Per-CPU setup
	trap_init_percpu();
}
Ejemplo n.º 3
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];
/*	extern void trap_handler0();
	extern void trap_handler1();
	extern void trap_handler2();
	extern void trap_handler3();
	extern void trap_handler4();
	extern void trap_handler6();
	extern void trap_handler7();
	extern void trap_handler8();
	extern void trap_handler9();
	extern void trap_handler10();
	extern void trap_handler11();
	extern void trap_handler12();
	extern void trap_handler13();
	extern void trap_handler14();
	extern void trap_handler16();
	extern void trap_handler17();
	extern void trap_handler18();
	extern void trap_handler19();*/
	// LAB 3: Your code here.
	/*
	SETGATE(idt[0], 0, GD_KT, trap_handler0, 0); 
	SETGATE(idt[1], 0, GD_KT, trap_handler1, 0); 
	SETGATE(idt[2], 0, GD_KT, trap_handler2, 0); 
	SETGATE(idt[3], 0, GD_KT, trap_handler3, 0); 
	SETGATE(idt[4], 0, GD_KT, trap_handler4, 0); 

	SETGATE(idt[6], 0, GD_KT, trap_handler6, 0); 
	SETGATE(idt[7], 0, GD_KT, trap_handler7, 0); 
	SETGATE(idt[8], 0, GD_KT, trap_handler8, 0); 
	SETGATE(idt[10], 0, GD_KT, trap_handler10, 0);
	SETGATE(idt[11], 0, GD_KT, trap_handler11, 0); 
	SETGATE(idt[12], 0, GD_KT, trap_handler12, 0); 
	SETGATE(idt[13], 0, GD_KT, trap_handler13, 0); 
	SETGATE(idt[14], 0, GD_KT, trap_handler14, 0); 

	SETGATE(idt[16], 0, GD_KT, trap_handler16, 0); 
	SETGATE(idt[17], 0, GD_KT, trap_handler17, 0); 
	SETGATE(idt[18], 0, GD_KT, trap_handler18, 0); 
	SETGATE(idt[19], 0, GD_KT, trap_handler19, 0); 
	*/
	extern uint32_t vectors[];
	extern void trap_handler48();
	int i;
	for (i = 0; i < 20; i++) {
		if (i == T_BRKPT) {

			SETGATE(idt[i], 0, GD_KT, vectors[i], 3);
		} else {
			SETGATE(idt[i], 0, GD_KT, vectors[i], 0);
		}
	}

	SETGATE(idt[48], 0, GD_KT, trap_handler48, 3);
	// Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 4
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];
	
	// LAB 3: Your code here.
	SETGATE(idt[T_DIVIDE], 0, GD_KT, t_divide, 0);
	SETGATE(idt[T_DEBUG], 0, GD_KT, t_debug, 0);
	SETGATE(idt[T_NMI], 0, GD_KT, t_nmi, 0);
	SETGATE(idt[T_BRKPT], 0, GD_KT, t_brkpt, 3);
	SETGATE(idt[T_OFLOW], 0, GD_KT, t_oflow, 0);
	SETGATE(idt[T_BOUND], 0, GD_KT, t_bound, 0);
	SETGATE(idt[T_ILLOP], 0, GD_KT, t_illop, 0);
	SETGATE(idt[T_DEVICE], 0, GD_KT, t_device, 0);
	SETGATE(idt[T_DBLFLT], 0, GD_KT, t_dblflt, 0);
	SETGATE(idt[T_TSS], 0, GD_KT, t_tss, 0);
	SETGATE(idt[T_SEGNP], 0, GD_KT, t_segnp, 0);
	SETGATE(idt[T_STACK], 0, GD_KT, t_stack, 0);
	SETGATE(idt[T_GPFLT], 0, GD_KT, t_gpflt, 0);
	SETGATE(idt[T_PGFLT], 0, GD_KT, t_pgflt, 0);
	SETGATE(idt[T_FPERR], 0, GD_KT, t_fperr, 0);
	SETGATE(idt[T_ALIGN], 0, GD_KT, t_align, 0);
	SETGATE(idt[T_MCHK], 0, GD_KT, t_mchk, 0);
	SETGATE(idt[T_SIMDERR], 0, GD_KT, t_simderr, 0);
	SETGATE(idt[T_SYSCALL], 0, GD_KT, t_syscall, 3);
	// Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 5
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	cprintf("%d %x\n", idt_pd.pd_lim, idt_pd.pd_base);
	// LAB 3: Your code here.
	SETGATE(idt[T_DIVIDE], 0, GD_KT, &route_divide_error, 0);
	SETGATE(idt[T_DEBUG], 0, GD_KT, &route_debug_exception, 0);
	SETGATE(idt[T_NMI], 0, GD_KT, &route_nmi_interrupt, 0);
	SETGATE(idt[T_BRKPT], 0, GD_KT, &route_breakpoint, 3);
	SETGATE(idt[T_OFLOW], 0, GD_KT, &route_overflow, 0);
	SETGATE(idt[T_BOUND], 0, GD_KT, &route_bound_check, 0);
	SETGATE(idt[T_ILLOP], 0, GD_KT, &route_illegal_opcode, 0);
	SETGATE(idt[T_DEVICE], 0, GD_KT, &route_device_notavailable, 0);
	SETGATE(idt[T_DBLFLT], 0, GD_KT, &route_double_fault, 0);
	SETGATE(idt[T_TSS], 0, GD_KT, &route_invalid_tss, 0);
	SETGATE(idt[T_SEGNP], 0, GD_KT, &route_segment_fault, 0);
	SETGATE(idt[T_STACK], 0, GD_KT, &route_stack_exception, 0);
	SETGATE(idt[T_GPFLT], 0, GD_KT, &route_general_protection, 0);
	SETGATE(idt[T_PGFLT], 0, GD_KT, &route_page_fault, 0);
	SETGATE(idt[T_FPERR], 0, GD_KT, &route_floating_point_error, 0);
	SETGATE(idt[T_ALIGN], 0, GD_KT, &route_alignment_check, 0);
	SETGATE(idt[T_MCHK], 0, GD_KT, &route_machine_check, 0);
	SETGATE(idt[T_SIMDERR], 0, GD_KT, &route_simd_floating_point_error, 0);

	SETGATE(idt[T_SYSCALL], 0, GD_KT, &route_system_call, 3);
	//cprintf("KSTACKTOP:%x\n", KSTACKTOP);
	// Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 6
0
// Setup code for APs
void
mp_main(void)
{
	// We are in high EIP now, safe to switch to kern_pgdir 
	lcr3(PADDR(kern_pgdir));
	cprintf("SMP: CPU %d starting\n", cpunum());

	lapic_init();
	env_init_percpu();
	trap_init_percpu();
	xchg(&thiscpu->cpu_status, CPU_STARTED); // tell boot_aps() we're up

#ifdef USE_TICKET_SPIN_LOCK
	spinlock_test();
#endif

	// Now that we have finished some basic setup, call sched_yield()
	// to start running processes on this CPU.  But make sure that
	// only one CPU can enter the scheduler at a time!
	//
	// Your code here:
	lock_kernel();
	sched_yield();
	// Remove this after you finish Exercise 4
	//for (;;);
}
Ejemplo n.º 7
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.

	// Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 8
0
Archivo: trap.c Proyecto: ouyangjn/joos
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.
        cprintf("JOOS: trap_init not implement yet\n");

	// Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 9
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.
	SETGATE(idt[T_DIVIDE], 0, GD_KT, _divide_error, 0);
	SETGATE(idt[T_DEBUG], 0, GD_KT, _debug, 0);
	SETGATE(idt[T_NMI], 0, GD_KT, _non_maskable_interrupt, 0);
	SETGATE(idt[T_BRKPT], 0, GD_KT, _breakpoint, 3);
	SETGATE(idt[T_OFLOW], 0, GD_KT, _overflow, 0);
	SETGATE(idt[T_BOUND], 0, GD_KT, _bound_range_exceeded, 0);
	SETGATE(idt[T_ILLOP], 0, GD_KT, _invalid_opcode, 0);
	SETGATE(idt[T_DEVICE], 0, GD_KT, _device_not_available, 0);
	SETGATE(idt[T_DBLFLT], 0, GD_KT, _double_fault, 0);

	SETGATE(idt[T_TSS], 0, GD_KT, _invalid_tss, 0);
	SETGATE(idt[T_SEGNP], 0, GD_KT, _segment_not_present, 0);
	SETGATE(idt[T_STACK], 0, GD_KT, _stack_fault, 0);
	SETGATE(idt[T_GPFLT], 0, GD_KT, _general_protection, 0);
	SETGATE(idt[T_PGFLT], 0, GD_KT, _page_fault, 0);

	SETGATE(idt[T_FPERR], 0, GD_KT, _x87_fpu_error, 0);
	SETGATE(idt[T_ALIGN], 0, GD_KT, _alignment_check, 0);
	SETGATE(idt[T_MCHK], 0, GD_KT, _machine_check, 0);
	SETGATE(idt[T_SIMDERR], 0, GD_KT, _simd_fp_exception, 0);
	SETGATE(idt[T_SYSCALL], 0, GD_KT, syscall, 3);

	SETGATE(idt[IRQ_OFFSET + 0], 0, GD_KT, _irq0, 0);
	SETGATE(idt[IRQ_OFFSET + 1], 0, GD_KT, _irq1, 0);
	SETGATE(idt[IRQ_OFFSET + 2], 0, GD_KT, _irq2, 0);
	SETGATE(idt[IRQ_OFFSET + 3], 0, GD_KT, _irq3, 0);
	SETGATE(idt[IRQ_OFFSET + 4], 0, GD_KT, _irq4, 0);
	SETGATE(idt[IRQ_OFFSET + 5], 0, GD_KT, _irq5, 0);
	SETGATE(idt[IRQ_OFFSET + 6], 0, GD_KT, _irq6, 0);
	SETGATE(idt[IRQ_OFFSET + 7], 0, GD_KT, _irq7, 0);
	SETGATE(idt[IRQ_OFFSET + 8], 0, GD_KT, _irq8, 0);
	SETGATE(idt[IRQ_OFFSET + 9], 0, GD_KT, _irq9, 0);
	SETGATE(idt[IRQ_OFFSET + 10], 0, GD_KT, _irq10, 0);
	SETGATE(idt[IRQ_OFFSET + 11], 0, GD_KT, _irq11, 0);
	SETGATE(idt[IRQ_OFFSET + 12], 0, GD_KT, _irq12, 0);
	SETGATE(idt[IRQ_OFFSET + 13], 0, GD_KT, _irq13, 0);
	SETGATE(idt[IRQ_OFFSET + 14], 0, GD_KT, _irq14, 0);
	SETGATE(idt[IRQ_OFFSET + 15], 0, GD_KT, _irq15, 0);

	extern void sysenter_handler();
	wrmsr(0x174, GD_KT, 0);
	wrmsr(0x175, KSTACKTOP, 0);
	wrmsr(0x176, sysenter_handler, 0);

	// Per-CPU setup
	trap_init_percpu();
}
Ejemplo n.º 10
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.
	// void th0();
	// void th1();
	// void th3();
	// void th4();
	// void th5();
	// void th6();
	// void th7();
	// void th8();
	// void th9();
	// void th10();
	// void th11();
	// void th12();
	// void th13();
	// void th14();
	// void th16();
	// SETGATE(idt[0], 0, GD_KT, th0, 0);
	// SETGATE(idt[1], 0, GD_KT, th1, 0);
	// SETGATE(idt[3], 0, GD_KT, th3, 0);
	// SETGATE(idt[4], 0, GD_KT, th4, 0);
	// SETGATE(idt[5], 0, GD_KT, th5, 0);
	// SETGATE(idt[6], 0, GD_KT, th6, 0);
	// SETGATE(idt[7], 0, GD_KT, th7, 0);
	// SETGATE(idt[8], 0, GD_KT, th8, 0);
	// SETGATE(idt[9], 0, GD_KT, th9, 0);
	// SETGATE(idt[10], 0, GD_KT, th10, 0);
	// SETGATE(idt[11], 0, GD_KT, th11, 0);
	// SETGATE(idt[12], 0, GD_KT, th12, 0);
	// SETGATE(idt[13], 0, GD_KT, th13, 0);
	// SETGATE(idt[14], 0, GD_KT, th14, 0);
	// SETGATE(idt[16], 0, GD_KT, th16, 0);

	// Challenge:
	extern void (*funs[])();
	cprintf("funs %x\n", funs);
	cprintf("funs[0] %x\n", funs[0]);
	cprintf("funs[48] %x\n", funs[48]);
	int i;
	for (i = 0; i <= 16; ++i)
		if (i==T_BRKPT)
			SETGATE(idt[i], 0, GD_KT, funs[i], 3)
		else if (i!=2 && i!=15) {
			SETGATE(idt[i], 0, GD_KT, funs[i], 0);
		}
	SETGATE(idt[48], 0, GD_KT, funs[48], 3);
	// Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 11
0
void trap_init()
{
	int i;
	extern uint32_t trap_handlers[];

	for(i = 0;i < 256; i++) {
		setgate(idt[i], 0, _KERNEL_CS_, trap_handlers[i], 0);
	}
	
	setgate(idt[T_SYSCALL], 0, _KERNEL_CS_, trap_handlers[T_SYSCALL], 3);

	trap_init_percpu();
}
Ejemplo n.º 12
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.
    SETGATE(idt[T_DIVIDE], 0, GD_KT, XTRPX_divzero, 0);  
    SETGATE(idt[T_DEBUG], 0, GD_KT, XTRPX_Debug, 0);  
    SETGATE(idt[T_NMI], 0, GD_KT, XTRPX_NonMaskI, 0);  
    SETGATE(idt[T_BRKPT], 0, GD_KT, XTRPX_Brkpt, 3);  
    SETGATE(idt[T_OFLOW], 0, GD_KT, XTRPX_OFlow, 0);  
    SETGATE(idt[T_BOUND], 0, GD_KT, XTRPX_Bound, 0);  
    SETGATE(idt[T_ILLOP], 0, GD_KT, XTRPX_Illop, 0);  
    SETGATE(idt[T_DEVICE], 0, GD_KT, XTRPX_Device, 0);  
    SETGATE(idt[T_DBLFLT], 0, GD_KT, XTRPX_DblFlt, 0);  
    SETGATE(idt[T_TSS], 0, GD_KT, XTRPX_Tss, 0);  
    SETGATE(idt[T_SEGNP], 0, GD_KT, XTRPX_Segnp, 0);  
    SETGATE(idt[T_STACK], 0, GD_KT, XTRPX_Stack, 0);  
    SETGATE(idt[T_GPFLT], 0, GD_KT, XTRPX_Gpflt, 0);  
    SETGATE(idt[T_PGFLT], 0, GD_KT, XTRPX_Pgflt, 0);  
    SETGATE(idt[T_FPERR], 0, GD_KT, XTRPX_FpErr, 0);  
    SETGATE(idt[T_ALIGN], 0, GD_KT, XTRPX_Align, 0);  
    SETGATE(idt[T_MCHK], 0, GD_KT, XTRPX_Mchk, 0);  
    SETGATE(idt[T_SIMDERR], 0, GD_KT, XTRPX_SimdErr, 0);  
    SETGATE(idt[T_SYSCALL], 0, GD_KT, XTRPX_Syscall, 3);
    SETGATE(idt[T_DEFAULT], 0, GD_KT, XTRPX_Default, 0);
	
    SETGATE(idt[IRQ_OFFSET+IRQ_TIMER], 0, GD_KT, XTRPX_IRQ0, 0);
    SETGATE(idt[IRQ_OFFSET+IRQ_KBD], 0, GD_KT, XTRPX_IRQ1, 0);
    SETGATE(idt[IRQ_OFFSET+2], 0, GD_KT, XTRPX_IRQ2, 0);
    SETGATE(idt[IRQ_OFFSET+3], 0, GD_KT, XTRPX_IRQ3, 0);
    SETGATE(idt[IRQ_OFFSET+IRQ_SERIAL], 0, GD_KT, XTRPX_IRQ4, 0);
    SETGATE(idt[IRQ_OFFSET+5], 0, GD_KT, XTRPX_IRQ5, 0);
    SETGATE(idt[IRQ_OFFSET+6], 0, GD_KT, XTRPX_IRQ6, 0);
    SETGATE(idt[IRQ_OFFSET+IRQ_SPURIOUS], 0, GD_KT, XTRPX_IRQ7, 0);
    SETGATE(idt[IRQ_OFFSET+8], 0, GD_KT, XTRPX_IRQ8, 0);
    SETGATE(idt[IRQ_OFFSET+9], 0, GD_KT, XTRPX_IRQ9, 0);
    SETGATE(idt[IRQ_OFFSET+10], 0, GD_KT, XTRPX_IRQa, 0);
    SETGATE(idt[IRQ_OFFSET+11], 0, GD_KT, XTRPX_IRQb, 0);
    SETGATE(idt[IRQ_OFFSET+12], 0, GD_KT, XTRPX_IRQc, 0);
    SETGATE(idt[IRQ_OFFSET+13], 0, GD_KT, XTRPX_IRQd, 0);
    SETGATE(idt[IRQ_OFFSET+IRQ_IDE], 0, GD_KT, XTRPX_IRQe, 0);
    SETGATE(idt[IRQ_OFFSET+15], 0, GD_KT, XTRPX_IRQf, 0);
	
    idt_pd.pd_lim = sizeof(idt)-1;
    idt_pd.pd_base = (uint64_t)idt;
	// Per-CPU setup
	trap_init_percpu();
}
Ejemplo n.º 13
0
Archivo: trap.c Proyecto: nollaG/jos
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.
  SETGATE(idt[0],0,GD_KT,trapfun0,0);
  SETGATE(idt[1],0,GD_KT,trapfun1,0);
  SETGATE(idt[2],0,GD_KT,trapfun2,0);
  SETGATE(idt[3],0,GD_KT,trapfun3,3);
  SETGATE(idt[4],0,GD_KT,trapfun4,0);
  SETGATE(idt[5],0,GD_KT,trapfun5,0);
  SETGATE(idt[6],0,GD_KT,trapfun6,0);
  SETGATE(idt[7],0,GD_KT,trapfun7,0);
  SETGATE(idt[8],0,GD_KT,trapfun8,0);
  SETGATE(idt[10],0,GD_KT,trapfun10,0);
  SETGATE(idt[11],0,GD_KT,trapfun11,0);
  SETGATE(idt[12],0,GD_KT,trapfun12,0);
  SETGATE(idt[13],0,GD_KT,trapfun13,0);
  SETGATE(idt[14],0,GD_KT,trapfun14,0);
  SETGATE(idt[16],0,GD_KT,trapfun16,0);
  SETGATE(idt[17],0,GD_KT,trapfun17,0);
  SETGATE(idt[18],0,GD_KT,trapfun18,0);
  SETGATE(idt[19],0,GD_KT,trapfun19,0);
  SETGATE(idt[48],0,GD_KT,trapfun48,3);



  SETGATE(idt[IRQ_OFFSET+0],0,GD_KT,irq0,0);
  SETGATE(idt[IRQ_OFFSET+1],0,GD_KT,irq1,0);
  SETGATE(idt[IRQ_OFFSET+2],0,GD_KT,irq2,0);
  SETGATE(idt[IRQ_OFFSET+3],0,GD_KT,irq3,0);
  SETGATE(idt[IRQ_OFFSET+4],0,GD_KT,irq4,0);
  SETGATE(idt[IRQ_OFFSET+5],0,GD_KT,irq5,0);
  SETGATE(idt[IRQ_OFFSET+6],0,GD_KT,irq6,0);
  SETGATE(idt[IRQ_OFFSET+7],0,GD_KT,irq7,0);
  SETGATE(idt[IRQ_OFFSET+8],0,GD_KT,irq8,0);
  SETGATE(idt[IRQ_OFFSET+9],0,GD_KT,irq9,0);
  SETGATE(idt[IRQ_OFFSET+10],0,GD_KT,irq10,0);
  SETGATE(idt[IRQ_OFFSET+11],0,GD_KT,irq11,0);
  SETGATE(idt[IRQ_OFFSET+12],0,GD_KT,irq12,0);
  SETGATE(idt[IRQ_OFFSET+13],0,GD_KT,irq13,0);
  SETGATE(idt[IRQ_OFFSET+14],0,GD_KT,irq14,0);
  SETGATE(idt[IRQ_OFFSET+15],0,GD_KT,irq15,0);


	// Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 14
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.
	int i;
	for (i = 0; i < 51; ++i) {
		SETGATE(idt[i], 0, GD_KT, traps[i], 0);
	}
	SETGATE(idt[T_BRKPT], 0, GD_KT, traps[T_BRKPT], 3);
	SETGATE(idt[T_SYSCALL], 0, GD_KT, traps[T_SYSCALL], 3);
	
	// Per-CPU setup
	trap_init_percpu();
}
Ejemplo n.º 15
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.

	// vectors[] is defined in kern/trapentry.S
	// see the comments there for important information about its data layout
	extern unsigned int vectors[];
	extern void T_DEFAULT_HANDLER(), T_SYSCALL_HANDLER(), T_BRKPT_HANDLER();    // trap handlers defined in kern/trapentry.S that we must make special references to
	int i;
	unsigned int *vector = vectors;

	// iterate through all possible 256 vectors, defining an IDT entry for each one
	// at each step, vector points to the next defined trap number that has yet to be set in the IDT
	// here we rely on the fact that, in kern/trapentry.S, TRAPHANDLER was called with increasing trap numbers
	for(i = 0; i < 256; i++) {
		if (*vector == i) {
			/*
			 * in this case, vector points to the trap number we must now set in the IDT,
			 * and vector+1 points to the address of the trap handler for this trap
			 */
			if (i >= IRQ_OFFSET && i < IRQ_OFFSET + 16) {
				// processor never checks DPL of the IDT entry when invoking a hardware interrupt handler
				SETGATE(idt[i], 0, GD_KT, *(vector+1), 3);
			}
			else {
				SETGATE(idt[i], 0, GD_KT, *(vector+1), 0);
			}
			vector += 2;	// make vector point to the next trap
		}
		else {
			/*
			 * in this case, there is no defined trap for this vector
			 * set the IDT entry to point to the default trap handler
			 */
			SETGATE(idt[i], 0, GD_KT, &T_DEFAULT_HANDLER, 0);
		}
	}
	// these are special, since they are traps we allow the user to call
	SETGATE(idt[T_SYSCALL], 0, GD_KT, &T_SYSCALL_HANDLER, 3);
	SETGATE(idt[T_BRKPT], 0, GD_KT, &T_BRKPT_HANDLER, 3);

	// Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 16
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];
	// LAB 3: Your code here.

	SETGATE(idt[T_DIVIDE], 0, GD_KT, xt_divide, 0);
	SETGATE(idt[T_DEBUG], 0, GD_KT, xt_debug,0);
	SETGATE(idt[T_DBLFLT], 0, GD_KT, xt_dblflt,0);
	SETGATE(idt[T_SYSCALL], 0, GD_KT, xt_syscall, 3);
	SETGATE(idt[T_NMI], 0, GD_KT, xt_nmi,0);
	SETGATE(idt[T_BRKPT], 0, GD_KT, xt_brkpt,3);
	SETGATE(idt[T_OFLOW], 0, GD_KT, xt_oflow,0);
	SETGATE(idt[T_BOUND], 0, GD_KT, xt_bound,0);
	SETGATE(idt[T_ILLOP], 0, GD_KT, xt_illop,0);
	SETGATE(idt[T_DEVICE], 0, GD_KT, xt_device,0);
	SETGATE(idt[T_TSS], 0, GD_KT, xt_tss,0);
	SETGATE(idt[T_SEGNP], 0, GD_KT, xt_segnp,0);
	SETGATE(idt[T_STACK], 0, GD_KT, xt_stack,0);
	SETGATE(idt[T_GPFLT], 0, GD_KT, xt_gpflt,0);
	SETGATE(idt[T_PGFLT], 0, GD_KT, xt_pgflt,0);
	SETGATE(idt[T_FPERR], 0, GD_KT, xt_fperr,0);
	SETGATE(idt[T_ALIGN], 0, GD_KT, xt_align,0);
        SETGATE(idt[T_MCHK], 0, GD_KT, xt_mchk,0);
	SETGATE(idt[T_SIMDERR], 0, GD_KT, xt_simderr,0);
   	SETGATE(idt[32], 0, GD_KT, xi_timer_0,0);
	SETGATE(idt[33], 0, GD_KT, xi_timer_1,0)
	SETGATE(idt[34], 0, GD_KT, xi_timer_2,0)
         SETGATE(idt[35], 0, GD_KT, xi_timer_3,0)
         SETGATE(idt[36], 0, GD_KT, xi_timer_4,0)
         SETGATE(idt[37], 0, GD_KT, xi_timer_5,0)
         SETGATE(idt[38], 0, GD_KT, xi_timer_6,0)
         SETGATE(idt[39], 0, GD_KT, xi_timer_7,0)
         SETGATE(idt[40], 0, GD_KT, xi_timer_8,0)
         SETGATE(idt[41], 0, GD_KT, xi_timer_9,0)
         SETGATE(idt[42], 0, GD_KT, xi_timer_10,0)
         SETGATE(idt[43], 0, GD_KT, xi_timer_11,0)
         SETGATE(idt[44], 0, GD_KT, xi_timer_12,0)
         SETGATE(idt[45], 0, GD_KT, xi_timer_13,0)
         SETGATE(idt[46], 0, GD_KT, xi_timer_14,0)
         SETGATE(idt[47], 0, GD_KT, xi_timer_15,0)
          idt_pd.pd_lim = sizeof(idt)-1;
    idt_pd.pd_base = (uint64_t)idt;
	// Per-CPU setup
	trap_init_percpu();
//	cprintf("success trap_init");
}
Ejemplo n.º 17
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.
extern void TEST_DIVIDE();
extern void TEST_DEBUG();
extern void TEST_NMI();
extern void TEST_BRKPT();
extern void TEST_OFLOW();
extern void TEST_BOUND();
extern void TEST_ILLOP();
extern void TEST_DEVICE();
extern void TEST_DBLFLT();
extern void TEST_TSS();
extern void TEST_SEGNP();
extern void TEST_STACK();
extern void TEST_GPFLT();
extern void TEST_PGFLT();
extern void TEST_SYSCALL();
  
SETGATE(idt[T_DIVIDE],0,GD_KT,TEST_DIVIDE,0);
SETGATE(idt[T_DEBUG],0,GD_KT,TEST_DEBUG,0);
SETGATE(idt[T_NMI],0,GD_KT,TEST_NMI,0);
SETGATE(idt[T_BRKPT],0,GD_KT,TEST_BRKPT,3);
SETGATE(idt[T_OFLOW],0,GD_KT,TEST_OFLOW,0);
SETGATE(idt[T_BOUND],0,GD_KT,TEST_BOUND,0);
SETGATE(idt[T_ILLOP],0,GD_KT,TEST_ILLOP,0);
SETGATE(idt[T_DEVICE],0,GD_KT,TEST_DEVICE,0);
SETGATE(idt[T_DBLFLT],0,GD_KT,TEST_DBLFLT,0);
SETGATE(idt[T_TSS],0,GD_KT,TEST_TSS,0);
SETGATE(idt[T_SEGNP],0,GD_KT,TEST_SEGNP,0);
SETGATE(idt[T_STACK],0,GD_KT,TEST_DIVIDE,0);
SETGATE(idt[T_GPFLT],0,GD_KT,TEST_GPFLT,0);
SETGATE(idt[T_PGFLT],0,GD_KT,TEST_PGFLT,0);
SETGATE(idt[T_SYSCALL],0,GD_KT,TEST_SYSCALL,3);


idt_pd.pd_lim = sizeof(idt)-1;
idt_pd.pd_base = (uint64_t)idt;

	// Per-CPU setup
	trap_init_percpu();
}
Ejemplo n.º 18
0
Archivo: trap.c Proyecto: joe-cai/jos
void
trap_init(void)
{
    extern struct Segdesc gdt[];
    // LAB 3: Your code here.
    // processor exception
    SETGATE(idt[T_DIVIDE], 0, GD_KT, t_divide, 0);
    SETGATE(idt[T_DEBUG], 0, GD_KT, t_debug, 0);
    SETGATE(idt[T_NMI], 0, GD_KT, t_nmi, 0);
    SETGATE(idt[T_BRKPT], 0, GD_KT, t_brkpt, 3);
    SETGATE(idt[T_OFLOW], 0, GD_KT, t_oflow, 0);
    SETGATE(idt[T_BOUND], 0, GD_KT, t_bound, 0);
    SETGATE(idt[T_ILLOP], 0, GD_KT, t_illop, 0);
    SETGATE(idt[T_DEVICE], 0, GD_KT, t_device, 0);
    SETGATE(idt[T_DBLFLT], 0, GD_KT, t_dblflt, 0);
    SETGATE(idt[T_TSS], 0, GD_KT, t_tss, 0);
    SETGATE(idt[T_SEGNP], 0, GD_KT, t_segnp, 0);
    SETGATE(idt[T_STACK], 0, GD_KT, t_stack, 0);
    SETGATE(idt[T_GPFLT], 0, GD_KT, t_gpflt, 0);
    SETGATE(idt[T_PGFLT], 0, GD_KT, t_pgflt, 0);
    SETGATE(idt[T_FPERR], 0, GD_KT, t_fperr, 0);
    SETGATE(idt[T_ALIGN], 0, GD_KT, t_align, 0);
    SETGATE(idt[T_MCHK], 0, GD_KT, t_mchk, 0);
    SETGATE(idt[T_SIMDERR], 0, GD_KT, t_simderr, 0);
/*
    SETGATE(idt[T_SYSCALL], 1, GD_KT, t_syscall, 3);
    SETGATE(idt[IRQ_OFFSET + IRQ_TIMER], 1, GD_KT, irq_timer, 3);
    SETGATE(idt[IRQ_OFFSET + IRQ_KBD], 1, GD_KT, irq_kbd, 3);
    SETGATE(idt[IRQ_OFFSET + IRQ_SERIAL], 1, GD_KT, irq_serial, 3);
    SETGATE(idt[IRQ_OFFSET + IRQ_SPURIOUS], 1, GD_KT, irq_spurious, 3);
    SETGATE(idt[IRQ_OFFSET + IRQ_IDE], 1, GD_KT, irq_ide, 3);
    SETGATE(idt[IRQ_OFFSET + IRQ_ERROR], 1, GD_KT, irq_error, 3);
*/
    // system call
    SETGATE(idt[T_SYSCALL], 0, GD_KT, t_syscall, 3);
    // hardware interrupts
    SETGATE(idt[IRQ_OFFSET + IRQ_TIMER], 0, GD_KT, irq_timer, 3);
    SETGATE(idt[IRQ_OFFSET + IRQ_KBD], 0, GD_KT, irq_kbd, 3);
    SETGATE(idt[IRQ_OFFSET + IRQ_SERIAL], 0, GD_KT, irq_serial, 3);
    SETGATE(idt[IRQ_OFFSET + IRQ_SPURIOUS], 0, GD_KT, irq_spurious, 3);
    SETGATE(idt[IRQ_OFFSET + IRQ_IDE], 0, GD_KT, irq_ide, 3);
    SETGATE(idt[IRQ_OFFSET + IRQ_ERROR], 0, GD_KT, irq_error, 3);
    // Per-CPU setup 
    trap_init_percpu();
}
Ejemplo n.º 19
0
void	
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.
	int i=0;
	for (; i< MAX_IDT ; i++){
		SETGATE(idt[i], 0, GD_KT, trap_handler[i], 0);
	}
	// init break point
	SETGATE(idt[T_BRKPT], 0, GD_KT, trap_handler[T_BRKPT], 3);
	// init syscall
	SETGATE(idt[T_SYSCALL], 0, GD_KT, trap_handler[T_SYSCALL], 3);

	// Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 20
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.
	SETGATE(idt[T_DIVIDE],0,GD_KT,DIV_HANDLER,3);
	SETGATE(idt[T_BRKPT],0,GD_KT,BRKPT_HANDLER,3);
	SETGATE(idt[T_GPFLT],0,GD_KT,GPFLT_HANDLER,3); 
	SETGATE(idt[T_SYSCALL],0,GD_KT,SYSCALL_HANDLER,3);
	SETGATE(idt[T_PGFLT],0,GD_KT,PGFLT_HANDLER,3); 
	SETGATE(idt[IRQ_OFFSET+IRQ_TIMER],0,GD_KT,IRQ_TIMER_HANDLER,3);
	SETGATE(idt[IRQ_OFFSET+IRQ_KBD],0,GD_KT,IRQ_KBD_HANDLER,3); 
	SETGATE(idt[IRQ_OFFSET+IRQ_SERIAL],0,GD_KT,IRQ_SERIAL_HANDLER,3);
	SETGATE(idt[IRQ_OFFSET+IRQ_SPURIOUS],0,GD_KT,IRQ_SPURIOUS_HANDLER,3);
	SETGATE(idt[IRQ_OFFSET+IRQ_IDE],0,GD_KT,IRQ_IDE_HANDLER,3);
	
	// Per-CPU setup 
	trap_init_percpu();	
}
Ejemplo n.º 21
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.

	int i = 0;
	for ( ; i < 52; i++) {
		SETGATE(idt[i], 0, GD_KT, thandlers[i], 0);
	}

	// Change DPL for break point
	SETGATE(idt[T_BRKPT], 0, GD_KT, thandlers[T_BRKPT], 3);

	// Change DPL for syscall
	SETGATE(idt[T_SYSCALL], 0, GD_KT, thandlers[T_SYSCALL], 3);

	// Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 22
0
// Setup code for APs
void
mp_main(void)
{
	// We are in high EIP now, safe to switch to kern_pgdir 
	lcr3(PADDR(kern_pgdir));
	cprintf("SMP: CPU %d starting\n", cpunum());

	lapic_init();
	env_init_percpu();
	trap_init_percpu();
	xchg(&thiscpu->cpu_status, CPU_STARTED); // tell boot_aps() we're up

	// Now that we have finished some basic setup, call sched_yield()
	// to start running processes on this CPU.  But make sure that
	// only one CPU can enter the scheduler at a time!
	//
	// Your code here:
	lock_kernel();  //Acquire the lock
	sched_yield(); //Call the sched_yield() function to schedule and run different environments, Exercise 6
	// Remove this after you finish Exercise 4
	//for (;;);
}
Ejemplo n.º 23
0
void
trap_init(void)
{
    extern struct Segdesc gdt[];
    // LAB 3: Your code here.
//----------------------------------------  Lab3  ------------------------------------------------------------
//------------------------------------Lab3-Challenge----------------------------------------------------------
    extern uint32_t vec[];
    void tid48();
    int i;
    for (i = 0; i != 20; i++) {
        if (i == 3){
            SETGATE(idt[i], 0, GD_KT, vec[i], 3);
        }
        else
            SETGATE(idt[i], 0, GD_KT, vec[i], 0);   
    }
//------------------------------------Lab3-Challenge----------------------------------------------------------
    SETGATE(idt[48], 0, GD_KT, tid48, 3);
//----------------------------------------  Lab3  ------------------------------------------------------------
//------------  Lab4  ----------------------------------------------------------------------------------------      
    extern void tid32();
    extern void tid33();
    extern void tid36();
    extern void tid39();
    extern void tid46();
    extern void tid51();
    SETGATE(idt[32], 0, GD_KT, tid32, 0);
    SETGATE(idt[33], 0, GD_KT, tid33, 0);
    SETGATE(idt[36], 0, GD_KT, tid36, 0);
    SETGATE(idt[39], 0, GD_KT, tid39, 0);
    SETGATE(idt[46], 0, GD_KT, tid46, 0);
    SETGATE(idt[51], 0, GD_KT, tid51, 0);
//------------  Lab4  ----------------------------------------------------------------------------------------          
    // Per-CPU setup 
    trap_init_percpu();
}
Ejemplo n.º 24
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// Create entries for the IDT
	SETGATE(idt[T_DIVIDE], 0, GD_KT, handle_divide, 0);
	SETGATE(idt[T_DEBUG], 0, GD_KT, handle_debug, 0);
	SETGATE(idt[T_NMI], 0, GD_KT, handle_nmi, 0);
	SETGATE(idt[T_BRKPT], 0, GD_KT, handle_brkpt, 3);
	SETGATE(idt[T_OFLOW], 0, GD_KT, handle_oflow, 0);
	SETGATE(idt[T_BOUND], 0, GD_KT, handle_bound, 0);
	SETGATE(idt[T_ILLOP], 0, GD_KT, handle_illop, 0);
	SETGATE(idt[T_DEVICE], 0, GD_KT, handle_device, 0);
	SETGATE(idt[T_DBLFLT], 0, GD_KT, handle_dblflt, 0);
	SETGATE(idt[T_TSS], 0, GD_KT, handle_tss, 0);
	SETGATE(idt[T_SEGNP], 0, GD_KT, handle_segnp, 0);
	SETGATE(idt[T_STACK], 0, GD_KT, handle_stack, 0);
	SETGATE(idt[T_GPFLT], 0, GD_KT, handle_gpflt, 0);
	SETGATE(idt[T_PGFLT], 0, GD_KT, handle_pgflt, 0);
	SETGATE(idt[T_FPERR], 0, GD_KT, handle_fperr, 0);
	SETGATE(idt[T_ALIGN], 0, GD_KT, handle_align, 0);
	SETGATE(idt[T_MCHK], 0, GD_KT, handle_mchk, 0);
	SETGATE(idt[T_SIMDERR], 0, GD_KT, handle_simderr, 0);
	SETGATE(idt[T_SYSCALL], 0, GD_KT, handle_syscall, 3);

	SETGATE(idt[IRQ_OFFSET+IRQ_TIMER], 0, GD_KT, handle_irq_timer, 0);
	SETGATE(idt[IRQ_OFFSET+IRQ_KBD], 0, GD_KT, handle_irq_kbd, 0);
	SETGATE(idt[IRQ_OFFSET+IRQ_SERIAL], 0, GD_KT, handle_irq_serial, 0);
	SETGATE(idt[IRQ_OFFSET+IRQ_SPURIOUS], 0, GD_KT, handle_irq_spurious, 0);
	SETGATE(idt[IRQ_OFFSET+IRQ_IDE], 0, GD_KT, handle_irq_ide, 0);
	SETGATE(idt[IRQ_OFFSET+IRQ_ERROR], 0, GD_KT, handle_irq_error, 0);

	// Per-CPU setup
	trap_init_percpu();
}
Ejemplo n.º 25
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];
	uint32_t istrap = 0;
	uint32_t dpl = 0;
	uint32_t upl = 3;
	
	extern void CSE_DIVIDE();     /* divide error*/ 
	extern void CSE_DEBUG();      /* debug exception*/
	extern void CSE_NMI();     /* non-maskable interrupt*/
	extern void CSE_BRKPT();     /* breakpoint*/
	extern void CSE_OFLOW();     /* overflow*/
	extern void CSE_BOUND();     /* bounds check*/
	extern void CSE_ILLOP();     /* illegal opcode*/
	extern void CSE_DEVICE();     /* device not available*/
	extern void CSE_DBLFLT();      /* double fault*/
	/* #define T_COPROC  9    // reserved (not generated by recent processors)*/
	extern void CSE_TSS();     /* invalid task switch segment*/
	extern void CSE_SEGNP();      /* segment not present*/
	extern void CSE_STACK();      /* stack exception*/
	extern void CSE_GPFLT();      /* general protection fault*/
	extern void CSE_PGFLT();      /* page fault*/
	/* #define T_RES    15    // reserved*/
	extern void CSE_FPERR();      /* floating point error*/
	extern void CSE_ALIGN();      /* aligment check*/
	extern void CSE_MCHK();      /* machine check*/
	extern void CSE_SIMDERR();      /* SIMD floating point error*/
	
	extern void CSE_SYSCALL();		/*SYSTEM CALL interrupt*/
	
	extern void CSE_IRQ0();
	extern void CSE_IRQ1();
	extern void CSE_IRQ2();
	extern void CSE_IRQ3();
	extern void CSE_IRQ4();
	extern void CSE_IRQ5();
	extern void CSE_IRQ6();
	extern void CSE_IRQ7();
	extern void CSE_IRQ8();
	extern void CSE_IRQ9();
	extern void CSE_IRQ10();
	extern void CSE_IRQ11();
	extern void CSE_IRQ12();
	extern void CSE_IRQ13();
	extern void CSE_IRQ14();
	extern void CSE_IRQ15();
		
	SETGATE(idt[0], istrap, GD_KT, CSE_DIVIDE, dpl);
	SETGATE(idt[1], istrap, GD_KT, CSE_DEBUG, dpl);
	SETGATE(idt[2], istrap, GD_KT, CSE_NMI, dpl);
	SETGATE(idt[3], istrap, GD_KT, CSE_BRKPT, upl);
	SETGATE(idt[4], istrap, GD_KT, CSE_OFLOW, dpl);
	SETGATE(idt[5], istrap, GD_KT, CSE_BOUND, dpl);
	SETGATE(idt[6], istrap, GD_KT, CSE_ILLOP, dpl);
	SETGATE(idt[7], istrap, GD_KT, CSE_DEVICE, dpl);
	SETGATE(idt[8], istrap, GD_KT, CSE_DBLFLT, dpl);
	SETGATE(idt[10], istrap, GD_KT, CSE_TSS, dpl);
	SETGATE(idt[11], istrap, GD_KT, CSE_SEGNP, dpl);
	SETGATE(idt[12], istrap, GD_KT, CSE_STACK, dpl);
	SETGATE(idt[13], istrap, GD_KT, CSE_GPFLT, dpl);
	SETGATE(idt[14], istrap, GD_KT, CSE_PGFLT, dpl);
	SETGATE(idt[16], istrap, GD_KT, CSE_FPERR, dpl);
	SETGATE(idt[17], istrap, GD_KT, CSE_ALIGN, dpl);
	SETGATE(idt[18], istrap, GD_KT, CSE_MCHK, dpl);
	SETGATE(idt[19], istrap, GD_KT, CSE_SIMDERR, dpl);
	
	SETGATE(idt[48], istrap, GD_KT, CSE_SYSCALL, upl);

	
	SETGATE(idt[32], istrap, GD_KT, CSE_IRQ0, dpl);
	SETGATE(idt[33], istrap, GD_KT, CSE_IRQ1, dpl);
	SETGATE(idt[34], istrap, GD_KT, CSE_IRQ2, dpl);
	SETGATE(idt[35], istrap, GD_KT, CSE_IRQ3, dpl);
	SETGATE(idt[36], istrap, GD_KT, CSE_IRQ4, dpl);
	SETGATE(idt[37], istrap, GD_KT, CSE_IRQ5, dpl);
	SETGATE(idt[38], istrap, GD_KT, CSE_IRQ6, dpl);
	SETGATE(idt[39], istrap, GD_KT, CSE_IRQ7, dpl);
	SETGATE(idt[40], istrap, GD_KT, CSE_IRQ8, dpl);
	SETGATE(idt[41], istrap, GD_KT, CSE_IRQ9, dpl);
	SETGATE(idt[42], istrap, GD_KT, CSE_IRQ10, dpl);
	SETGATE(idt[43], istrap, GD_KT, CSE_IRQ11, dpl);
	SETGATE(idt[44], istrap, GD_KT, CSE_IRQ12, dpl);
	SETGATE(idt[45], istrap, GD_KT, CSE_IRQ13, dpl);
	SETGATE(idt[46], istrap, GD_KT, CSE_IRQ14, dpl);
	SETGATE(idt[47], istrap, GD_KT, CSE_IRQ15, dpl);


	// LAB 3: Your code here.
    idt_pd.pd_lim = sizeof(idt)-1;
    idt_pd.pd_base = (uint64_t)idt;
	// Per-CPU setup
	trap_init_percpu();
}
Ejemplo n.º 26
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];
extern void intr_irq0();
extern void intr_irq1();
extern void intr_irq2();
extern void intr_irq3();
extern void intr_irq4();
extern void intr_irq5();
extern void intr_irq6();
extern void intr_irq7();
extern void intr_irq8();
extern void intr_irq9();
extern void intr_irq10();
extern void intr_irq11();
extern void intr_irq12();
extern void intr_irq13();
extern void intr_irq14();
extern void intr_irq15();
SETGATE( idt[IRQ_OFFSET + 0], 0, GD_KT, intr_irq0, 0);
SETGATE( idt[IRQ_OFFSET + 1], 0, GD_KT, intr_irq1, 0);
SETGATE( idt[IRQ_OFFSET + 2], 0, GD_KT, intr_irq2, 0);
SETGATE( idt[IRQ_OFFSET + 3], 0, GD_KT, intr_irq3, 0);
SETGATE( idt[IRQ_OFFSET + 4], 0, GD_KT, intr_irq4, 0);
SETGATE( idt[IRQ_OFFSET + 5], 0, GD_KT, intr_irq5, 0);
SETGATE( idt[IRQ_OFFSET + 6], 0, GD_KT, intr_irq6, 0);
SETGATE( idt[IRQ_OFFSET + 7], 0, GD_KT, intr_irq7, 0); 
SETGATE( idt[IRQ_OFFSET + 8], 0, GD_KT, intr_irq8, 0);
SETGATE( idt[IRQ_OFFSET + 9], 0, GD_KT, intr_irq9, 0);
SETGATE( idt[IRQ_OFFSET + 10], 0, GD_KT, intr_irq10, 0);
SETGATE( idt[IRQ_OFFSET + 11], 0, GD_KT, intr_irq11, 0);
SETGATE( idt[IRQ_OFFSET + 12], 0, GD_KT, intr_irq12, 0);
SETGATE( idt[IRQ_OFFSET + 13], 0, GD_KT, intr_irq13, 0);
SETGATE( idt[IRQ_OFFSET + 14], 0, GD_KT, intr_irq14, 0);
SETGATE( idt[IRQ_OFFSET + 15], 1, GD_KT, intr_irq15, 0);
	// LAB 3: Your code here.
/*	void routine_divde();
	void routine_debug();
	void routine_nmi();
	void routine_brkpt();
	void routine_oflow();
	void routine_bound();
	void routine_illop();
	void routine_device();
	void routine_dblft();
	void routine_tss();
	void routine_segnp();
	void routine_stack();
	void routine_gpflt();
	void routine_pgflt();
	void routine_fperr();  
    void routine_syscall();
	SETGATE(idt[0], 0, GD_KT, routine_divde, 0);
	SETGATE(idt[1], 0, GD_KT, routine_debug, 0);
	SETGATE(idt[2], 0, GD_KT, routine_nmi, 0);
	SETGATE(idt[3], 0, GD_KT, routine_brkpt, 3);
	SETGATE(idt[4], 0, GD_KT, routine_oflow, 0);
	SETGATE(idt[5], 0, GD_KT, routine_bound, 0);
	SETGATE(idt[6], 0, GD_KT, routine_illop, 0);
	SETGATE(idt[7], 0, GD_KT, routine_device, 0);
	SETGATE(idt[8], 0, GD_KT, routine_dblft, 0);
	SETGATE(idt[10], 0, GD_KT, routine_tss, 0);
	SETGATE(idt[11], 0, GD_KT, routine_segnp, 0);
	SETGATE(idt[12], 0, GD_KT, routine_stack, 0);
	SETGATE(idt[13], 0, GD_KT, routine_gpflt, 0);
	SETGATE(idt[14], 0, GD_KT, routine_pgflt, 0);
	SETGATE(idt[16], 0, GD_KT, routine_fperr, 0);  
    SETGATE(idt[48], 0, GD_KT, routine_syscall, 3);
*/
    //Challenge
	extern void (*funs[])();
	int i =0 ;
	while (i <=16)
    {
		if (i==T_BRKPT)
			SETGATE(idt[i], 0, GD_KT, funs[i], 3)
		else if (i!=2 && i!=15) {
			SETGATE(idt[i], 0, GD_KT, funs[i], 0);
		}
        ++i;
    }
	SETGATE(idt[48], 0, GD_KT, funs[48], 3);
                            SETGATE(idt[48], 0, GD_KT, funs[48], 3);
    // Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 27
0
Archivo: trap.c Proyecto: chenkexin/jos
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.
  void th0();
  void th1();
  void th3();
  void th4();
  void th5();
  void th6();
  void th7();
  void th8();
  void th9();
  void th10();
  void th11();
  void th12();
  void th13();
  void th14();
  void th16();
	void th48();

	void th32();
	void th33();
	void th34();
	void th35();
	void th36();
	void th37();
	void th38();
	void th39();
	void th40();
	void th41();
	void th42();
	void th43();
	void th44();
	void th45();
	void th46();
	void th47();
  
  SETGATE(idt[0], 0, GD_KT, th0, 0);
  SETGATE(idt[1], 0, GD_KT, th1, 0);
  //modify 0 to 3 to pass breakpoint test.
	SETGATE(idt[3], 0, GD_KT, th3, 0);
	SETGATE(idt[3], 0, GD_KT, th3, 3);
  SETGATE(idt[4], 0, GD_KT, th4, 0);
  SETGATE(idt[5], 0, GD_KT, th5, 0);
  SETGATE(idt[6], 0, GD_KT, th6, 0);
  SETGATE(idt[7], 0, GD_KT, th7, 0);
  SETGATE(idt[8], 0, GD_KT, th8, 0);
  SETGATE(idt[9], 0, GD_KT, th9, 0);
  SETGATE(idt[10], 0, GD_KT, th10, 0);
  SETGATE(idt[11], 0, GD_KT, th11, 0);
  SETGATE(idt[12], 0, GD_KT, th12, 0);
  SETGATE(idt[13], 0, GD_KT, th13, 0);
  SETGATE(idt[14], 0, GD_KT, th14, 0);
  SETGATE(idt[16], 0, GD_KT, th16, 0);
	SETGATE(idt[48], 0, GD_KT, th48, 0);
	SETGATE(idt[48], 0, GD_KT, th48, 3);


  SETGATE(idt[32], 0, GD_KT, th32, 0);
  SETGATE(idt[33], 0, GD_KT, th33, 0);
  SETGATE(idt[34], 0, GD_KT, th34, 0);
  SETGATE(idt[35], 0, GD_KT, th35, 0);
  SETGATE(idt[36], 0, GD_KT, th36, 0);
  SETGATE(idt[37], 0, GD_KT, th37, 0);
  SETGATE(idt[38], 0, GD_KT, th38, 0);
  SETGATE(idt[39], 0, GD_KT, th39, 0);
  SETGATE(idt[40], 0, GD_KT, th40, 0);
  SETGATE(idt[41], 0, GD_KT, th41, 0);
  SETGATE(idt[42], 0, GD_KT, th42, 0);
  SETGATE(idt[43], 0, GD_KT, th43, 0);
  SETGATE(idt[44], 0, GD_KT, th44, 0);
  SETGATE(idt[45], 0, GD_KT, th45, 0);
  SETGATE(idt[46], 0, GD_KT, th46, 0);
  SETGATE(idt[47], 0, GD_KT, th47, 0);
	// Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 28
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.
	/*
	void vec0();
	void vec1();
	void vec2();
	void vec3();
	void vec4();
	void vec6();
	void vec7();
	void vec8();
	void vec10();
	void vec11();
	void vec12();
	void vec13();
	void vec14();
	void vec16();	
	void vec17();
	void vec18();
	void vec19();
    void vec48();

	SETGATE(idt[0], 0, GD_KT, vec0, 0);
	SETGATE(idt[1], 0, GD_KT, vec1, 0);
	SETGATE(idt[2], 0, GD_KT, vec2, 0);
	SETGATE(idt[3], 0, GD_KT, vec3, 3);     // software interrupt 
	SETGATE(idt[4], 0, GD_KT, vec4, 0);

	SETGATE(idt[6], 0, GD_KT, vec6, 0);
	SETGATE(idt[7], 0, GD_KT, vec7, 0);
	SETGATE(idt[8], 0, GD_KT, vec8, 0);
	SETGATE(idt[10], 0, GD_KT, vec10, 0);
	SETGATE(idt[11], 0, GD_KT, vec11, 0);
	SETGATE(idt[12], 0, GD_KT, vec12, 0);
	SETGATE(idt[13], 0, GD_KT, vec13, 0);
	SETGATE(idt[14], 0, GD_KT, vec14, 0);

	SETGATE(idt[16], 0, GD_KT, vec16, 0);
	SETGATE(idt[17], 0, GD_KT, vec17, 0);
	SETGATE(idt[18], 0, GD_KT, vec18, 0);
	SETGATE(idt[19], 0, GD_KT, vec19, 0);
    SETGATE(idt[48], 0, GD_KT, vec48, 3);
    */
    
    extern uint32_t vectors[];
    extern void vec48();
    int i;
    for (i = 0; i != 20; i++) {
    	if (i == T_BRKPT) {
    		SETGATE(idt[i], 0, GD_KT, vectors[i], 3);
    	} else {
    		SETGATE(idt[i], 0, GD_KT, vectors[i], 0);
    	}
    }
    SETGATE(idt[48], 0, GD_KT, vec48, 3);

	// Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 29
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];

	// LAB 3: Your code here.
	// Handlers defined in trapentry.S
	extern void handler_divide();
	extern void handler_debug();
	extern void handler_nmi();
	extern void handler_brkpt();
	extern void handler_oflow();
	extern void handler_bound();
	extern void handler_illop();
	extern void handler_device();
	extern void handler_dblflt();
	//extern void handler_coproc();
	extern void handler_tss();
	extern void handler_segnp();
	extern void handler_stack();
	extern void handler_gpflt();
	extern void handler_pgflt();
	//extern void handler_res();
	extern void handler_fperr();
	extern void handler_align();
	extern void handler_mchk();
	extern void handler_simderr();
	extern void handler_syscall();

	extern void handler_irq0();
	extern void handler_irq1();
	extern void handler_irq2();
	extern void handler_irq3();
	extern void handler_irq4();
	extern void handler_irq5();
	extern void handler_irq6();
	extern void handler_irq7();
	extern void handler_irq8();
	extern void handler_irq9();
	extern void handler_irq10();
	extern void handler_irq11();
	extern void handler_irq12();
	extern void handler_irq13();
	extern void handler_irq14();
	extern void handler_irq15();

	// Initialize entries in idt
	SETGATE(idt[T_DIVIDE], 0, GD_KT, handler_divide, DPL_KERN);
	SETGATE(idt[T_DEBUG], 0, GD_KT, handler_debug, DPL_KERN); // Don't allow interrupts while in debug mode
	SETGATE(idt[T_NMI], 0, GD_KT, handler_nmi, DPL_KERN);
	SETGATE(idt[T_BRKPT], 0, GD_KT, handler_brkpt, DPL_USER);
	SETGATE(idt[T_OFLOW], 0, GD_KT, handler_oflow, DPL_KERN);
	SETGATE(idt[T_BOUND], 0, GD_KT, handler_bound, DPL_KERN);
	SETGATE(idt[T_ILLOP], 0, GD_KT, handler_illop, DPL_KERN);
	SETGATE(idt[T_DEVICE], 0, GD_KT, handler_device, DPL_KERN);
	SETGATE(idt[T_DBLFLT], 0, GD_KT, handler_dblflt, DPL_KERN);
	//SETGATE(idt[T_COPROC], 0, GD_KT, handler_coproc, 0);
	SETGATE(idt[T_TSS], 0, GD_KT, handler_tss, DPL_KERN);
	SETGATE(idt[T_SEGNP], 0, GD_KT, handler_segnp, DPL_KERN);
	SETGATE(idt[T_STACK], 0, GD_KT, handler_stack, DPL_KERN);
	SETGATE(idt[T_GPFLT], 0, GD_KT, handler_gpflt, DPL_KERN);
	SETGATE(idt[T_PGFLT], 0, GD_KT, handler_pgflt, DPL_KERN);
	//SETGATE(idt[T_RES], 0, GD_KT, handler_res, 0);
	SETGATE(idt[T_FPERR], 0, GD_KT, handler_fperr, DPL_KERN);
	SETGATE(idt[T_ALIGN], 0, GD_KT, handler_align, DPL_KERN);
	SETGATE(idt[T_MCHK], 0, GD_KT, handler_mchk, DPL_KERN);
	SETGATE(idt[T_SIMDERR], 0, GD_KT, handler_simderr, DPL_KERN);

	//Initial system call entry
	SETGATE(idt[T_SYSCALL], 0, GD_KT, handler_syscall, DPL_USER);

	// Initialize IRQ entries
	SETGATE(idt[IRQ_OFFSET], 0, GD_KT, handler_irq0, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 1], 0, GD_KT, handler_irq1, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 2], 0, GD_KT, handler_irq2, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 3], 0, GD_KT, handler_irq3, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 4], 0, GD_KT, handler_irq4, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 5], 0, GD_KT, handler_irq5, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 6], 0, GD_KT, handler_irq6, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 7], 0, GD_KT, handler_irq7, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 8], 0, GD_KT, handler_irq8, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 9], 0, GD_KT, handler_irq9, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 10], 0, GD_KT, handler_irq10, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 11], 0, GD_KT, handler_irq11, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 12], 0, GD_KT, handler_irq12, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 13], 0, GD_KT, handler_irq13, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 14], 0, GD_KT, handler_irq14, DPL_KERN);
	SETGATE(idt[IRQ_OFFSET + 15], 0, GD_KT, handler_irq15, DPL_KERN);

	// Per-CPU setup 
	trap_init_percpu();
}
Ejemplo n.º 30
0
void
trap_init(void)
{
	extern struct Segdesc gdt[];
	// LAB 3: Your code here.
	
	extern void divide_handler();
	extern void debug_handler();
	extern void nmi_handler();
	extern void brkpt_handler();
	extern void oflow_handler();
	extern void bound_handler();
	extern void illop_handler();
	extern void device_handler();
	extern void dblflt_handler();
	extern void tss_handler();
	extern void segnp_handler();
	extern void stack_handler();
	extern void gpflt_handler();
	extern void pgflt_handler();
	extern void fperr_handler();
	extern void align_handler();
	extern void mchk_handler();
	extern void simderr_handler();

	extern void irq0();
	extern void irq1();
	extern void irq2();
	extern void irq3();
	extern void irq4();
	extern void irq5();
	extern void irq6();
	extern void irq7();
	extern void irq8();
	extern void irq9();
	extern void irq10();
	extern void irq11();
	extern void irq12();
	extern void irq13();
	extern void irq14();
	extern void irq15();

	extern void sysint_handler();

	SETGATE(idt[T_DIVIDE], 0, GD_KT, divide_handler, 0);
	SETGATE(idt[T_DEBUG], 0, GD_KT, debug_handler, 0);
	SETGATE(idt[T_NMI], 0, GD_KT, nmi_handler, 0);
	SETGATE(idt[T_BRKPT], 0, GD_KT, brkpt_handler, 3);
	SETGATE(idt[T_OFLOW], 0, GD_KT, oflow_handler, 0);
	SETGATE(idt[T_BOUND], 0, GD_KT, bound_handler, 0);
	SETGATE(idt[T_ILLOP], 0, GD_KT, illop_handler, 0);
	SETGATE(idt[T_DEVICE], 0, GD_KT, device_handler, 0);
	SETGATE(idt[T_DBLFLT], 0, GD_KT, dblflt_handler, 0);
	SETGATE(idt[T_TSS], 0, GD_KT, tss_handler, 0);
	SETGATE(idt[T_SEGNP], 0, GD_KT, segnp_handler, 0);
	SETGATE(idt[T_STACK], 0, GD_KT, stack_handler, 0);
	SETGATE(idt[T_GPFLT], 0, GD_KT, gpflt_handler, 0);
	SETGATE(idt[T_PGFLT], 0, GD_KT, pgflt_handler, 0);
	SETGATE(idt[T_FPERR], 0, GD_KT, fperr_handler, 0);
	SETGATE(idt[T_ALIGN], 0, GD_KT, align_handler, 0);
	SETGATE(idt[T_MCHK], 0, GD_KT, mchk_handler, 0);
	SETGATE(idt[T_SIMDERR],0, GD_KT, simderr_handler, 0);

	SETGATE(idt[IRQ_OFFSET+0], 0, GD_KT, irq0, 0);
	SETGATE(idt[IRQ_OFFSET+1], 0, GD_KT, irq1, 0);
	SETGATE(idt[IRQ_OFFSET+2], 0, GD_KT, irq2, 0);
	SETGATE(idt[IRQ_OFFSET+3], 0, GD_KT, irq3, 0);
	SETGATE(idt[IRQ_OFFSET+4], 0, GD_KT, irq4, 0);
	SETGATE(idt[IRQ_OFFSET+5], 0, GD_KT, irq5, 0);
	SETGATE(idt[IRQ_OFFSET+6], 0, GD_KT, irq6, 0);
	SETGATE(idt[IRQ_OFFSET+7], 0, GD_KT, irq7, 0);
	SETGATE(idt[IRQ_OFFSET+8], 0, GD_KT, irq8, 0);
	SETGATE(idt[IRQ_OFFSET+9], 0, GD_KT, irq9, 0);
	SETGATE(idt[IRQ_OFFSET+10], 0, GD_KT, irq10, 0);
	SETGATE(idt[IRQ_OFFSET+11], 0, GD_KT, irq11, 0);
	SETGATE(idt[IRQ_OFFSET+12], 0, GD_KT, irq12, 0);
	SETGATE(idt[IRQ_OFFSET+13], 0, GD_KT, irq13, 0);
	SETGATE(idt[IRQ_OFFSET+14], 0, GD_KT, irq14, 0);
	SETGATE(idt[IRQ_OFFSET+15], 0, GD_KT, irq15, 0);

	SETGATE(idt[T_SYSCALL], 0, GD_KT, sysint_handler, 3);

	// Per-CPU setup 
	trap_init_percpu();
}