/
at91_spi.c
301 lines (238 loc) · 8.74 KB
/
at91_spi.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
/*
* Serial Peripheral Interface (SPI) driver for the Atmel AT91RM9200 (Thunder)
*
* Copyright (C) SAN People (Pty) Ltd
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/init.h>
#include <linux/module.h>
#include <asm/semaphore.h>
#include <linux/pci.h>
#include <linux/sched.h>
#include <linux/completion.h>
#include <linux/interrupt.h>
#include <asm/arch/AT91RM9200_SPI.h>
#include <asm/arch/board.h>
#include <asm/arch/pio.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_spi.h>
#define DEBUG_SPI 0
#undef DEBUG_SPI
static struct spi_local spi_dev[NR_SPI_DEVICES]; /* state of the SPI devices */
static int spi_enabled = 0;
static struct semaphore spi_lock; /* protect access to SPI bus */
static int current_device = -1; /* currently selected SPI device */
DECLARE_COMPLETION(transfer_complete);
/* SPI controller device */
static AT91PS_SPI controller = (AT91PS_SPI) AT91C_VA_BASE_SPI;
/* ......................................................................... */
/*
* Access and enable the SPI bus.
* This MUST be called before any transfers are performed.
*/
void spi_access_bus(short device)
{
/* Ensure that requested device is valid */
if ((device < 0) || (device >= NR_SPI_DEVICES))
panic("at91_spi: spi_access_bus called with invalid device");
if (spi_enabled == 0) {
AT91_SYS->PMC_PCER = 1 << AT91C_ID_SPI; /* Enable Peripheral clock */
controller->SPI_CR = AT91C_SPI_SPIEN; /* Enable SPI */
controller->SPI_MR = AT91C_SPI_DIV32; /* The SPI operates at MCK/32 */
#ifdef DEBUG_SPI
printk(KERN_INFO "[DEBUG INFO] : SPI On\n");
#endif /* DEBUG_SPI */
}
spi_enabled++;
/* Lock the SPI bus */
down(&spi_lock);
current_device = device;
/* Enable PIO */
if (!spi_dev[device].pio_enabled) {
switch (device) {
case 0: AT91_CfgPIO_SPI_CS0(); break;
case 1: AT91_CfgPIO_SPI_CS1(); break;
case 2: AT91_CfgPIO_SPI_CS2(); break;
case 3: AT91_CfgPIO_SPI_CS3(); break;
}
spi_dev[device].pio_enabled = 1;
#ifdef DEBUG_SPI
printk(KERN_INFO "[DEBUG INFO] : SPI CS%i enabled\n", device);
#endif
}
/* Configure SPI bus for device */
controller->SPI_MR = AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | (spi_dev[device].pcs << 16);
at91_set_gpio_value(AT91_PIN_PA24, 0);
}
/*
* Relinquish control of the SPI bus.
*/
void spi_release_bus(short device)
{
at91_set_gpio_value(AT91_PIN_PA24, 1);
if (device != current_device)
panic("at91_spi: spi_release called with invalid device");
/* Release the SPI bus */
current_device = -1;
up(&spi_lock);
spi_enabled--;
if (spi_enabled == 0) {
controller->SPI_CR = AT91C_SPI_SPIDIS; /* Disable SPI */
AT91_SYS->PMC_PCER = 1 << AT91C_ID_SPI; /* Disable Peripheral clock */
#ifdef DEBUG_SPI
printk(KERN_INFO "[DEBUG INFO] : SPI off\n");
#endif
}
// at91_set_gpio_value(AT91_PIN_PA24, 1);
}
/*
* Perform a data transfer over the SPI bus
*/
int spi_transfer(struct spi_transfer_list* list)
{
struct spi_local *device = (struct spi_local *) &spi_dev[current_device];
if (!list)
panic("at91_spi: spi_transfer called with NULL transfer list");
if (current_device == -1)
panic("at91_spi: spi_transfer called without acquiring bus");
#ifdef DEBUG_SPI
printk(KERN_INFO "[DEBUG INFO] : SPI transfer start [%i]\n", list->nr_transfers);
#endif
/* Store transfer list */
device->xfers = list;
list->curr = 0;
/* Assume there must be at least one transfer */
device->tx = pci_map_single(NULL, list->tx[0], list->txlen[0], PCI_DMA_TODEVICE);
device->rx = pci_map_single(NULL, list->rx[0], list->rxlen[0], PCI_DMA_FROMDEVICE);
/* Program PDC registers */
controller->SPI_TPR = device->tx;
controller->SPI_RPR = device->rx;
controller->SPI_TCR = list->txlen[0];
controller->SPI_RCR = list->rxlen[0];
/* Is there a second transfer? */
if (list->nr_transfers > 1) {
device->txnext = pci_map_single(NULL, list->tx[1], list->txlen[1], PCI_DMA_TODEVICE);
device->rxnext = pci_map_single(NULL, list->rx[1], list->rxlen[1], PCI_DMA_FROMDEVICE);
/* Program Next PDC registers */
controller->SPI_TNPR = device->txnext;
controller->SPI_RNPR = device->rxnext;
controller->SPI_TNCR = list->txlen[1];
controller->SPI_RNCR = list->rxlen[1];
}
else {
device->txnext = 0;
device->rxnext = 0;
controller->SPI_TNCR = 0;
controller->SPI_RNCR = 0;
}
// TODO: If we are doing consecutive transfers (at high speed, or
// small buffers), then it might be worth modifying the 'Delay between
// Consecutive Transfers' in the CSR registers.
// This is an issue if we cannot chain the next buffer fast enough
// in the interrupt handler.
/* Enable transmitter and receiver */
at91_set_gpio_value(AT91_PIN_PA24, 0);
controller->SPI_PTCR = AT91C_PDC_RXTEN | AT91C_PDC_TXTEN;
controller->SPI_IER = AT91C_SPI_SPENDRX; /* enable buffer complete interrupt */
wait_for_completion(&transfer_complete);
// at91_set_gpio_value(AT91_PIN_PA24, 1);
#ifdef DEBUG_SPI
printk("[DEBUG INFO] : SPI ");
printk(KERN_INFO "[DEBUG INFO] : SPI transfer end\n");
#endif
return 0;
}
/* ......................................................................... */
/*
* Handle interrupts from the SPI controller.
*/
static irqreturn_t spi_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
unsigned int status;
struct spi_local *device = (struct spi_local *) &spi_dev[current_device];
struct spi_transfer_list *list = device->xfers;
#ifdef DEBUG_SPI
printk(KERN_INFO "[DEBUG INFO] : SPI interrupt %i\n", current_device);
#endif
if (!list)
panic("at91_spi: spi_interrupt with a NULL transfer list");
status = controller->SPI_SR & controller->SPI_IMR; /* read status */
pci_unmap_single(NULL, device->tx, list->txlen[list->curr], PCI_DMA_TODEVICE);
pci_unmap_single(NULL, device->rx, list->rxlen[list->curr], PCI_DMA_FROMDEVICE);
device->tx = device->txnext; /* move next transfer to current transfer */
device->rx = device->rxnext;
list->curr = list->curr + 1;
if (list->curr == list->nr_transfers) { /* all transfers complete */
controller->SPI_IDR = AT91C_SPI_SPENDRX; /* disable interrupt */
/* Disable transmitter and receiver */
controller->SPI_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;
device->xfers = NULL;
complete(&transfer_complete);
}
else if (list->curr+1 == list->nr_transfers) { /* no more next transfers */
device->txnext = 0;
device->rxnext = 0;
controller->SPI_TNCR = 0;
controller->SPI_RNCR = 0;
}
else {
int i = (list->curr)+1;
device->txnext = pci_map_single(NULL, list->tx[i], list->txlen[i], PCI_DMA_TODEVICE);
device->rxnext = pci_map_single(NULL, list->rx[i], list->rxlen[i], PCI_DMA_FROMDEVICE);
controller->SPI_TNPR = device->txnext;
controller->SPI_RNPR = device->rxnext;
controller->SPI_TNCR = list->txlen[i];
controller->SPI_RNCR = list->rxlen[i];
}
return IRQ_HANDLED;
}
/* ......................................................................... */
/******************************************************************************/
/******************************************************************************/
/*
* Initialize the SPI controller
*/
static int __init at91_spi_init(void)
{
init_MUTEX(&spi_lock);
AT91_CfgPIO_SPI();
controller->SPI_CR = AT91C_SPI_SWRST; /* software reset of SPI controller */
/* Set Chip Select registers to good defaults */
// controller->SPI_CSR0 = AT91C_SPI_CPOL |AT91C_SPI_NCPHA | AT91C_SPI_BITS_8 | (1 << 16) | (15 << 8);
controller->SPI_CSR0 = AT91C_SPI_BITS_8 | (16 << 16) | (15 << 8);
controller->SPI_CSR1 = AT91C_SPI_CPOL | AT91C_SPI_BITS_8 | (16 << 16) | (DEFAULT_SPI_BAUD << 8);
controller->SPI_CSR2 = AT91C_SPI_CPOL | AT91C_SPI_BITS_8 | (16 << 16) | (DEFAULT_SPI_BAUD << 8);
controller->SPI_CSR3 = AT91C_SPI_CPOL | AT91C_SPI_BITS_8 | (16 << 16) | (DEFAULT_SPI_BAUD << 8);
controller->SPI_PTCR = AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS;
memset(&spi_dev, 0, sizeof(spi_dev));
spi_dev[0].pcs = 0xE;
spi_dev[1].pcs = 0xD;
spi_dev[2].pcs = 0xB;
spi_dev[3].pcs = 0x7;
if (request_irq(AT91C_ID_SPI, spi_interrupt, 0, "dudu_spi", NULL))
{
printk(KERN_INFO "I am Busy.\n");
return -EBUSY;
}
controller->SPI_CR = AT91C_SPI_SPIEN; /* Enable SPI */
/******************************************************************************/
at91_set_gpio_output(AT91_PIN_PA24, 1);
at91_set_gpio_value(AT91_PIN_PA24, 1);
/******************************************************************************/
return 0;
}
static void __exit at91_spi_exit(void)
{
controller->SPI_CR = AT91C_SPI_SPIDIS; /* Disable SPI */
free_irq(AT91C_ID_SPI, 0);
}
EXPORT_SYMBOL(spi_access_bus);
EXPORT_SYMBOL(spi_release_bus);
EXPORT_SYMBOL(spi_transfer);
module_init(at91_spi_init);
module_exit(at91_spi_exit);
MODULE_LICENSE("GPL");