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This is a project for computer architecture at northeastern university

This project was made by Chris Canal and Nick Knaian

Name		Name	Last commit message	Last commit date
Latest commit History 31 Commits
gui/addmenu		gui/addmenu
tutorials		tutorials
verilog		verilog
work		work
2_to_1_MUX.v		2_to_1_MUX.v
2_to_1_MUX.v.bak		2_to_1_MUX.v.bak
2_to_1_MUX_tb.v		2_to_1_MUX_tb.v
2_to_1_MUX_tb.v.bak		2_to_1_MUX_tb.v.bak
ALU.v		ALU.v
ALU.v.bak		ALU.v.bak
ALUControl.v		ALUControl.v
ALUControl.v.bak		ALUControl.v.bak
ALUControl_tb.v		ALUControl_tb.v
ALUControl_tb.v.bak		ALUControl_tb.v.bak
ALU_tb.v		ALU_tb.v
ALU_tb.v.bak		ALU_tb.v.bak
And_gate.v		And_gate.v
And_gate.v.bak		And_gate.v.bak
And_gate_tb.v		And_gate_tb.v
And_gate_tb.v.bak		And_gate_tb.v.bak
FinalProjectPaperChrisCanalandNickKnaian.pdf		FinalProjectPaperChrisCanalandNickKnaian.pdf
Hw6.cr.mti		Hw6.cr.mti
Hw6.mpf		Hw6.mpf
MinMax.hexdump		MinMax.hexdump
Processor.v		Processor.v
Processor.v.bak		Processor.v.bak
Processor_tb.v		Processor_tb.v
Processor_tb.v.bak		Processor_tb.v.bak
README.txt		README.txt
Reg_32_bit.v		Reg_32_bit.v
Reg_32_bit.v.bak		Reg_32_bit.v.bak
Reg_32_bit_tb.v		Reg_32_bit_tb.v
Reg_32_bit_tb.v.bak		Reg_32_bit_tb.v.bak
Reg_File.v		Reg_File.v
Reg_File.v.bak		Reg_File.v.bak
Reg_file_tb.v		Reg_file_tb.v
Reg_file_tb.v.bak		Reg_file_tb.v.bak
Shift_left_two.v		Shift_left_two.v
Shift_left_two.v.bak		Shift_left_two.v.bak
Shift_left_two_jump.v		Shift_left_two_jump.v
Shift_left_two_jump.v.bak		Shift_left_two_jump.v.bak
Shift_left_two_jumpAddress.v		Shift_left_two_jumpAddress.v
Shift_left_two_jumpAddress.v.bak		Shift_left_two_jumpAddress.v.bak
Shift_left_two_jumpAddress_tb.v		Shift_left_two_jumpAddress_tb.v
Shift_left_two_jumpAddress_tb.v.bak		Shift_left_two_jumpAddress_tb.v.bak
Shift_left_two_jump_tb.v		Shift_left_two_jump_tb.v
Shift_left_two_tb.v		Shift_left_two_tb.v
Shift_left_two_tb.v.bak		Shift_left_two_tb.v.bak
Sign_extend.v		Sign_extend.v
Sign_extend.v.bak		Sign_extend.v.bak
Sign_extend_tb.v		Sign_extend_tb.v
Sign_extend_tb.v.bak		Sign_extend_tb.v.bak
TestProject.cr.mti		TestProject.cr.mti
TestProject.mpf		TestProject.mpf
Two_to_one_MUX.v		Two_to_one_MUX.v
Two_to_one_MUX.v.bak		Two_to_one_MUX.v.bak
Two_to_one_MUX_5bit.v		Two_to_one_MUX_5bit.v
Two_to_one_MUX_5bit.v.bak		Two_to_one_MUX_5bit.v.bak
Two_to_one_MUX_5bit_tb.v		Two_to_one_MUX_5bit_tb.v
Two_to_one_MUX_5bit_tb.v.bak		Two_to_one_MUX_5bit_tb.v.bak
Two_to_one_MUX_tb		Two_to_one_MUX_tb
Two_to_one_MUX_tb.v		Two_to_one_MUX_tb.v
Two_to_one_MUX_tb.v.bak		Two_to_one_MUX_tb.v.bak
controlUnit.v		controlUnit.v
controlUnit.v.bak		controlUnit.v.bak
controlUnit_tb.v		controlUnit_tb.v
controlUnit_tb.v.bak		controlUnit_tb.v.bak
memory.v		memory.v
memory.v.bak		memory.v.bak
readme.md		readme.md
transcript		transcript
vish_stacktrace.vstf		vish_stacktrace.vstf
vsim.wlf		vsim.wlf
wlft0qtim4		wlft0qtim4
wlft0ray2m		wlft0ray2m
wlft10w4fa		wlft10w4fa
wlft19731v		wlft19731v
wlft4vk13r		wlft4vk13r
wlft4zx64n		wlft4zx64n
wlft6qfebi		wlft6qfebi
wlft6xmv9s		wlft6xmv9s
wlfta086wr		wlfta086wr
wlftbynxt7		wlftbynxt7
wlftc45vd1		wlftc45vd1
wlftf0fr9h		wlftf0fr9h
wlftf2hqtf		wlftf2hqtf
wlftff6mbn		wlftff6mbn
wlfthhqs5f		wlfthhqs5f
wlfthj7ine		wlfthj7ine
wlftifzi5b		wlftifzi5b
wlftit8zeq		wlftit8zeq
wlftizh2xw		wlftizh2xw
wlftj3akq0		wlftj3akq0
wlftjx4t1b		wlftjx4t1b
wlftk8yz82		wlftk8yz82
wlftkat9rz		wlftkat9rz
wlftkh76r3		wlftkh76r3
wlftmd1cqm		wlftmd1cqm
wlftnfm17n		wlftnfm17n
wlftr14wmt		wlftr14wmt

chriscanal/examples

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