My diploma work done years ago to graduate as telecommunications engineer.

This project is made available in GitHub (repository) to provide to VHDL coders some more code snippets. It is actually implemented in French and translation is not planned, however, do not hesitate to contact me to get more explanations.

• code Source-code of the project

  • FPGA_Cpp Software implementation of various algorithms thus permit to validate corresponding VHDL implementations
  • FPGA_Debug Some VHDL code to test and ease the handling of the boards (e.g. pins assignement, ...)
  • FPGA_VHDL Pure-VHDL implementation of the embedded system, the main part of the project
  • FX2_Firmware Cypress FX2 firmware (unfinished work)
  • FX2_Logiciel_DDRAW The PC / receiver part of the demonstrator (unfinished work)
  • cleanup.bat and cleanup.sh Cleanup script (remove compilation's intermediate files)

• docs Some documentation (datasheets, boards, photos)
• report My diploma thesis

-----References ----------

• Cours de traitement d'images
• Cours de morphologie mathématique
• Comparison of Tracking Techniques
• Iris Recognition with CASIA Database
• 2D edge detection w.cost minimiz/snakes
• Canny Edge Detector by Chien-I Liao
• Wikipedia Canny edge detector
• Wikipedia HSL and HSV

• Altera Cyclone FPGA
• DigChip IC database
• National Semiconductor Main page
• RokEPXA board from EPFL (broken link) and SOC/ARM Module on FPGAi

• Microsoft Using Video Capture
• ONVERSITY Norme IEEE 754
• CSEE VHDL samples

Kind Regards,

David Fischer