/*
 **************************************************************************
 * FunctionName: imx219_liteon_enum_framesizes;
 * Description : NA;
 * Input       : NA;
 * Output      : NA;
 * ReturnValue : NA;
 * Other       : NA;
 **************************************************************************
*/
static int imx219_liteon_enum_framesizes(struct v4l2_frmsizeenum *framesizes)
{
	u32 max_index = ARRAY_SIZE(camera_framesizes) - 1;
	u32 this_max_index =   ARRAY_SIZE(imx219_liteon_framesizes) - 1;

	assert(framesizes);
	if(NULL == framesizes) {
		return -EINVAL;
	}

	print_debug("enter %s;", __func__);

	if (framesizes->index > max_index) {
		print_error("framesizes->index = %d error", framesizes->index);
		return -EINVAL;
	}

	if ((camera_framesizes[framesizes->index].width > imx219_liteon_framesizes[this_max_index].width)
		|| (camera_framesizes[framesizes->index].height > imx219_liteon_framesizes[this_max_index].height)) {
		print_error("framesizes->index = %d error", framesizes->index);
		return -EINVAL;
	}

	framesizes->type = V4L2_FRMSIZE_TYPE_DISCRETE;
	framesizes->discrete.width = imx219_liteon_framesizes[this_max_index].width;
	framesizes->discrete.height = imx219_liteon_framesizes[this_max_index].height;

	return 0;
}
/*
 * system init for baseboard usage. Will be called by mx31moboard init.
 */
void __init mx31moboard_smartbot_init(int board)
{
	printk(KERN_INFO "Initializing mx31smartbot peripherals\n");

	mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins),
		"smartbot");

	imx31_add_imx_uart1(&uart_pdata);

	switch (board) {
	case MX31SMARTBOT:
		mxc_register_device(&mxc_otg_udc_device, &usb_pdata);
		break;
	case MX31EYEBOT:
		smartbot_otg_host_init();
		break;
	default:
		printk(KERN_WARNING "Unknown board %d, USB OTG not initialized",
			board);
	}

	smartbot_resets_init();

	smartbot_cam_init();
	platform_add_devices(smartbot_cameras, ARRAY_SIZE(smartbot_cameras));
}
Example #3
0
static void __init omap3pandora_init(void)
{
	omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
	omap_hsmmc_init(omap3pandora_mmc);
	omap3pandora_i2c_init();
	pandora_wl1251_init();
	platform_add_devices(omap3pandora_devices,
			ARRAY_SIZE(omap3pandora_devices));
	omap_display_init(&pandora_dss_data);
	omap_serial_init();
	omap_sdrc_init(mt46h32m32lf6_sdrc_params,
				  mt46h32m32lf6_sdrc_params);
	spi_register_board_info(omap3pandora_spi_board_info,
			ARRAY_SIZE(omap3pandora_spi_board_info));
	omap_ads7846_init(1, OMAP3_PANDORA_TS_GPIO, 0, NULL);

	usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
	usbhs_init(&usbhs_bdata);

	usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
	usb_musb_init(NULL);
	gpmc_nand_init(&pandora_nand_data, NULL);

	/* Ensure SDRC pins are mux'd for self-refresh */
	omap_mux_init_signal("sdrc_cke0", OMAP_PIN_OUTPUT);
	omap_mux_init_signal("sdrc_cke1", OMAP_PIN_OUTPUT);
}
static int tegra3_get_core_floor_mv(int cpu_mv)
{
#if 0
	if (cpu_mv < 800)
		return  950;
	if (cpu_mv < 900)
		return 1000;
	if (cpu_mv < 1000)
		return 1100;
	if ((tegra_cpu_speedo_id() < 2) ||
	    (tegra_cpu_speedo_id() == 4) ||
	    (tegra_cpu_speedo_id() == 7) ||
	    (tegra_cpu_speedo_id() == 8))
		return 1200;
	if (cpu_mv < 1100)
		return 1200;
	if (cpu_mv <= 1250)
		return 1300;
#endif
	int i;
	
	for (i=0; i<ARRAY_SIZE(core_millivolts) && core_millivolts[i] < cpu_mv; i++);
	if (i<ARRAY_SIZE(core_millivolts)){
		return core_millivolts[i];
	}
	
	/* fail-safe */
	if (cpu_mv <= VDD_CPU_MAX)
		return 1300;

	BUG();
}
Example #5
0
int board_video_skip(void)
{
	int i;
	int ret;
	char const *panel = getenv("panel");
	if (!panel) {
		panel = displays[0].mode.name;
		printf("No panel detected: default to %s\n", panel);
		i = 0;
	} else {
		for (i = 0; i < ARRAY_SIZE(displays); i++) {
			if (!strcmp(panel, displays[i].mode.name))
				break;
		}
	}
	if (i < ARRAY_SIZE(displays)) {
		ret = mxs_lcd_panel_setup(displays[i].mode, displays[i].depth,
				    displays[i].lcdif_base_addr);
		if (!ret) {
			if (displays[i].enable)
				displays[i].enable(displays+i);
			printf("Display: %s (%ux%u)\n",
			       displays[i].mode.name,
			       displays[i].mode.xres,
			       displays[i].mode.yres);
		} else
			printf("LCD %s cannot be configured: %d\n",
			       displays[i].mode.name, ret);
	} else {
		printf("unsupported panel %s\n", panel);
		return -EINVAL;
	}

	return 0;
}
void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
{
	unsigned int count = entry_cnt;
	unsigned int tmp;

	for (; count > 0; count--)
		__raw_writel(exynos4_pmu_config[count - 1].val[mode],
				exynos4_pmu_config[count - 1].reg);

	if ((!soc_is_exynos4210()) && (exynos4_is_c2c_use())) {
		for (count = 0 ; count < ARRAY_SIZE(exynos4x12_c2c_pmu_conf) ; count++)
			__raw_writel(exynos4x12_c2c_pmu_conf[count].val[mode],
					exynos4x12_c2c_pmu_conf[count].reg);

		if (soc_is_exynos4212())
			__raw_writel(exynos4212_c2c_pmu_conf[0].val[mode],
					exynos4212_c2c_pmu_conf[0].reg);

		for (count = 0 ; count < ARRAY_SIZE(exynos4_config_for_c2c) ; count++) {
			tmp = __raw_readl(exynos4_config_for_c2c[count].reg);
			tmp |= exynos4_config_for_c2c[count].val;
			__raw_writel(tmp, exynos4_config_for_c2c[count].reg);
		}
	}
}
static int playpaq_wm8510_init(struct snd_soc_pcm_runtime *rtd)
{
	struct snd_soc_codec *codec = rtd->codec;
	struct snd_soc_dapm_context *dapm = &codec->dapm;
	int i;

	/*
	 * Add DAPM widgets
	 */
	for (i = 0; i < ARRAY_SIZE(playpaq_dapm_widgets); i++)
		snd_soc_dapm_new_control(dapm, &playpaq_dapm_widgets[i]);



	/*
	 * Setup audio path interconnects
	 */
	snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));



	/* always connected pins */
	snd_soc_dapm_enable_pin(dapm, "Int Mic");
	snd_soc_dapm_enable_pin(dapm, "Ext Spk");
	snd_soc_dapm_sync(dapm);



	/* Make CSB show PLL rate */
	snd_soc_dai_set_clkdiv(rtd->codec_dai, WM8510_OPCLKDIV,
				       WM8510_OPCLKDIV_1 | 4);

	return 0;
}
Example #8
0
static void __init smdkv210_machine_init(void)
{
	s3c_pm_init();

	smdkv210_dm9000_init();

	samsung_keypad_set_platdata(&smdkv210_keypad_data);
	s3c24xx_ts_set_platdata(&s3c_ts_platform);

	s3c_i2c0_set_platdata(NULL);
	s3c_i2c1_set_platdata(NULL);
	s3c_i2c2_set_platdata(NULL);
	i2c_register_board_info(0, smdkv210_i2c_devs0,
			ARRAY_SIZE(smdkv210_i2c_devs0));
	i2c_register_board_info(1, smdkv210_i2c_devs1,
			ARRAY_SIZE(smdkv210_i2c_devs1));
	i2c_register_board_info(2, smdkv210_i2c_devs2,
			ARRAY_SIZE(smdkv210_i2c_devs2));

	s3c_ide_set_platdata(&smdkv210_ide_pdata);

	s3c_fb_set_platdata(&smdkv210_lcd0_pdata);

	samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data);

	platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
}
Example #9
0
bool TestParseLBN() {
	const char *validStrings[] = {
		"/sce_lbn0x5fa0_size0x1428",
		"/sce_lbn7050_sizeee850",
		"/sce_lbn0x5eeeh_size0x234x",  // Check for trailing chars. See #7960.
		"/sce_lbneee__size434.",  // Check for trailing chars. See #7960.
	};
	int expectedResults[][2] = {
		{0x5fa0, 0x1428},
		{0x7050, 0xee850},
		{0x5eee, 0x234},
		{0xeee,  0x434},
	};
	const char *invalidStrings[] = {
		"/sce_lbn0x5fa0_sze0x1428",
		"",
		"//",
	};
	for (int i = 0; i < ARRAY_SIZE(validStrings); i++) {
		u32 startSector = 0, readSize = 0;
		// printf("testing %s\n", validStrings[i]);
		EXPECT_TRUE(parseLBN(validStrings[i], &startSector, &readSize));
		EXPECT_EQ_INT(startSector, expectedResults[i][0]);
		EXPECT_EQ_INT(readSize, expectedResults[i][1]);
	}
	for (int i = 0; i < ARRAY_SIZE(invalidStrings); i++) {
		u32 startSector, readSize;
		EXPECT_FALSE(parseLBN(invalidStrings[i], &startSector, &readSize));
	}
	return true;
}
Example #10
0
static void
i386obsd_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch)
{
    struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);

    /* Obviously OpenBSD is BSD-based.  */
    i386bsd_init_abi (info, gdbarch);

    /* OpenBSD has a different `struct reg'.  */
    tdep->gregset_reg_offset = i386obsd_r_reg_offset;
    tdep->gregset_num_regs = ARRAY_SIZE (i386obsd_r_reg_offset);
    tdep->sizeof_gregset = 16 * 4;

    /* OpenBSD uses -freg-struct-return by default.  */
    tdep->struct_return = reg_struct_return;

    /* OpenBSD uses a different memory layout.  */
    tdep->sigtramp_start = i386obsd_sigtramp_start_addr;
    tdep->sigtramp_end = i386obsd_sigtramp_end_addr;
    tdep->sigtramp_p = i386obsd_sigtramp_p;

    /* OpenBSD has a `struct sigcontext' that's different from the
       original 4.3 BSD.  */
    tdep->sc_reg_offset = i386obsd_sc_reg_offset;
    tdep->sc_num_regs = ARRAY_SIZE (i386obsd_sc_reg_offset);
}
Example #11
0
void pwm_set_voltage(unsigned int id, unsigned int voltage)
{
	int to;

	for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
		if (pwm_voltage_table[to][1] >= voltage) {
			break;
		}
	}
	if (to >= ARRAY_SIZE(pwm_voltage_table)) {
		to = ARRAY_SIZE(pwm_voltage_table) - 1;
	}
	switch (id) {
	case pwm_b:
		P_PWM_PWM_B = pwm_voltage_table[to][0];
		break;

	case pwm_d:
		P_PWM_PWM_D = pwm_voltage_table[to][0];
		break;
	default:
		break;
	}
	_udelay_(200);
}
Example #12
0
static int bq24192_therm_set_input_i_limit(const char *val,
					const struct kernel_param *kp)
{
	int ret;

	if (!the_chip)
		return -ENODEV;

	ret = param_set_int(val, kp);
	if (ret) {
		pr_err("failed to set input_limit_idx\n");
		return ret;
	}

	if (input_limit_idx >= ARRAY_SIZE(mitigate_tbl))
		input_limit_idx = ARRAY_SIZE(mitigate_tbl) - 1;

	if (!power_supply_is_system_supplied())
		return 0;

	schedule_delayed_work(&the_chip->therm_work,
			msecs_to_jiffies(2000));

	return 0;
}
static void wcd9xxx_irq_sync_unlock(struct irq_data *data)
{
	struct wcd9xxx_core_resource *wcd9xxx_res =
			irq_data_get_irq_chip_data(data);
	int i;

	if ((ARRAY_SIZE(wcd9xxx_res->irq_masks_cur) >
			WCD9XXX_MAX_IRQ_REGS) ||
		(ARRAY_SIZE(wcd9xxx_res->irq_masks_cache) >
			WCD9XXX_MAX_IRQ_REGS)) {
			pr_err("%s: Array Size out of bound\n", __func__);
			 return;
	}
	if (!wcd9xxx_res->codec_reg_write) {
		pr_err("%s: Codec reg write callback function not defined\n",
				__func__);
		return;
	}

	for (i = 0; i < ARRAY_SIZE(wcd9xxx_res->irq_masks_cur); i++) {
		if (wcd9xxx_res->irq_masks_cur[i] !=
					wcd9xxx_res->irq_masks_cache[i]) {

			wcd9xxx_res->irq_masks_cache[i] =
					wcd9xxx_res->irq_masks_cur[i];
			wcd9xxx_res->codec_reg_write(wcd9xxx_res,
					  WCD9XXX_A_INTR_MASK0 + i,
					  wcd9xxx_res->irq_masks_cur[i]);
		}
	}

	mutex_unlock(&wcd9xxx_res->irq_lock);
}
Example #14
0
// Note: The caller must free the buffer obtained from this function.
static char *
get_control_flags (CControlFlags flags)
{
	int i;

	const char *delimiter = ", ";
	const char *names[] = {
		"CAN_READ",
		"CAN_WRITE",
		"CAN_NOTIFY",
		"<Unknown>",
		"<Unknown>",
		"<Unknown>",
		"<Unknown>",
		"<Unknown>",
		"IS_CUSTOM",
		"IS_RELATIVE",
		"IS_ACTION",
	};
	char buffer[14 * ARRAY_SIZE(names)];		// 14 = maximum name length + strlen(delimiter)
	memset(buffer, 0, sizeof(buffer));

	for(i = 0; i < ARRAY_SIZE(names); i++) {
		if(flags & (1 << i)) {
			strcat(buffer, names[i]);
			if(flags >= (1 << (i + 1)))
				strcat(buffer, delimiter);
		}
	}

	return strdup(buffer);
}
int main(void)
{
	int array1[] = {1, 2, 3, 7, 9, 10};
	int array2[] = {4, 5, 6, 8};
	
	double result;
	int i;

	result = findMedianSortedArrays(array1, ARRAY_SIZE(array1), array2, ARRAY_SIZE(array2));
	
	for(i = 0; i < ARRAY_SIZE(array1); i++)
	{
		printf("%d ", array1[i]);
	}
	printf("\n");

	for(i = 0; i < ARRAY_SIZE(array2); i++)
	{
		printf("%d ", array2[i]);
	}
	printf("\n");

	printf("result = %f\n", result);

	return 0;

}
Example #16
0
static int aic31xx_device_init(struct aic31xx_priv *aic31xx)
{
	int ret, i;

	dev_set_drvdata(aic31xx->dev, aic31xx);

	if (dev_get_platdata(aic31xx->dev))
		memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev),
		       sizeof(aic31xx->pdata));
	else if (aic31xx->dev->of_node)
		aic31xx_pdata_from_of(aic31xx);

	if (aic31xx->pdata.gpio_reset) {
		ret = devm_gpio_request_one(aic31xx->dev,
					    aic31xx->pdata.gpio_reset,
					    GPIOF_OUT_INIT_HIGH,
					    "aic31xx-reset-pin");
		if (ret < 0) {
			dev_err(aic31xx->dev, "not able to acquire gpio\n");
			return ret;
		}
	}

	for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
		aic31xx->supplies[i].supply = aic31xx_supply_names[i];

	ret = devm_regulator_bulk_get(aic31xx->dev,
				      ARRAY_SIZE(aic31xx->supplies),
				      aic31xx->supplies);
	if (ret != 0)
		dev_err(aic31xx->dev, "Failed to request supplies: %d\n", ret);

	return ret;
}
Example #17
0
void __init tegra_soc_init_dvfs(void)
{
	int i;
	struct clk *c;
	struct dvfs *d;
	int process_id;
	int ret;
	int cpu_process_id = tegra_cpu_process_id();
	int core_process_id = tegra_core_process_id();
	int speedo_id = tegra_soc_speedo_id();

	BUG_ON(speedo_id >= ARRAY_SIZE(cpu_speedo_nominal_millivolts));
	tegra2_dvfs_rail_vdd_cpu.nominal_millivolts =
		cpu_speedo_nominal_millivolts[speedo_id];
	BUG_ON(speedo_id >= ARRAY_SIZE(core_speedo_nominal_millivolts));
	tegra2_dvfs_rail_vdd_core.nominal_millivolts =
		core_speedo_nominal_millivolts[speedo_id];
	tegra2_dvfs_rail_vdd_aon.nominal_millivolts =
		core_speedo_nominal_millivolts[speedo_id];

	tegra_dvfs_init_rails(tegra2_dvfs_rails, ARRAY_SIZE(tegra2_dvfs_rails));
	tegra_dvfs_add_relationships(tegra2_dvfs_relationships,
		ARRAY_SIZE(tegra2_dvfs_relationships));
	/*
	 * VDD_CORE must always be at least 50 mV higher than VDD_CPU
	 * Fill out cpu_core_millivolts based on cpu_millivolts
	 */
	for (i = 0; i < ARRAY_SIZE(dvfs_init); i++) {
		d = &dvfs_init[i];

		process_id = strcmp(d->clk_name, "cpu") ?
			core_process_id : cpu_process_id;
		if ((d->process_id != -1 && d->process_id != process_id) ||
		    (d->speedo_id != -1 && d->speedo_id != speedo_id)) {
			pr_debug("tegra_dvfs: rejected %s speedo %d,"
				" process %d\n", d->clk_name, d->speedo_id,
				d->process_id);
			continue;
		}

		c = tegra_get_clock_by_name(d->clk_name);

		if (!c) {
			pr_debug("tegra_dvfs: no clock found for %s\n",
				d->clk_name);
			continue;
		}

		ret = tegra_enable_dvfs_on_clk(c, d);
		if (ret)
			pr_err("tegra_dvfs: failed to enable dvfs on %s\n",
				c->name);
	}

	if (tegra_dvfs_core_disabled)
		tegra_dvfs_rail_disable(&tegra2_dvfs_rail_vdd_core);

	if (tegra_dvfs_cpu_disabled)
		tegra_dvfs_rail_disable(&tegra2_dvfs_rail_vdd_cpu);
}
Example #18
0
static int aic31xx_add_widgets(struct snd_soc_codec *codec)
{
	struct snd_soc_dapm_context *dapm = &codec->dapm;
	struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
	int ret = 0;

	if (aic31xx->pdata.codec_type & AIC31XX_STEREO_CLASS_D_BIT) {
		ret = snd_soc_dapm_new_controls(
			dapm, aic311x_dapm_widgets,
			ARRAY_SIZE(aic311x_dapm_widgets));
		if (ret)
			return ret;

		ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map,
					      ARRAY_SIZE(aic311x_audio_map));
		if (ret)
			return ret;
	} else {
		ret = snd_soc_dapm_new_controls(
			dapm, aic310x_dapm_widgets,
			ARRAY_SIZE(aic310x_dapm_widgets));
		if (ret)
			return ret;

		ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map,
					      ARRAY_SIZE(aic310x_audio_map));
		if (ret)
			return ret;
	}

	return 0;
}
static int __init exynos4_pmu_init(void)
{
	unsigned int i;

	if(!soc_is_exynos4210())
		exynos4_reset_assert_ctrl(1);

	if (soc_is_exynos4210()) {
		exynos4_pmu_config = exynos4210_pmu_config;
		entry_cnt = ARRAY_SIZE(exynos4210_pmu_config);
		printk(KERN_INFO "%s: PMU supports 4210(%d)\n",
					__func__, entry_cnt);
	} else if (soc_is_exynos4212()) {
		exynos4_pmu_config = exynos4212_pmu_config;
		entry_cnt = ARRAY_SIZE(exynos4212_pmu_config);
		printk(KERN_INFO "%s: PMU supports 4212(%d)\n",
					__func__, entry_cnt);
	} else if (soc_is_exynos4412()) {
		exynos4_pmu_config = exynos4412_pmu_config;
		entry_cnt = ARRAY_SIZE(exynos4412_pmu_config);
		printk(KERN_INFO "%s: PMU supports 4412(%d)\n",
					__func__, entry_cnt);
	} else {
		printk(KERN_INFO "%s: PMU not supported\n", __func__);
	}

	return 0;
}
Example #20
0
static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
				  int clk_id, unsigned int freq, int dir)
{
	struct snd_soc_codec *codec = codec_dai->codec;
	struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
	int i;

	dev_dbg(codec->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
		__func__, clk_id, freq, dir);

	for (i = 1; freq/i > 20000000 && i < 8; i++)
		;
	if (freq/i > 20000000) {
		dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n",
			__func__, freq);
			return -EINVAL;
	}
	aic31xx->p_div = i;

	for (i = 0; i < ARRAY_SIZE(aic31xx_divs) &&
		     aic31xx_divs[i].mclk_p != freq/aic31xx->p_div; i++)
		;
	if (i == ARRAY_SIZE(aic31xx_divs)) {
		dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
			__func__, freq);
		return -EINVAL;
	}

	/* set clock on MCLK, BCLK, or GPIO1 as PLL input */
	snd_soc_update_bits(codec, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
			    clk_id << AIC31XX_PLL_CLKIN_SHIFT);

	aic31xx->sysclk = freq;
	return 0;
}
static void tegra_adjust_cpu_mvs(int mvs)
{
	int i;

	mutex_lock(&dvfs_lock);

	pr_info("tegra_adjust_cpu_mvs: mvs %d\n", mvs);
	BUG_ON(ARRAY_SIZE(cpu_millivolts) != ARRAY_SIZE(cpu_millivolts_orig));
	
	curr_cpu_vdd_change = mvs;
	for (i = 0; i < ARRAY_SIZE(cpu_millivolts); i++){
		int old_val = cpu_millivolts_orig[i];
		int new_val = old_val + mvs;
		
		if (new_val < VDD_CPU_MIN)
			new_val = VDD_CPU_MIN;
		 
		if(new_val > VDD_CPU_MAX)
			new_val = VDD_CPU_MAX;
						
		cpu_millivolts[i] = new_val;
	}
	
	mutex_unlock(&dvfs_lock);
}
Example #22
0
static int aic31xx_power_on(struct snd_soc_codec *codec)
{
	struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
	int ret = 0;

	ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies),
				    aic31xx->supplies);
	if (ret)
		return ret;

	if (gpio_is_valid(aic31xx->pdata.gpio_reset)) {
		gpio_set_value(aic31xx->pdata.gpio_reset, 1);
		udelay(100);
	}
	regcache_cache_only(aic31xx->regmap, false);
	ret = regcache_sync(aic31xx->regmap);
	if (ret != 0) {
		dev_err(codec->dev,
			"Failed to restore cache: %d\n", ret);
		regcache_cache_only(aic31xx->regmap, true);
		regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
				       aic31xx->supplies);
		return ret;
	}
	return 0;
}
Example #23
0
static void setup_iomux_fec(int fec_id)
{
	if (0 == fec_id)
		imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
	else
		imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads));
}
Example #24
0
int board_init(void)
{
    unsigned int temp;
#ifndef CONFIG_USE_IRQ
    irq_init();
#endif

    /* arch number of the board */
    gd->bd->bi_arch_number = MACH_TYPE_OMAPL138_LCDK;

    /* address of boot parameters */
    gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;


    /* setup the SUSPSRC for ARM to control emulation suspend */
    writel(readl(&davinci_syscfg_regs->suspsrc) &
           ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
             DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
             DAVINCI_SYSCFG_SUSPSRC_UART2),
           &davinci_syscfg_regs->suspsrc);

    /* configure pinmux settings */
    if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
        return 1;

#ifdef CONFIG_NAND_DAVINCI
    /*
     * NAND CS setup - cycle counts based on da850evm NAND timings in the
     * Linux kernel @ 25MHz EMIFA
     */
    writel((DAVINCI_ABCR_WSETUP(15) |
            DAVINCI_ABCR_WSTROBE(63) |
            DAVINCI_ABCR_WHOLD(7) |
            DAVINCI_ABCR_RSETUP(15) |
            DAVINCI_ABCR_RSTROBE(63) |
            DAVINCI_ABCR_RHOLD(7) |
            DAVINCI_ABCR_TA(3) |
            DAVINCI_ABCR_ASIZE_16BIT),
           &davinci_emif_regs->ab2cr); /* CS3 */
#endif


#ifdef CONFIG_DAVINCI_MMC
    if (davinci_configure_pin_mux(mmc0_pins, ARRAY_SIZE(mmc0_pins)) != 0)
        return 1;
#endif

#ifdef CONFIG_DRIVER_TI_EMAC
    if (davinci_configure_pin_mux(emac_pins, ARRAY_SIZE(emac_pins)) != 0)
        return 1;
    davinci_emac_mii_mode_sel(HAS_RMII);
#endif /* CONFIG_DRIVER_TI_EMAC */

    /* enable the console UART */
    writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
            DAVINCI_UART_PWREMU_MGMT_UTRST),
           &davinci_uart2_ctrl_regs->pwremu_mgmt);

    return 0;
}
Example #25
0
SR_PRIV int zp_set_samplerate(struct dev_context *devc, uint64_t samplerate)
{
	int i;

	for (i = 0; ARRAY_SIZE(samplerates_200); i++)
		if (samplerate == samplerates_200[i])
			break;

	if (i == ARRAY_SIZE(samplerates_200) || samplerate > devc->max_samplerate) {
		sr_err("Unsupported samplerate: %" PRIu64 "Hz.", samplerate);
		return SR_ERR_ARG;
	}

	sr_info("Setting samplerate to %" PRIu64 "Hz.", samplerate);

	if (samplerate >= SR_MHZ(1))
		analyzer_set_freq(samplerate / SR_MHZ(1), FREQ_SCALE_MHZ);
	else if (samplerate >= SR_KHZ(1))
		analyzer_set_freq(samplerate / SR_KHZ(1), FREQ_SCALE_KHZ);
	else
		analyzer_set_freq(samplerate, FREQ_SCALE_HZ);

	devc->cur_samplerate = samplerate;

	return SR_OK;
}
Example #26
0
File: mcbsp.c Project: 020gzh/linux
static ssize_t dma_op_mode_store(struct device *dev,
				struct device_attribute *attr,
				const char *buf, size_t size)
{
	struct omap_mcbsp *mcbsp = dev_get_drvdata(dev);
	const char * const *s;
	int i = 0;

	for (s = &dma_op_modes[i]; i < ARRAY_SIZE(dma_op_modes); s++, i++)
		if (sysfs_streq(buf, *s))
			break;

	if (i == ARRAY_SIZE(dma_op_modes))
		return -EINVAL;

	spin_lock_irq(&mcbsp->lock);
	if (!mcbsp->free) {
		size = -EBUSY;
		goto unlock;
	}
	mcbsp->dma_op_mode = i;

unlock:
	spin_unlock_irq(&mcbsp->lock);

	return size;
}
Example #27
0
static bool ath_regd_is_eeprom_valid(struct ath_regulatory *reg)
{
	u16 rd = ath_regd_get_eepromRD(reg);
	int i;

	if (rd & COUNTRY_ERD_FLAG) {
		/* EEPROM value is a country code */
		u16 cc = rd & ~COUNTRY_ERD_FLAG;
		printk(KERN_DEBUG
		       "ath: EEPROM indicates we should expect "
			"a country code\n");
		for (i = 0; i < ARRAY_SIZE(allCountries); i++)
			if (allCountries[i].countryCode == cc)
				return true;
	} else {
		/* EEPROM value is a regpair value */
		if (rd != CTRY_DEFAULT)
			printk(KERN_DEBUG "ath: EEPROM indicates we "
			       "should expect a direct regpair map\n");
		for (i = 0; i < ARRAY_SIZE(regDomainPairs); i++)
			if (regDomainPairs[i].regDmnEnum == rd)
				return true;
	}
	printk(KERN_DEBUG
		 "ath: invalid regulatory domain/country code 0x%x\n", rd);
	return false;
}
Example #28
0
static void __init _mx1_clocks_init(unsigned long fref)
{
	clk[IMX1_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
	clk[IMX1_CLK_CLK32] = imx_obtain_fixed_clock("clk32", fref);
	clk[IMX1_CLK_CLK16M_EXT] = imx_clk_fixed("clk16m_ext", 16000000);
	clk[IMX1_CLK_CLK16M] = imx_clk_gate("clk16m", "clk16m_ext", CCM_CSCR, 17);
	clk[IMX1_CLK_CLK32_PREMULT] = imx_clk_fixed_factor("clk32_premult", "clk32", 512, 1);
	clk[IMX1_CLK_PREM] = imx_clk_mux("prem", CCM_CSCR, 16, 1, prem_sel_clks, ARRAY_SIZE(prem_sel_clks));
	clk[IMX1_CLK_MPLL] = imx_clk_pllv1("mpll", "clk32_premult", CCM_MPCTL0);
	clk[IMX1_CLK_MPLL_GATE] = imx_clk_gate("mpll_gate", "mpll", CCM_CSCR, 0);
	clk[IMX1_CLK_SPLL] = imx_clk_pllv1("spll", "prem", CCM_SPCTL0);
	clk[IMX1_CLK_SPLL_GATE] = imx_clk_gate("spll_gate", "spll", CCM_CSCR, 1);
	clk[IMX1_CLK_MCU] = imx_clk_divider("mcu", "clk32_premult", CCM_CSCR, 15, 1);
	clk[IMX1_CLK_FCLK] = imx_clk_divider("fclk", "mpll_gate", CCM_CSCR, 15, 1);
	clk[IMX1_CLK_HCLK] = imx_clk_divider("hclk", "spll_gate", CCM_CSCR, 10, 4);
	clk[IMX1_CLK_CLK48M] = imx_clk_divider("clk48m", "spll_gate", CCM_CSCR, 26, 3);
	clk[IMX1_CLK_PER1] = imx_clk_divider("per1", "spll_gate", CCM_PCDR, 0, 4);
	clk[IMX1_CLK_PER2] = imx_clk_divider("per2", "spll_gate", CCM_PCDR, 4, 4);
	clk[IMX1_CLK_PER3] = imx_clk_divider("per3", "spll_gate", CCM_PCDR, 16, 7);
	clk[IMX1_CLK_CLKO] = imx_clk_mux("clko", CCM_CSCR, 29, 3, clko_sel_clks, ARRAY_SIZE(clko_sel_clks));
	clk[IMX1_CLK_UART3_GATE] = imx_clk_gate("uart3_gate", "hclk", SCM_GCCR, 6);
	clk[IMX1_CLK_SSI2_GATE] = imx_clk_gate("ssi2_gate", "hclk", SCM_GCCR, 5);
	clk[IMX1_CLK_BROM_GATE] = imx_clk_gate("brom_gate", "hclk", SCM_GCCR, 4);
	clk[IMX1_CLK_DMA_GATE] = imx_clk_gate("dma_gate", "hclk", SCM_GCCR, 3);
	clk[IMX1_CLK_CSI_GATE] = imx_clk_gate("csi_gate", "hclk", SCM_GCCR, 2);
	clk[IMX1_CLK_MMA_GATE] = imx_clk_gate("mma_gate", "hclk", SCM_GCCR, 1);
	clk[IMX1_CLK_USBD_GATE] = imx_clk_gate("usbd_gate", "clk48m", SCM_GCCR, 0);

	imx_check_clocks(clk, ARRAY_SIZE(clk));
}
Example #29
0
static void __init common_setup(unsigned usb_power_gpio, bool sec_ethernet)
{
    u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);

    /* disable PHY_SWAP and PHY_ADDR_SWAP bits */
    ath79_setup_ar933x_phy4_switch(false, false);

    ath79_register_m25p80(&tl_wr703n_flash_data);
    ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr703n_leds_gpio),
                             tl_wr703n_leds_gpio);
    ath79_register_gpio_keys_polled(-1, TL_WR703N_KEYS_POLL_INTERVAL,
                                    ARRAY_SIZE(tl_wr703n_gpio_keys),
                                    tl_wr703n_gpio_keys);

    gpio_request_one(usb_power_gpio,
                     GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
                     "USB power");
    ath79_register_usb();

    ath79_register_mdio(0, 0x0);
    ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
    ath79_register_eth(0);

    if (sec_ethernet)
    {
        ath79_init_mac(ath79_eth1_data.mac_addr, mac, -1);
        ath79_register_eth(1);
    }
    tplink_register_builtin_wmac1(0x1000, mac, 0);
}
Example #30
0
static void rds_stats_info(struct socket *sock, unsigned int len,
			   struct rds_info_iterator *iter,
			   struct rds_info_lengths *lens)
{
	struct rds_statistics stats = {0, };
	uint64_t *src;
	uint64_t *sum;
	size_t i;
	int cpu;
	unsigned int avail;

	avail = len / sizeof(struct rds_info_counter);

	if (avail < ARRAY_SIZE(rds_stat_names)) {
		avail = 0;
		goto trans;
	}

	for_each_online_cpu(cpu) {
		src = (uint64_t *)&(per_cpu(rds_stats, cpu));
		sum = (uint64_t *)&stats;
		for (i = 0; i < sizeof(stats) / sizeof(uint64_t); i++)
			*(sum++) += *(src++);
	}

	rds_stats_info_copy(iter, (uint64_t *)&stats, rds_stat_names,
			    ARRAY_SIZE(rds_stat_names));
	avail -= ARRAY_SIZE(rds_stat_names);

trans:
	lens->each = sizeof(struct rds_info_counter);
	lens->nr = rds_trans_stats_info_copy(iter, avail) +
		   ARRAY_SIZE(rds_stat_names);
}