//////////////////////////////////////////////////// // 功能: 延迟N个豪秒 // 输入: // 输出: // 返回: // 说明: //////////////////////////////////////////////////// static void dma_init(unsigned int channel, char mode) { unsigned int group, data; #ifdef KPRINTF_DEF kprintf("dma init channle = %d\n",channel); #endif group = channel / HALF_DMA_NUM; SETREG32(A_DMA_DMAC(group), (DMAC_DMA_EN | DMAC_FAST_AIC) ); SETREG32(A_DMA_DCKE(group), (1 << (channel - group * HALF_DMA_NUM)) ); OUTREG32(A_DMA_DCS(channel), DCS_NDES ); if (mode) { data = DCM_SAI | DCM_SP_32BIT | DCM_DP_16BIT | DCM_TSZ_16BYTE | DCM_RDIL_IGN | DCM_TRANS_INTR_EN; OUTREG32(A_DMA_DCM(channel), data); OUTREG32(A_DMA_DRT(channel), DRT_AIC_TX); } else { data = DCM_DAI | DCM_SP_16BIT | DCM_DP_32BIT | DCM_TSZ_16BYTE | DCM_RDIL_IGN; OUTREG32(A_DMA_DCM(channel), data); OUTREG32(A_DMA_DRT(channel), DRT_AIC_RX); } }
void dma_copy_nowait(void *tar,void *src,int size) { int timeout = 0x1000000; while ((!(INREG32(A_DMA_DCS(DMA_CPY_CHANNEL)) & DCS_TT)) && (timeout--)); CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_CTE); OUTREG32(A_DMA_DSA(DMA_CPY_CHANNEL), PHYSADDR((unsigned long)src)); OUTREG32(A_DMA_DTA(DMA_CPY_CHANNEL), PHYSADDR((unsigned long)tar)); OUTREG32(A_DMA_DTC(DMA_CPY_CHANNEL), size / 32); OUTREG32(A_DMA_DRT(DMA_CPY_CHANNEL), DRT_AUTO); OUTREG32(A_DMA_DCM(DMA_CPY_CHANNEL), (DCM_SAI| DCM_DAI | DCM_SP_32BIT | DCM_DP_32BIT | DCM_TSZ_32BYTE)); CLRREG32(A_DMA_DCS(DMA_CPY_CHANNEL),(DCS_TT)); SETREG32(A_DMA_DCS(DMA_CPY_CHANNEL), DCS_CTE | DCS_NDES); }
//////////////////////////////////////////////////// // 功能: 读取DMA状态 // 输入: // 输出: // 返回: // 说明: //////////////////////////////////////////////////// void GetDmaInfo() { unsigned int channel; channel = PLAYBACK_CHANNEL; for(channel= 0; channel < 4 ; channel++) { kprintf("DMA CHANNEL = %d\n",channel); kprintf("status = %x, count = %x\n",INREG32(A_DMA_DCM(channel)),INREG32(A_DMA_DTC(channel))); kprintf("control = %x,irq = %x\n",INREG32(A_DMA_DCS(channel)),INREG32(A_DMA_DIRQP(channel/6))); kprintf("source addr = %x, destion addr = %x\n",INREG32(A_DMA_DSA(channel)),INREG32(A_DMA_DTA(channel))); kprintf("DRT = %x, DMAC = %x, DCKE = %x\n",INREG32(A_DMA_DRT(channel)),INREG32(A_DMA_DMAC(0)),INREG32(A_DMA_DCKE(0))); } kprintf("\nDMA interrupt count = %d\n",interrupt_count); kprintf("aic register = %x\n",INREG32(A_CPM_CLKGR)); kprintf("dma register = %x\n\n",INREG32(INTC_IMR)); kprintf("======== aic status ========\n"); kprintf("AIC I2S/MSB-justified Control Register I2SCR = %x\n",REG_AIC_I2SCR); kprintf("AIC Controller FIFO Status Register AICSR = %x\n",REG_AIC_SR); kprintf("AIC AC-link Status Register ACSR = %x\n",REG_AIC_ACSR); kprintf("AIC I2S/MSB-justified Status Register I2SSR = %x\n\n",REG_AIC_I2SSR); kprintf("======== codec status ========\n"); kprintf("Audio Interface Control, Software Write = %x\n",codec_reg_read(A_CODEC_AICR)); kprintf("Control Register 1 = %x\n",codec_reg_read(A_CODEC_CR1)); kprintf("Control Register 2 = %x\n",codec_reg_read(A_CODEC_CR2)); kprintf("Control Clock Register 1 = %x\n",codec_reg_read(A_CODEC_CCR1)); kprintf("Control Clock Register 2 = %x\n",codec_reg_read(A_CODEC_CCR2)); kprintf("Power Mode Register 1 = %x\n",codec_reg_read(A_CODEC_PMR1)); kprintf("Power Mode Register 2 = %x\n",codec_reg_read(A_CODEC_PMR2)); kprintf("Control Ramp Register = %x\n",codec_reg_read(A_CODEC_CRR)); kprintf("Interrupt Control Register = %x\n",codec_reg_read(A_CODEC_ICR)); kprintf("Interrupt Flag Register = %x\n",codec_reg_read(A_CODEC_IFR)); kprintf("Control Gain Register 1 = %x\n",codec_reg_read(A_CODEC_CGR1)); kprintf("Control Gain Register 2 = %x\n",codec_reg_read(A_CODEC_CGR2)); kprintf("Control Gain Register 3 = %x\n",codec_reg_read(A_CODEC_CGR3)); kprintf("Control Gain Register 4 = %x\n",codec_reg_read(A_CODEC_CGR4)); kprintf("Control Gain Register 5 = %x\n",codec_reg_read(A_CODEC_CGR5)); kprintf("Control Gain Register 6 = %x\n",codec_reg_read(A_CODEC_CGR6)); kprintf("Control Gain Register 7 = %x\n",codec_reg_read(A_CODEC_CGR7)); kprintf("Control Gain Register 8 = %x\n",codec_reg_read(A_CODEC_CGR8)); kprintf("Control Gain Register 9 = %x\n",codec_reg_read(A_CODEC_CGR9)); kprintf("Control Gain Register 10 = %x\n",codec_reg_read(A_CODEC_CGR10)); }
void dma_nand_set_wait(void *tar,unsigned char src,unsigned int size) { unsigned int setdata[16]; unsigned int *ptemp; ptemp = (unsigned int *)UNCACHE(((unsigned int)(&setdata)+ 31)& (~31)); *ptemp = (unsigned int) ((src << 24) | (src << 16) | (src << 8) | src); if(((unsigned int)tar < 0xa0000000) && size) dma_cache_wback_inv((unsigned long)tar, size); CLRREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL), DCS_CTE); OUTREG32(A_DMA_DSA(DMA_NAND_COPY_CHANNEL), PHYSADDR((unsigned long)ptemp)); OUTREG32(A_DMA_DTA(DMA_NAND_COPY_CHANNEL), PHYSADDR((unsigned long)tar)); OUTREG32(A_DMA_DTC(DMA_NAND_COPY_CHANNEL), size / 32); OUTREG32(A_DMA_DRT(DMA_NAND_COPY_CHANNEL), DRT_AUTO); OUTREG32(A_DMA_DCM(DMA_NAND_COPY_CHANNEL),(DCM_DAI | DCM_SP_32BIT | DCM_DP_32BIT| DCM_TSZ_32BYTE)); CLRREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL),(DCS_TT)); SETREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL), DCS_CTE | DCS_NDES); while (!(INREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL)) & DCS_TT)); }
void yuv_copy_nowait(unsigned int *tar,unsigned int *src,int *t_stride,int *s_stride,int *size,int *line) { int i; while (!(INREG32(A_DMA_DCS(DMA_STRIDE_CPY_CHANNEL)) & DCS_CT) ); //error for(i = 0;i < 3;i++) { g_desc[8*i+1] = PHYSADDR(src[i]); g_desc[8*i+2] = PHYSADDR(tar[i]); g_desc[8*i+3] = (((unsigned int)&g_desc[8 * (i + 1)] & 0xff0)<<20 ) | ((*(line + i))<<16) | (*(size + i) ); g_desc[8*i+4] = ((*(t_stride + i)) << 16) | (*(s_stride + i)); } OUTREG32(A_DMA_DDA(DMA_STRIDE_CPY_CHANNEL),PHYSADDR(g_desc)); OUTREG32(A_DMA_DRT(DMA_STRIDE_CPY_CHANNEL), DRT_AUTO); CLRREG32(A_DMA_DCS(DMA_STRIDE_CPY_CHANNEL),(DCS_TT | DCS_CT)); OUTREG32(A_DMA_DDRS(DMA_STRIDE_CPY_CHANNEL / 6), (1 << (DMA_STRIDE_CPY_CHANNEL % 6)));//add SETREG32(A_DMA_DCS(DMA_STRIDE_CPY_CHANNEL), DCS_CTE); }
void dma_nand_copy_wait(void *tar,void *src,int size) { int timeout = 0x1000000; if(((unsigned int)src < 0xa0000000) && size) dma_cache_wback_inv((unsigned long)src, size); if(((unsigned int)tar < 0xa0000000) && size) dma_cache_wback_inv((unsigned long)tar, size); CLRREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL), DCS_CTE); OUTREG32(A_DMA_DSA(DMA_NAND_COPY_CHANNEL), PHYSADDR((unsigned long)src)); OUTREG32(A_DMA_DTA(DMA_NAND_COPY_CHANNEL), PHYSADDR((unsigned long)tar)); OUTREG32(A_DMA_DTC(DMA_NAND_COPY_CHANNEL), size / 32); OUTREG32(A_DMA_DRT(DMA_NAND_COPY_CHANNEL), DRT_AUTO); OUTREG32(A_DMA_DCM(DMA_NAND_COPY_CHANNEL), (DCM_SAI| DCM_DAI | DCM_SP_32BIT | DCM_DP_32BIT | DCM_TSZ_32BYTE)); CLRREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL),(DCS_TT)); SETREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL), DCS_CTE | DCS_NDES); while ((!(INREG32(A_DMA_DCS(DMA_NAND_COPY_CHANNEL)) & DCS_TT)) && (timeout--)); }