void hdlc_test(void)
{
    u8_t data;

    // Enable RS-485 PIO for loopback operation
    BIT_SET_HI(PORT_RS485_TX_EN_O, BIT_RS485_TX_EN_O);
    BIT_SET_HI(DDR_RS485_TX_EN_O, BIT_RS485_TX_EN_O);

    BIT_SET_LO(PORT_RS485_RX_EN_O, BIT_RS485_RX_EN_O);
    BIT_SET_HI(DDR_RS485_RX_EN_O, BIT_RS485_RX_EN_O);

    // Initialise modules
    uart0_init();
    uart1_init();
    printf_init();
    hdlc_init(&hdlc_on_rx_frame);

    // Enable global interrupts
    sei();
        
    // Send an HDLC packet
    data = 0x55;
    hdlc_tx_frame(&data,1);

    // Process received data
    for(;;)
    {
        if(uart1_get_rx_byte(&data))
        {
            PRINTF("%02X ", data);
            // Feed received data to HDLC layer
            hdlc_on_rx_byte(data);
        }
    }
}
/* _____GLOBAL FUNCTIONS_____________________________________________________ */
void spi_init(void)
{
    // Enable SPI pins
    BIT_SET_HI(PORT_SPI,   BIT_SPI_SS);
    BIT_SET_LO(DDR_SPI,    BIT_SPI_SS);

    BIT_SET_HI(PORT_SPI,   BIT_SPI_SCK);
    BIT_SET_HI(DDR_SPI,    BIT_SPI_SCK);

    BIT_SET_HI(PORT_SPI,   BIT_SPI_MOSI);
    BIT_SET_HI(DDR_SPI,    BIT_SPI_MOSI);

    BIT_SET_LO(PORT_SPI,   BIT_SPI_MISO);
    BIT_SET_LO(DDR_SPI,    BIT_SPI_MISO);

    // Configure and enable SPI peripheral
    SPCR =  (0<<SPIE)|(1<<SPE)|(0<<DORD)|(1<<MSTR)
           |(0<<CPOL)|(0<<CPHA)|(0<<SPR1)|(0<<SPR0);
    SPSR =  (0<<SPI2X);
}
Example #3
0
u08 CHandler::test() {
  u08 cca, cca_cnt, mode;
  cca = 0;
  cca_cnt = 0;

  BIT_SET_LO(PORTD, 5);
  _delay_us(10);
  BIT_SET_HI(PORTD, 5);

  mode = cc1101->readReg(CC1101_MARCSTATE, CC1101_STATUS_REGISTER) & 0x1F;
  if (mode == MARC_STATE_TXFIFO_UV) {
    cc1101->cmdStrobe(CC1101_SFTX);
  }
  if (mode == MARC_STATE_RXFIFO_OV) {
    cc1101->cmdStrobe(CC1101_SFRX);
  }

  // ================= wait for IDLE MODE ==================
  if ((mode == MARC_STATE_IDLE || mode == MARC_STATE_RX)) {
    cca_cnt = 0;
    // ================= SET RX MODE==========================
    cc1101->cmdStrobe(CC1101_SRX);
    // =================== wait 800us for RX MODE ============
    do {
      mode = cc1101->readReg(CC1101_MARCSTATE, CC1101_STATUS_REGISTER) & 0x1F;
      cca_cnt++;
      _delay_us(10); // IDLE TO RX takes 800us page 54 in datasheet
    } while ((mode != MARC_STATE_RX) && (cca_cnt < 200));
    if (cca_cnt >= 200) {
      cc1101->cmdStrobe(CC1101_SIDLE); // FORCE IDLE MODE
      return false;
    }
    //================= Send Packet to FIFO ==================
    cc1101->writeReg(CC1101_TXFIFO, sizeof(TAG::sRfTag));
    cc1101->writeBurstReg(CC1101_TXFIFO, (u08*) &tag, sizeof(TAG::sRfTag));
    mode = cc1101->readReg(CC1101_MARCSTATE, CC1101_STATUS_REGISTER) & 0x1F;
    cc1101->rssiValidWait();
    cc1101->cmdStrobe(CC1101_STX);
    while (BIT_IS_HI(READ_GD0,PIN_GD0))
      ;
    // ================= Wait 725 us for IDLE MODE ===========
    cca_cnt = 0;
    do {
      mode = cc1101->readReg(CC1101_MARCSTATE, CC1101_STATUS_REGISTER) & 0x1F;
      _delay_us(10); // TX to IDle with calibration - 725 us
    } while ((mode != MARC_STATE_IDLE));
    return true;
  }
  return false;
}
void spi_init2(u32_t bit_rate, u8_t spi_mode, bool_t data_order_lsb)
{
    u8_t  spcr;
    u32_t actual_bit_rate;
    u8_t  divisor;

    // Default values for SPCR
    spcr =  (0<<SPIE)|(1<<SPE)|(0<<DORD)|(1<<MSTR)
           |(0<<CPOL)|(0<<CPHA)|(0<<SPR1)|(0<<SPR0);

    // Set data order
    if(data_order_lsb == TRUE)
    {
        BIT_SET_HI(spcr, DORD);
    }

    // Set SPI Mode (0,1,2 or 3)
    spcr |= (spi_mode&3) << CPHA;

    // Select clock divisor that generates a bit rate closest to the desired bit rate (equal or less)
    actual_bit_rate = F_CPU;
    divisor = 1;
    do
    {
        actual_bit_rate >>= 1;
        divisor         <<= 1;
        // Stop if divisor reaches maximum
        if(divisor == 128)
        {
            break;
        }
    }
    while (actual_bit_rate > bit_rate);

    switch(divisor)
    {
    case 2 : spcr |= (0<<SPR1)|(0<<SPR0);
             BIT_SET_HI(SPSR, SPI2X);
             break;
    case 4 : spcr |= (0<<SPR1)|(0<<SPR0);
             BIT_SET_LO(SPSR, SPI2X);
             break;
    case 8 : spcr |= (0<<SPR1)|(1<<SPR0);
             BIT_SET_HI(SPSR, SPI2X);
             break;
    case 16 : spcr |= (0<<SPR1)|(1<<SPR0);
             BIT_SET_LO(SPSR, SPI2X);
             break;
    case 32 : spcr |= (1<<SPR1)|(0<<SPR0);
             BIT_SET_HI(SPSR, SPI2X);
             break;
    case 64 : spcr |= (1<<SPR1)|(0<<SPR0);
             BIT_SET_LO(SPSR, SPI2X);
             break;
    case 128 : spcr |= (1<<SPR1)|(1<<SPR0);
             BIT_SET_LO(SPSR, SPI2X);
             break;
    default:
             break;
    }

    SPCR = spcr;
}