void m68307_sim::write_pbdat(address_space &space, UINT16 data, UINT16 mem_mask)
{
int pc = space.device().safe_pc();
m68ki_cpu_core *m68k = m68k_get_safe_token(&space.device());
COMBINE_DATA(&m_pbdat);
if (m68k->m_m68307_portb_w)
{
m68k->m_m68307_portb_w(space, false, data, mem_mask);
}
else
{
logerror("%08x m68307_internal_sim_w %04x (%04x) (Port B (16-bit) Data Register - PBDAT)\n", pc, data,mem_mask);
}
}
void m68307_sim::write_licr1(UINT16 data, UINT16 mem_mask)
{
COMBINE_DATA(&m_licr1);
data = m_licr1;
logerror("m_licr1 value %04x : Details :\n", data);
logerror("int4ipl %01x\n", (data>>0)&7);
logerror("pir4 %01x\n", (data>>3)&1);
logerror("int3ipl %01x\n", (data>>4)&7);
logerror("pir3 %01x\n", (data>>7)&1);
logerror("int2ipl %01x\n", (data>>8)&7);
logerror("pir2 %01x\n", (data>>11)&1);
logerror("int1ipl %01x\n", (data>>12)&7);
logerror("pir1 %01x\n", (data>>15)&1);
logerror("\n");
}
static WRITE32_HANDLER( paletteram32_xRRRRRGGGGGBBBBB_dword_w )
{
int r,g,b;
COMBINE_DATA(&paletteram32[offset]);
r = (paletteram32[offset] & 0x7c000000) >> (10+16);
g = (paletteram32[offset] & 0x03e00000) >> (5+16);
b = (paletteram32[offset] & 0x001f0000) >> (0+16);
b = b << 3;
r = r << 3;
g = g << 3;
palette_set_color(offset,r,g,b);
}
static WRITE16_HANDLER( cpuB_ctrl_w )
{
overdriv_state *state = space->machine->driver_data<overdriv_state>();
COMBINE_DATA(&state->cpuB_ctrl);
if (ACCESSING_BITS_0_7)
{
/* bit 0 = enable sprite ROM reading */
k053246_set_objcha_line(state->k053246, (data & 0x01) ? ASSERT_LINE : CLEAR_LINE);
/* bit 1 used but unknown (irq enable?) */
/* other bits unused? */
}
}
static WRITE16_HANDLER( dbzcontrol_w )
{
dbz_state *state = space->machine->driver_data<dbz_state>();
/* bit 10 = enable '246 readback */
COMBINE_DATA(&state->control);
if (data & 0x400)
k053246_set_objcha_line(state->k053246, ASSERT_LINE);
else
k053246_set_objcha_line(state->k053246, CLEAR_LINE);
coin_counter_w(space->machine, 0, data & 1);
coin_counter_w(space->machine, 1, data & 2);
}
static WRITE16_HANDLER(dbzcontrol_w)
{
/* bit 10 = enable '246 readback */
COMBINE_DATA(&dbz2_control);
if (data & 0x400)
{
K053246_set_OBJCHA_line(ASSERT_LINE);
}
else
{
K053246_set_OBJCHA_line(CLEAR_LINE);
}
}
static WRITE32_HANDLER( superchs_input_w )
{
#if 0
{
char t[64];
static UINT32 mem[2];
COMBINE_DATA(&mem[offset]);
sprintf(t,"%08x %08x",mem[0],mem[1]);
//ui_popup(t);
}
#endif
switch (offset)
{
case 0x00:
{
if (ACCESSING_MSB32) /* $300000 is watchdog */
{
watchdog_reset_w(0,data >> 24);
}
if (ACCESSING_LSB32)
{
EEPROM_set_clock_line((data & 0x20) ? ASSERT_LINE : CLEAR_LINE);
EEPROM_write_bit(data & 0x40);
EEPROM_set_cs_line((data & 0x10) ? CLEAR_LINE : ASSERT_LINE);
return;
}
return;
}
/* there are 'vibration' control bits somewhere! */
case 0x01:
{
if (ACCESSING_MSB32)
{
coin_lockout_w(0,~data & 0x01000000);
coin_lockout_w(1,~data & 0x02000000);
coin_counter_w(0, data & 0x04000000);
coin_counter_w(1, data & 0x08000000);
coin_word=(data >> 16) &0xffff;
}
}
}
}
inline void megasys1_state::scrollram_w(offs_t offset, UINT16 data, UINT16 mem_mask, int which)
{
COMBINE_DATA(&m_scrollram[which][offset]);
if (offset < 0x40000/2 && m_tmap[which])
{
if (m_scroll_flag[which] & 0x10) /* tiles are 8x8 */
{
m_tmap[which]->mark_tile_dirty(offset );
}
else
{
m_tmap[which]->mark_tile_dirty(offset*4 + 0);
m_tmap[which]->mark_tile_dirty(offset*4 + 1);
m_tmap[which]->mark_tile_dirty(offset*4 + 2);
m_tmap[which]->mark_tile_dirty(offset*4 + 3);
}
}
}
INLINE void scrollram_w(int which, offs_t offset, UINT16 data, UINT16 mem_mask)
{
COMBINE_DATA(&megasys1_scrollram[which][offset]);
if (offset < 0x40000/2 && megasys1_tmap[which])
{
if (megasys1_scroll_flag[which] & 0x10) /* tiles are 8x8 */
{
tilemap_mark_tile_dirty(megasys1_tmap[which], offset );
}
else
{
tilemap_mark_tile_dirty(megasys1_tmap[which], offset*4 + 0);
tilemap_mark_tile_dirty(megasys1_tmap[which], offset*4 + 1);
tilemap_mark_tile_dirty(megasys1_tmap[which], offset*4 + 2);
tilemap_mark_tile_dirty(megasys1_tmap[which], offset*4 + 3);
}
}
}
void atarigt_state::atarigt_colorram_w(offs_t address, UINT16 data, UINT16 mem_mask)
{
UINT16 olddata;
/* update the raw data */
address = (address & 0x7ffff) / 2;
olddata = m_colorram[address];
COMBINE_DATA(&m_colorram[address]);
/* update the TRAM checksum */
if (address >= 0x10000 && address < 0x14000)
m_tram_checksum += m_colorram[address] - olddata;
/* update expanded MRAM */
else if (address >= 0x20000 && address < 0x28000)
{
m_expanded_mram[0 * MRAM_ENTRIES + (address & 0x7fff)] = (m_colorram[address] >> 8) << RSHIFT;
m_expanded_mram[1 * MRAM_ENTRIES + (address & 0x7fff)] = (m_colorram[address] & 0xff) << GSHIFT;
}
static WRITE16_HANDLER( latch_w )
{
batman_state *state = space->machine().driver_data<batman_state>();
int oldword = state->m_latch_data;
COMBINE_DATA(&state->m_latch_data);
/* bit 4 is connected to the /RESET pin on the 6502 */
if (state->m_latch_data & 0x0010)
cputag_set_input_line(space->machine(), "jsa", INPUT_LINE_RESET, CLEAR_LINE);
else
cputag_set_input_line(space->machine(), "jsa", INPUT_LINE_RESET, ASSERT_LINE);
/* alpha bank is selected by the upper 4 bits */
if ((oldword ^ state->m_latch_data) & 0x7000)
{
space->machine().primary_screen->update_partial(space->machine().primary_screen->vpos());
tilemap_mark_all_tiles_dirty(state->m_alpha_tilemap);
state->m_alpha_tile_bank = (state->m_latch_data >> 12) & 7;
}
static WRITE16_HANDLER( jpeg2_w )
{
COMBINE_DATA(&jpeg2);
{
int idx=find_data((int)jpeg2+(((int)jpeg1)<<16));
if(idx>=0)
{
jpeg_addr=gfxlookup[idx][0];
jpeg_w=gfxlookup[idx][2];
jpeg_h=gfxlookup[idx][3];
render_jpeg();
}
else
{
jpeg_addr=-1;
}
}
}
INLINE void scrollram_w(address_space *space, offs_t offset, UINT16 data, UINT16 mem_mask, int which)
{
megasys1_state *state = space->machine().driver_data<megasys1_state>();
COMBINE_DATA(&state->m_scrollram[which][offset]);
if (offset < 0x40000/2 && state->m_tmap[which])
{
if (state->m_scroll_flag[which] & 0x10) /* tiles are 8x8 */
{
tilemap_mark_tile_dirty(state->m_tmap[which], offset );
}
else
{
tilemap_mark_tile_dirty(state->m_tmap[which], offset*4 + 0);
tilemap_mark_tile_dirty(state->m_tmap[which], offset*4 + 1);
tilemap_mark_tile_dirty(state->m_tmap[which], offset*4 + 2);
tilemap_mark_tile_dirty(state->m_tmap[which], offset*4 + 3);
}
}
}
static WRITE16_HANDLER( jpeg2_w )
{
sliver_state *state = space->machine().driver_data<sliver_state>();
int idx;
COMBINE_DATA(&state->m_jpeg2);
idx = find_data((int)state->m_jpeg2 + (((int)state->m_jpeg1) << 16));
if (idx >= 0)
{
state->m_jpeg_addr = gfxlookup[idx][0];
state->m_jpeg_w = gfxlookup[idx][2];
state->m_jpeg_h = gfxlookup[idx][3];
render_jpeg(space->machine());
}
else
{
state->m_jpeg_addr = -1;
}
}
static WRITE16_HANDLER( fifo_data_w )
{
if(tmp_counter<8)
{
COMBINE_DATA(&tempbuf[tmp_counter]);
tmp_counter++;
if(tmp_counter==8) // copy 8 bytes to fifo, every byte should be copied directly, but it's easier to copy whole commands
{
do
{
fifo[fptr++]=tempbuf[8-tmp_counter];
if(fptr>(FIFO_SIZE-1))
{
fptr=FIFO_SIZE-1;
}
}
while(--tmp_counter>0);
}
}
}
static void i82371ab_pci_ide_w(device_t *busdevice, device_t *device, int offset, UINT32 data, UINT32 mem_mask)
{
i82371ab_state *i82371ab = get_safe_token(device);
logerror("i82371ab_pci_ide_w, offset = %02x, data = %08x, mem_mask = %08x\n", offset, data, mem_mask);
switch (offset)
{
case 0x04:
COMBINE_DATA(&i82371ab->regs[1][offset]);
/* clear reserved bits */
i82371ab->regs[1][offset] &= 0x00000005;
/* set new status */
i82371ab->regs[1][offset] |= 0x02800000;
break;
}
}
static WRITE16_HANDLER( ddragon3_io_w )
{
ddragon3_state *state = space->machine->driver_data<ddragon3_state>();
COMBINE_DATA(&state->io_reg[offset]);
switch (offset)
{
case 0:
state->vreg = state->io_reg[0];
break;
case 1: /* soundlatch_w */
soundlatch_w(space, 1, state->io_reg[1] & 0xff);
cpu_set_input_line(state->audiocpu, INPUT_LINE_NMI, PULSE_LINE );
break;
case 2:
/* this gets written to on startup and at the end of IRQ6
** possibly trigger IRQ on sound CPU
*/
cpu_set_input_line(state->maincpu, 6, CLEAR_LINE);
break;
case 3:
/* this gets written to on startup,
** and at the end of IRQ5 (input port read) */
cpu_set_input_line(state->maincpu, 5, CLEAR_LINE);
break;
case 4:
/* this gets written to at the end of IRQ6 only */
cpu_set_input_line(state->maincpu, 6, CLEAR_LINE);
break;
default:
logerror("OUTPUT 1400[%02x] %08x, pc=%06x \n", offset, (unsigned)data, cpu_get_pc(space->cpu) );
break;
}
}
static WRITE16_HANDLER(io_data_w)
{
if(io_offset<IO_SIZE)
{
int tmpx,tmpy;
COMBINE_DATA(&io_reg[io_offset]);
tmpy=io_reg[0x1a]+(io_reg[0x1b]<<8)-io_reg[0x20]; //0x20 ???
tmpx=io_reg[0x1e]+(io_reg[0x1f]<<8);
if(tmpy!=jpeg_y || tmpx!=jpeg_x)
{
jpeg_x=tmpx;
jpeg_y=tmpy;
render_jpeg();
}
}
else
{
logerror("I/O access out of range: %x\n", io_offset);
}
}
static WRITE32_HANDLER( ps_intc_w )
{
pockstat_state *state = space->machine().driver_data<pockstat_state>();
switch(offset)
{
case 0x0000/4:
verboselog(space->machine(), 0, "ps_intc_w: Held Interrupt (Invalid Write) = %08x & %08x\n", data, mem_mask );
break;
case 0x0004/4:
verboselog(space->machine(), 0, "ps_intc_w: Interrupt Status (Invalid Write) = %08x & %08x\n", data, mem_mask );
break;
case 0x0008/4:
verboselog(space->machine(), 0, "ps_intc_w: Interrupt Enable = %08x & %08x\n", data, mem_mask );
state->m_intc_regs.enable |= data;
//COMBINE_DATA(&state->m_intc_regs.enable);
//state->m_intc_regs.status &= state->m_intc_regs.enable;
//state->m_intc_regs.hold &= state->m_intc_regs.enable;
ps_intc_set_interrupt_line(space->machine(), 0, 0);
break;
case 0x000c/4:
verboselog(space->machine(), 0, "ps_intc_w: Interrupt Mask = %08x & %08x\n", data, mem_mask );
state->m_intc_regs.enable &= ~data;
COMBINE_DATA(&state->m_intc_regs.mask);
//state->m_intc_regs.status &= state->m_intc_regs.enable;
//state->m_intc_regs.hold &= state->m_intc_regs.enable;
ps_intc_set_interrupt_line(space->machine(), 0, 0);
break;
case 0x0010/4:
verboselog(space->machine(), 0, "ps_intc_w: Interrupt Acknowledge = %08x & %08x\n", data, mem_mask );
state->m_intc_regs.hold &= ~data;
state->m_intc_regs.status &= ~data;
ps_intc_set_interrupt_line(space->machine(), 0, 0);
//COMBINE_DATA(&state->m_intc_regs.acknowledge);
break;
default:
verboselog(space->machine(), 0, "ps_intc_w: Unknown Register %08x = %08x & %08x\n", 0x0a000000 + (offset << 2), data, mem_mask );
break;
}
}
void m68307_sim::write_licr2(UINT16 data, UINT16 mem_mask)
{
COMBINE_DATA(&m_licr2);
UINT16 newdata = m_licr2;
logerror("m_licr2 value %04x : Details :\n", newdata);
logerror("int8ipl %01x\n", (newdata>>0)&7);
logerror("pir8 %01x\n", (newdata>>3)&1);
logerror("int7ipl %01x\n", (newdata>>4)&7);
logerror("pir7 %01x\n", (newdata>>7)&1);
logerror("int6ipl %01x\n", (newdata>>8)&7);
logerror("pir6 %01x\n", (newdata>>11)&1);
logerror("int5ipl %01x\n", (newdata>>12)&7);
logerror("pir5 %01x\n", (newdata>>15)&1);
logerror("\n");
if (data & 0x0008) m_licr2 = m_licr2 & ~0x0008;
if (data & 0x0080) m_licr2 = m_licr2 & ~0x0080;
if (data & 0x0800) m_licr2 = m_licr2 & ~0x0800;
if (data & 0x8000) m_licr2 = m_licr2 & ~0x8000;
}
static WRITE32_HANDLER( smbus_w )
{
COMBINE_DATA(smbusst.words);
if ((offset == 0) && (mem_mask == 0xff)) // 0 smbus status
smbusst.status &= ~data;
if ((offset == 0) && (mem_mask == 0xff0000)) // 2 smbus control
{
data=data>>16;
smbusst.control = data;
if ((smbusst.control & 6) == 2)
{
if (smbusst.devices[smbusst.address & 127]) {
if (smbusst.rw == 0) {
smbusst.devices[smbusst.address & 127](smbusst.command,smbusst.rw,smbusst.data);
}
else {
smbusst.data=smbusst.devices[smbusst.address & 127](smbusst.command,smbusst.rw,smbusst.data);
}
}
smbusst.status |= 0x10;
}
}
static WRITE16_HANDLER( fifo_data_w )
{
sliver_state *state = space->machine().driver_data<sliver_state>();
if (state->m_tmp_counter < 8)
{
COMBINE_DATA(&state->m_tempbuf[state->m_tmp_counter]);
state->m_tmp_counter++;
if (state->m_tmp_counter == 8) // copy 8 bytes to fifo, every byte should be copied directly, but it's easier to copy whole commands
{
do
{
state->m_fifo[state->m_fptr++]=state->m_tempbuf[8-state->m_tmp_counter];
if (state->m_fptr > (FIFO_SIZE - 1))
{
state->m_fptr=FIFO_SIZE-1;
}
}
while (--state->m_tmp_counter > 0);
}
}
}
ADDRESS_MAP_END
WRITE16_MEMBER(namcofl_state::mcu_shared_w)
{
// HACK! Many games data ROM routines redirect the vector from the sound command read to an RTS.
// This needs more investigation. nebulray and vshoot do NOT do this.
// Timers A2 and A3 are set up in "external input counter" mode, this may be related.
#if 0
if ((offset == 0x647c/2) && (data != 0))
{
data = 0xd2f6;
}
#endif
COMBINE_DATA(&m_shareram[offset]);
// C75 BIOS has a very short window on the CPU sync signal, so immediately let the i960 at it
if ((offset == 0x6000/2) && (data & 0x80))
{
space.device().execute().yield();
}
}
static WRITE32_HANDLER( control_w )
{
// bit $80000000 = BSMT access/ROM read
// bit $20000000 = toggled every 64 IRQ4's
// bit $10000000 = ????
// bit $00800000 = EEPROM data
// bit $00400000 = EEPROM clock
// bit $00200000 = EEPROM enable (on 1)
COMBINE_DATA(&control_data);
/* handle EEPROM I/O */
if (!(mem_mask & 0x00ff0000))
{
EEPROM_write_bit(data & 0x00800000);
EEPROM_set_cs_line((data & 0x00200000) ? CLEAR_LINE : ASSERT_LINE);
EEPROM_set_clock_line((data & 0x00400000) ? ASSERT_LINE : CLEAR_LINE);
}
/* log any unknown bits */
if (data & 0x4f1fffff)
logerror("%08X: control_w = %08X & %08X\n", activecpu_get_previouspc(), data, ~mem_mask);
}
static WRITE16_HANDLER( ddragon3_io16_w )
{
static UINT16 reg[8];
COMBINE_DATA(®[offset]);
switch (offset)
{
case 0:
ddragon3_vreg = reg[0];
break;
case 1: /* soundlatch_w */
soundlatch_w(1,reg[1]&0xff);
cpunum_set_input_line( 1, INPUT_LINE_NMI, PULSE_LINE );
break;
case 2:
/* this gets written to on startup and at the end of IRQ6
** possibly trigger IRQ on sound CPU
*/
break;
case 3:
/* this gets written to on startup,
** and at the end of IRQ5 (input port read) */
break;
case 4:
/* this gets written to at the end of IRQ6 only */
break;
default:
logerror("OUTPUT 1400[%02x] %08x, pc=%06x \n", offset,(unsigned)data, activecpu_get_pc() );
break;
}
}
static WRITE16_HANDLER( protection_w )
{
COMBINE_DATA(prot+offset);
if (offset == 1)
{
UINT32 cmd = (prot[0] << 16) | prot[1];
switch (cmd >> 24)
{
case 0x64:
{
UINT32 param1 = (program_read_word(cmd & 0xffffff) << 16)
| program_read_word((cmd & 0xffffff) + 2);
UINT32 param2 = (program_read_word((cmd & 0xffffff) + 4) << 16)
| program_read_word((cmd & 0xffffff) + 6);
switch (param1 >> 24)
{
case 0x22:
{
int size = param2 >> 24;
param1 &= 0xffffff;
param2 &= 0xffffff;
while(size >= 0)
{
program_write_word(param2, program_read_word(param1));
param1 += 2;
param2 += 2;
size--;
}
break;
}
}
break;
}
}
}
static WRITE16_HANDLER( galaxi_500004_w )
{
galaxi_state *state = space->machine().driver_data<galaxi_state>();
if (ACCESSING_BITS_0_7)
{
/*
- Lbits -
7654 3210
=========
---- ---x Hold1 lamp.
---- --x- Hold2 lamp.
---- -x-- Hold3 lamp.
---- x--- Hold4 lamp.
---x ---- Hold5 lamp.
--x- ---- Start lamp.
-x-- ---- Payout.
*/
output_set_lamp_value(1, (data & 1)); /* Lamp 1 - HOLD 1 */
output_set_lamp_value(2, (data >> 1) & 1); /* Lamp 2 - HOLD 2 */
output_set_lamp_value(3, (data >> 2) & 1); /* Lamp 3 - HOLD 3 */
output_set_lamp_value(4, (data >> 3) & 1); /* Lamp 4 - HOLD 4 */
output_set_lamp_value(5, (data >> 4) & 1); /* Lamp 5 - HOLD 5 */
output_set_lamp_value(6, (data >> 5) & 1); /* Lamp 6 - START */
}
if (ACCESSING_BITS_8_15)
{
state->m_ticket = data & 0x0100;
state->m_hopper = data & 0x1000;
coin_counter_w(space->machine(), 0, data & 0x2000); // coins
}
COMBINE_DATA(&state->m_out[2]);
show_out(space->machine());
}
static WRITE16_HANDLER( protection_w )
{
asterix_state *state = (asterix_state *)space->machine->driver_data;
COMBINE_DATA(state->prot + offset);
if (offset == 1)
{
UINT32 cmd = (state->prot[0] << 16) | state->prot[1];
switch (cmd >> 24)
{
case 0x64:
{
UINT32 param1 = (memory_read_word(space, cmd & 0xffffff) << 16) | memory_read_word(space, (cmd & 0xffffff) + 2);
UINT32 param2 = (memory_read_word(space, (cmd & 0xffffff) + 4) << 16) | memory_read_word(space, (cmd & 0xffffff) + 6);
switch (param1 >> 24)
{
case 0x22:
{
int size = param2 >> 24;
param1 &= 0xffffff;
param2 &= 0xffffff;
while(size >= 0)
{
memory_write_word(space, param2, memory_read_word(space, param1));
param1 += 2;
param2 += 2;
size--;
}
break;
}
}
break;
}
}
}
static WRITE32_HANDLER( speedup_w )
{
COMBINE_DATA(speedup_data);
/* see if the PC matches */
if ((activecpu_get_previouspc() & 0x1fffffff) == speedup_pc)
{
UINT32 curr_cycles = activecpu_gettotalcycles();
/* if less than 50 cycles from the last time, count it */
if (curr_cycles - last_cycles < 50)
{
loop_count++;
/* more than 2 in a row and we spin */
if (loop_count > 2)
cpu_spinuntil_int();
}
else
loop_count = 0;
last_cycles = curr_cycles;
}
}
static WRITE16_HANDLER(io_data_w)
{
sliver_state *state = space->machine().driver_data<sliver_state>();
if (state->m_io_offset < IO_SIZE)
{
int tmpx, tmpy;
COMBINE_DATA(&state->m_io_reg[state->m_io_offset]);
tmpy = state->m_io_reg[0x1a] + (state->m_io_reg[0x1b] << 8) - state->m_io_reg[0x20]; //0x20 ???
tmpx = state->m_io_reg[0x1e] + (state->m_io_reg[0x1f] << 8);
if (tmpy != state->m_jpeg_y || tmpx != state->m_jpeg_x)
{
state->m_jpeg_x = tmpx;
state->m_jpeg_y = tmpy;
render_jpeg(space->machine());
}
}
else
{
logerror("I/O access out of range: %x\n", state->m_io_offset);
}
}
