void __init cp_intc_init(void) { unsigned long num_irq = davinci_soc_info.intc_irq_num; u8 *irq_prio = davinci_soc_info.intc_irq_prios; u32 *host_map = davinci_soc_info.intc_host_map; unsigned num_reg = BITS_TO_LONGS(num_irq); int i; davinci_intc_type = DAVINCI_INTC_TYPE_CP_INTC; davinci_intc_base = ioremap(davinci_soc_info.intc_base, SZ_8K); if (WARN_ON(!davinci_intc_base)) return; cp_intc_write(0, CP_INTC_GLOBAL_ENABLE); /* Disable all host interrupts */ cp_intc_write(0, CP_INTC_HOST_ENABLE(0)); /* Disable system interrupts */ for (i = 0; i < num_reg; i++) cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i)); /* Set to normal mode, no nesting, no priority hold */ cp_intc_write(0, CP_INTC_CTRL); cp_intc_write(0, CP_INTC_HOST_CTRL); /* Clear system interrupt status */ for (i = 0; i < num_reg; i++) cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i)); /* Enable nIRQ (what about nFIQ?) */ cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); /* * Priority is determined by host channel: lower channel number has * higher priority i.e. channel 0 has highest priority and channel 31 * had the lowest priority. */ num_reg = (num_irq + 3) >> 2; /* 4 channels per register */ if (irq_prio) { unsigned j, k; u32 val; for (k = i = 0; i < num_reg; i++) { for (val = j = 0; j < 4; j++, k++) { val >>= 8; if (k < num_irq) val |= irq_prio[k] << 24; } cp_intc_write(val, CP_INTC_CHAN_MAP(i)); } } else { /* * Default everything to channel 15 if priority not specified. * Note that channel 0-1 are mapped to nFIQ and channels 2-31 * are mapped to nIRQ. */ for (i = 0; i < num_reg; i++)
void __init cp_intc_init(void __iomem *base, unsigned short num_irq, u8 *irq_prio) { unsigned num_reg = BITS_TO_LONGS(num_irq); int i; cp_intc_base = base; cp_intc_write(0, CP_INTC_GLOBAL_ENABLE); /* Disable all host interrupts */ cp_intc_write(0, CP_INTC_HOST_ENABLE(0)); /* Disable system interrupts */ for (i = 0; i < num_reg; i++) cp_intc_write(~0, CP_INTC_SYS_ENABLE_CLR(i)); /* Set to normal mode, no nesting, no priority hold */ cp_intc_write(0, CP_INTC_CTRL); cp_intc_write(0, CP_INTC_HOST_CTRL); /* Clear system interrupt status */ for (i = 0; i < num_reg; i++) cp_intc_write(~0, CP_INTC_SYS_STAT_CLR(i)); /* Enable nIRQ (what about nFIQ?) */ cp_intc_write(1, CP_INTC_HOST_ENABLE_IDX_SET); /* * Priority is determined by host channel: lower channel number has * higher priority i.e. channel 0 has highest priority and channel 31 * had the lowest priority. */ num_reg = (num_irq + 3) >> 2; /* 4 channels per register */ if (irq_prio) { unsigned j, k; u32 val; for (k = i = 0; i < num_reg; i++) { for (val = j = 0; j < 4; j++, k++) { val >>= 8; if (k < num_irq) val |= irq_prio[k] << 24; } // printk("[0x%08X] = 0x%08X\n", CP_INTC_CHAN_MAP(i), val); cp_intc_write(val, CP_INTC_CHAN_MAP(i)); } } else { /* * Default everything to channel 15 if priority not specified. * Note that channel 0-1 are mapped to nFIQ and channels 2-31 * are mapped to nIRQ. */ for (i = 0; i < num_reg; i++)