static u32 calc_residency(struct drm_device *dev, i915_reg_t reg) { struct drm_i915_private *dev_priv = dev->dev_private; u64 raw_time; /* 32b value may overflow during fixed point math */ u64 units = 128ULL, div = 100000ULL; u32 ret; if (!intel_enable_rc6(dev)) return 0; intel_runtime_pm_get(dev_priv); /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { units = 1; div = dev_priv->czclk_freq; if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH) units <<= 8; } else if (IS_BROXTON(dev)) { units = 1; div = 1200; /* 833.33ns */ } raw_time = I915_READ(reg) * units; ret = DIV_ROUND_UP_ULL(raw_time, div); intel_runtime_pm_put(dev_priv); return ret; }
/* Returns MBps of read/writes for the sampling window. */ static unsigned int bytes_to_mbps(long long bytes, unsigned int us) { bytes *= USEC_PER_SEC; do_div(bytes, us); bytes = DIV_ROUND_UP_ULL(bytes, SZ_1M); return bytes; }
static long pl111_clk_div_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { int div = pl111_clk_div_choose_div(hw, rate, prate, true); return DIV_ROUND_UP_ULL(*prate, div); }
static void params_from_rate(unsigned long requested_rate, unsigned long parent_rate, unsigned int *sdm, unsigned int *n2, u8 flags) { uint64_t div = parent_rate; uint64_t frac = do_div(div, requested_rate); frac *= SDM_DEN; if (flags & CLK_MESON_MPLL_ROUND_CLOSEST) *sdm = DIV_ROUND_CLOSEST_ULL(frac, requested_rate); else *sdm = DIV_ROUND_UP_ULL(frac, requested_rate); if (*sdm == SDM_DEN) { *sdm = 0; div += 1; } if (div < N2_MIN) { *n2 = N2_MIN; *sdm = 0; } else if (div > N2_MAX) { *n2 = N2_MAX; *sdm = SDM_DEN - 1; } else { *n2 = div; } }
static int pl111_clk_div_choose_div(struct clk_hw *hw, unsigned long rate, unsigned long *prate, bool set_parent) { int best_div = 1, div; struct clk_hw *parent = clk_hw_get_parent(hw); unsigned long best_prate = 0; unsigned long best_diff = ~0ul; int max_div = (1 << (TIM2_PCD_LO_BITS + TIM2_PCD_HI_BITS)) - 1; for (div = 1; div < max_div; div++) { unsigned long this_prate, div_rate, diff; if (set_parent) this_prate = clk_hw_round_rate(parent, rate * div); else this_prate = *prate; div_rate = DIV_ROUND_UP_ULL(this_prate, div); diff = abs(rate - div_rate); if (diff < best_diff) { best_div = div; best_diff = diff; best_prate = this_prate; } } *prate = best_prate; return best_div; }
unsigned int beats_to_mbps(long long beats, unsigned int us) { beats *= USEC_PER_SEC; beats *= bytes_per_beat; do_div(beats, us); beats = DIV_ROUND_UP_ULL(beats, SZ_1M); return beats; }
static long rate_from_params(unsigned long parent_rate, unsigned int sdm, unsigned int n2) { unsigned long divisor = (SDM_DEN * n2) + sdm; if (n2 < N2_MIN) return -EINVAL; return DIV_ROUND_UP_ULL((u64)parent_rate * SDM_DEN, divisor); }
static u32 calc_residency(struct drm_device *dev, const u32 reg) { struct drm_i915_private *dev_priv = dev->dev_private; u64 raw_time; /* 32b value may overflow during fixed point math */ if (!intel_enable_rc6(dev)) return 0; raw_time = I915_READ(reg) * 128ULL; return DIV_ROUND_UP_ULL(raw_time, 100000); }
static unsigned long pl111_clk_div_recalc_rate(struct clk_hw *hw, unsigned long prate) { struct pl111_drm_dev_private *priv = container_of(hw, struct pl111_drm_dev_private, clk_div); u32 tim2 = readl(priv->regs + CLCD_TIM2); int div; if (tim2 & TIM2_BCD) return prate; div = tim2 & TIM2_PCD_LO_MASK; div |= (tim2 & TIM2_PCD_HI_MASK) >> (TIM2_PCD_HI_SHIFT - TIM2_PCD_LO_BITS); div += 2; return DIV_ROUND_UP_ULL(prate, div); }
static void imx_ocotp_set_imx7_timing(struct ocotp_priv *priv) { unsigned long clk_rate = 0; u64 fsource, strobe_prog; u32 timing = 0; /* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1 * 6.4.3.3 */ clk_rate = clk_get_rate(priv->clk); fsource = DIV_ROUND_UP_ULL((u64)clk_rate * DEF_FSOURCE, NSEC_PER_SEC) + 1; strobe_prog = DIV_ROUND_CLOSEST_ULL((u64)clk_rate * DEF_STROBE_PROG, NSEC_PER_SEC) + 1; timing = strobe_prog & 0x00000FFF; timing |= (fsource << 12) & 0x000FF000; writel(timing, priv->base + IMX_OCOTP_ADDR_TIMING); }
/* Returns MBps of read/writes for the sampling window. */ static int mon_get_mbps(int n, u32 start_val, unsigned int us) { u32 overflow, count; long long beats; count = get_l2_indirect_reg(L2PMnEVCNTR(n)); overflow = get_l2_indirect_reg(L2PMOVSR); if (overflow & BIT(n)) beats = 0xFFFFFFFF - start_val + count; else beats = count - start_val; beats *= USEC_PER_SEC; beats *= bytes_per_beat; do_div(beats, us); beats = DIV_ROUND_UP_ULL(beats, MBYTE); pr_debug("EV%d ov: %x, cnt: %x\n", n, overflow, count); return beats; }
static unsigned long apds9300_calculate_lux(u16 ch0, u16 ch1) { unsigned long lux, tmp; /* avoid division by zero */ if (ch0 == 0) return 0; tmp = DIV_ROUND_UP(ch1 * 100, ch0); if (tmp <= 52) { lux = 3150 * ch0 - (unsigned long)DIV_ROUND_UP_ULL(ch0 * apds9300_lux_ratio[tmp] * 5930ull, 1000); } else if (tmp <= 65) { lux = 2290 * ch0 - 2910 * ch1; } else if (tmp <= 80) { lux = 1570 * ch0 - 1800 * ch1; } else if (tmp <= 130) { lux = 338 * ch0 - 260 * ch1; } else { lux = 0; } return lux / 100000; }
/* * The realtime counter also called master counter, is a free-running * counter, which is related to real time. It produces the count used * by the CPU local timer peripherals in the MPU cluster. The timer counts * at a rate of 6.144 MHz. Because the device operates on different clocks * in different power modes, the master counter shifts operation between * clocks, adjusting the increment per clock in hardware accordingly to * maintain a constant count rate. */ static void __init realtime_counter_init(void) { void __iomem *base; static struct clk *sys_clk; unsigned long rate; unsigned int reg; unsigned long long num, den; base = ioremap(REALTIME_COUNTER_BASE, SZ_32); if (!base) { pr_err("%s: ioremap failed\n", __func__); return; } sys_clk = clk_get(NULL, "sys_clkin"); if (IS_ERR(sys_clk)) { pr_err("%s: failed to get system clock handle\n", __func__); iounmap(base); return; } rate = clk_get_rate(sys_clk); if (soc_is_dra7xx()) { /* * Errata i856 says the 32.768KHz crystal does not start at * power on, so the CPU falls back to an emulated 32KHz clock * based on sysclk / 610 instead. This causes the master counter * frequency to not be 6.144MHz but at sysclk / 610 * 375 / 2 * (OR sysclk * 75 / 244) * * This affects at least the DRA7/AM572x 1.0, 1.1 revisions. * Of course any board built without a populated 32.768KHz * crystal would also need this fix even if the CPU is fixed * later. * * Either case can be detected by using the two speedselect bits * If they are not 0, then the 32.768KHz clock driving the * coarse counter that corrects the fine counter every time it * ticks is actually rate/610 rather than 32.768KHz and we * should compensate to avoid the 570ppm (at 20MHz, much worse * at other rates) too fast system time. */ reg = omap_ctrl_readl(DRA7_CTRL_CORE_BOOTSTRAP); if (reg & DRA7_SPEEDSELECT_MASK) { num = 75; den = 244; goto sysclk1_based; } } /* Numerator/denumerator values refer TRM Realtime Counter section */ switch (rate) { case 12000000: num = 64; den = 125; break; case 13000000: num = 768; den = 1625; break; case 19200000: num = 8; den = 25; break; case 20000000: num = 192; den = 625; break; case 26000000: num = 384; den = 1625; break; case 27000000: num = 256; den = 1125; break; case 38400000: default: /* Program it for 38.4 MHz */ num = 4; den = 25; break; } sysclk1_based: /* Program numerator and denumerator registers */ reg = __raw_readl(base + INCREMENTER_NUMERATOR_OFFSET) & NUMERATOR_DENUMERATOR_MASK; reg |= num; __raw_writel(reg, base + INCREMENTER_NUMERATOR_OFFSET); reg = __raw_readl(base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET) & NUMERATOR_DENUMERATOR_MASK; reg |= den; __raw_writel(reg, base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); arch_timer_freq = DIV_ROUND_UP_ULL(rate * num, den); set_cntfreq(); iounmap(base); }